int ase_smartmips;
int ase_dsp;
int ase_dspr2;
+ int ase_eva;
int ase_mt;
int ase_mcu;
int ase_virt;
static struct mips_set_options mips_opts =
{
/* isa */ ISA_UNKNOWN, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
- /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
- /* ase_mcu */ -1, /* ase_virt */ -1, /* mips16 */ -1,/* micromips */ -1,
+ /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1,
+ /* ase_eva */ -1, /* ase_mt */ -1, /* ase_mcu */ -1,
+ /* ase_virt */ -1, /* mips16 */ -1, /* micromips */ -1,
/* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0,
/* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* gp32 */ 0,
/* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
|| mips_opts.isa == ISA_MIPS64R2 \
|| mips_opts.micromips)
+/* True if -meva was passed or implied by arguments passed on the
+ command line (e.g., by -march). */
+static int file_ase_eva;
+
+#define ISA_SUPPORTS_EVA_ASE (mips_opts.isa == ISA_MIPS32R2 \
+ || mips_opts.isa == ISA_MIPS64R2 \
+ || mips_opts.micromips)
+
/* True if -mmt was passed or implied by arguments passed on the
command line (e.g., by -march). */
static int file_ase_mt;
static int file_ase_virt;
#define ISA_SUPPORTS_VIRT_ASE (mips_opts.isa == ISA_MIPS32R2 \
- || mips_opts.isa == ISA_MIPS64R2)
+ || mips_opts.isa == ISA_MIPS64R2 \
+ || mips_opts.micromips)
-#define ISA_SUPPORTS_VIRT64_ASE (mips_opts.isa == ISA_MIPS64R2)
+#define ISA_SUPPORTS_VIRT64_ASE (mips_opts.isa == ISA_MIPS64R2 \
+ || (mips_opts.micromips \
+ && ISA_HAS_64BIT_REGS (mips_opts.isa)))
/* The argument of the -march= flag. The architecture we are assembling. */
static int file_mips_arch = CPU_UNKNOWN;
#define IS_SEXT_12BIT_NUM(x) \
(((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
+/* Is the given value a sign-extended 9-bit value? */
+#define IS_SEXT_9BIT_NUM(x) \
+ (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
+
/* Is the given value a zero-extended 32-bit value? Or a negated one? */
#define IS_ZEXT_32BIT_NUM(x) \
(((x) &~ (offsetT) 0xffffffff) == 0 \
static void s_gpvalue (int);
static void s_gpword (int);
static void s_gpdword (int);
+static void s_ehword (int);
static void s_cpadd (int);
static void s_insn (int);
static void md_obj_begin (void);
struct mips_cpu_info
{
const char *name; /* CPU or ISA name. */
- int flags; /* ASEs available, or ISA flag. */
+ int flags; /* MIPS_CPU_* flags. */
+ int ase; /* Set of ASEs implemented by the CPU. */
int isa; /* ISA level. */
int cpu; /* CPU number (default CPU if ISA). */
};
#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
-#define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
-#define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
-#define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
-#define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
-#define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
-#define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
-#define MIPS_CPU_ASE_MCU 0x0080 /* CPU implements MCU ASE */
-#define MIPS_CPU_ASE_VIRT 0x0100 /* CPU implements Virtualization ASE */
static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
{"gpvalue", s_gpvalue, 0},
{"gpword", s_gpword, 0},
{"gpdword", s_gpdword, 0},
+ {"ehword", s_ehword, 0},
{"cpadd", s_cpadd, 0},
{"insn", s_insn, 0},
return ok && reglist != 0;
}
-/* Return TRUE if opcode MO is valid on the currently selected ISA and
- architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
+/* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
+ and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
static bfd_boolean
is_opcode_valid (const struct mips_opcode *mo)
{
int isa = mips_opts.isa;
+ int ase = 0;
int fp_s, fp_d;
if (mips_opts.ase_mdmx)
- isa |= INSN_MDMX;
+ ase |= ASE_MDMX;
if (mips_opts.ase_dsp)
- isa |= INSN_DSP;
+ ase |= ASE_DSP;
if (mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
- isa |= INSN_DSP64;
+ ase |= ASE_DSP64;
if (mips_opts.ase_dspr2)
- isa |= INSN_DSPR2;
+ ase |= ASE_DSPR2;
+ if (mips_opts.ase_eva)
+ ase |= ASE_EVA;
if (mips_opts.ase_mt)
- isa |= INSN_MT;
+ ase |= ASE_MT;
if (mips_opts.ase_mips3d)
- isa |= INSN_MIPS3D;
+ ase |= ASE_MIPS3D;
if (mips_opts.ase_smartmips)
- isa |= INSN_SMARTMIPS;
+ ase |= ASE_SMARTMIPS;
if (mips_opts.ase_mcu)
- isa |= INSN_MCU;
+ ase |= ASE_MCU;
if (mips_opts.ase_virt)
- isa |= INSN_VIRT;
+ ase |= ASE_VIRT;
if (mips_opts.ase_virt && ISA_SUPPORTS_VIRT64_ASE)
- isa |= INSN_VIRT64;
+ ase |= ASE_VIRT64;
- if (!opcode_is_member (mo, isa, mips_opts.arch))
+ if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
return FALSE;
/* Check whether the instruction or macro requires single-precision or
static bfd_boolean
is_opcode_valid_16 (const struct mips_opcode *mo)
{
- return opcode_is_member (mo, mips_opts.isa, mips_opts.arch);
+ return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
}
/* Return TRUE if the size of the microMIPS opcode MO matches one
branch_disp = method == APPEND_SWAP ? insn_length (history) : 0;
#ifdef OBJ_ELF
- /* The value passed to dwarf2_emit_insn is the distance between
- the beginning of the current instruction and the address that
- should be recorded in the debug tables. This is normally the
- current address.
-
- For MIPS16/microMIPS debug info we want to use ISA-encoded
- addresses, so we use -1 for an address higher by one than the
- current one.
-
- If the instruction produced is a branch that we will swap with
- the preceding instruction, then we add the displacement by which
- the branch will be moved backwards. This is more appropriate
- and for MIPS16/microMIPS code also prevents a debugger from
- placing a breakpoint in the middle of the branch (and corrupting
- code if software breakpoints are used). */
- dwarf2_emit_insn ((HAVE_CODE_COMPRESSION ? -1 : 0) + branch_disp);
+ dwarf2_emit_insn (0);
+ /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
+ so "move" the instruction address accordingly.
+
+ Also, it doesn't seem appropriate for the assembler to reorder .loc
+ entries. If this instruction is a branch that we are going to swap
+ with the previous instruction, the two instructions should be
+ treated as a unit, and the debug information for both instructions
+ should refer to the start of the branch sequence. Using the
+ current position is certainly wrong when swapping a 32-bit branch
+ and a 16-bit delay slot, since the current position would then be
+ in the middle of a branch. */
+ dwarf2_move_insn ((HAVE_CODE_COMPRESSION ? 1 : 0) - branch_disp);
#endif
relax32 = (mips_relax_branch
out that the branch was out-of-range, we'll get an error. */
&& !mips_opts.warn_about_macros
&& (mips_opts.at || mips_pic == NO_PIC)
- /* Don't relax BPOSGE32/64 as they have no complementing
- branches. */
- && !(ip->insn_mo->membership & (INSN_DSP64 | INSN_DSP)));
+ /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
+ as they have no complementing branches. */
+ && !(ip->insn_mo->ase & (ASE_MIPS3D | ASE_DSP64 | ASE_DSP)));
if (!HAVE_CODE_COMPRESSION
&& address_expr
INSERT_OPERAND (0, SEQI, insn, va_arg (args, int));
continue;
+ case 'j':
+ INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, insn, va_arg (args, int));
+ continue;
+
default:
abort ();
}
const char *fmt;
int likely = 0;
int coproc = 0;
- int off12 = 0;
+ int offbits = 16;
int call = 0;
int jals = 0;
int dbl = 0;
int ust = 0;
int lp = 0;
int ab = 0;
- int off0 = 0;
int off;
offsetT maxnum;
bfd_reloc_code_real_type r;
break;
+ case M_LBUE_AB:
+ ab = 1;
+ case M_LBUE_OB:
+ s = "lbue";
+ fmt = "t,+j(b)";
+ offbits = 9;
+ goto ld_st;
+ case M_LHUE_AB:
+ ab = 1;
+ case M_LHUE_OB:
+ s = "lhue";
+ fmt = "t,+j(b)";
+ offbits = 9;
+ goto ld_st;
+ case M_LBE_AB:
+ ab = 1;
+ case M_LBE_OB:
+ s = "lbe";
+ fmt = "t,+j(b)";
+ offbits = 9;
+ goto ld_st;
+ case M_LHE_AB:
+ ab = 1;
+ case M_LHE_OB:
+ s = "lhe";
+ fmt = "t,+j(b)";
+ offbits = 9;
+ goto ld_st;
+ case M_LLE_AB:
+ ab = 1;
+ case M_LLE_OB:
+ s = "lle";
+ fmt = "t,+j(b)";
+ offbits = 9;
+ goto ld_st;
+ case M_LWE_AB:
+ ab = 1;
+ case M_LWE_OB:
+ s = "lwe";
+ fmt = "t,+j(b)";
+ offbits = 9;
+ goto ld_st;
+ case M_LWLE_AB:
+ ab = 1;
+ case M_LWLE_OB:
+ s = "lwle";
+ fmt = "t,+j(b)";
+ offbits = 9;
+ goto ld_st;
+ case M_LWRE_AB:
+ ab = 1;
+ case M_LWRE_OB:
+ s = "lwre";
+ fmt = "t,+j(b)";
+ offbits = 9;
+ goto ld_st;
+ case M_SBE_AB:
+ ab = 1;
+ case M_SBE_OB:
+ s = "sbe";
+ fmt = "t,+j(b)";
+ offbits = 9;
+ goto ld_st;
+ case M_SCE_AB:
+ ab = 1;
+ case M_SCE_OB:
+ s = "sce";
+ fmt = "t,+j(b)";
+ offbits = 9;
+ goto ld_st;
+ case M_SHE_AB:
+ ab = 1;
+ case M_SHE_OB:
+ s = "she";
+ fmt = "t,+j(b)";
+ offbits = 9;
+ goto ld_st;
+ case M_SWE_AB:
+ ab = 1;
+ case M_SWE_OB:
+ s = "swe";
+ fmt = "t,+j(b)";
+ offbits = 9;
+ goto ld_st;
+ case M_SWLE_AB:
+ ab = 1;
+ case M_SWLE_OB:
+ s = "swle";
+ fmt = "t,+j(b)";
+ offbits = 9;
+ goto ld_st;
+ case M_SWRE_AB:
+ ab = 1;
+ case M_SWRE_OB:
+ s = "swre";
+ fmt = "t,+j(b)";
+ offbits = 9;
+ goto ld_st;
case M_ACLR_AB:
ab = 1;
case M_ACLR_OB:
s = "aclr";
treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
fmt = "\\,~(b)";
- off12 = 1;
+ offbits = 12;
goto ld_st;
case M_ASET_AB:
ab = 1;
s = "aset";
treg = EXTRACT_OPERAND (mips_opts.micromips, 3BITPOS, *ip);
fmt = "\\,~(b)";
- off12 = 1;
+ offbits = 12;
goto ld_st;
case M_LB_AB:
ab = 1;
case M_LWC2_OB:
s = "lwc2";
fmt = COP12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
/* Itbl support may require additional care here. */
coproc = 1;
goto ld_st;
case M_LWL_OB:
s = "lwl";
fmt = MEM12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_LWR_AB:
ab = 1;
case M_LWR_OB:
s = "lwr";
fmt = MEM12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_LDC1_AB:
ab = 1;
case M_LDC2_OB:
s = "ldc2";
fmt = COP12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
/* Itbl support may require additional care here. */
coproc = 1;
goto ld_st;
case M_LDL_OB:
s = "ldl";
fmt = MEM12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_LDR_AB:
ab = 1;
case M_LDR_OB:
s = "ldr";
fmt = MEM12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_LL_AB:
ab = 1;
case M_LL_OB:
s = "ll";
fmt = MEM12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
goto ld;
case M_LLD_AB:
ab = 1;
case M_LLD_OB:
s = "lld";
fmt = MEM12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
goto ld;
case M_LWU_AB:
ab = 1;
case M_LWU_OB:
s = "lwu";
fmt = MEM12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
goto ld;
case M_LWP_AB:
ab = 1;
gas_assert (mips_opts.micromips);
s = "lwp";
fmt = "t,~(b)";
- off12 = 1;
+ offbits = 12;
lp = 1;
goto ld;
case M_LDP_AB:
gas_assert (mips_opts.micromips);
s = "ldp";
fmt = "t,~(b)";
- off12 = 1;
+ offbits = 12;
lp = 1;
goto ld;
case M_LWM_AB:
gas_assert (mips_opts.micromips);
s = "lwm";
fmt = "n,~(b)";
- off12 = 1;
+ offbits = 12;
goto ld_st;
case M_LDM_AB:
ab = 1;
gas_assert (mips_opts.micromips);
s = "ldm";
fmt = "n,~(b)";
- off12 = 1;
+ offbits = 12;
goto ld_st;
ld:
case M_SWC2_OB:
s = "swc2";
fmt = COP12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
/* Itbl support may require additional care here. */
coproc = 1;
goto ld_st;
case M_SWL_OB:
s = "swl";
fmt = MEM12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_SWR_AB:
ab = 1;
case M_SWR_OB:
s = "swr";
fmt = MEM12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_SC_AB:
ab = 1;
case M_SC_OB:
s = "sc";
fmt = MEM12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_SCD_AB:
ab = 1;
case M_SCD_OB:
s = "scd";
fmt = MEM12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_CACHE_AB:
ab = 1;
case M_CACHE_OB:
s = "cache";
fmt = mips_opts.micromips ? "k,~(b)" : "k,o(b)";
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
+ goto ld_st;
+ case M_CACHEE_AB:
+ ab = 1;
+ case M_CACHEE_OB:
+ s = "cachee";
+ fmt = "k,+j(b)";
+ offbits = 9;
goto ld_st;
case M_PREF_AB:
ab = 1;
case M_PREF_OB:
s = "pref";
fmt = !mips_opts.micromips ? "k,o(b)" : "k,~(b)";
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
+ goto ld_st;
+ case M_PREFE_AB:
+ ab = 1;
+ case M_PREFE_OB:
+ s = "prefe";
+ fmt = "k,+j(b)";
+ offbits = 9;
goto ld_st;
case M_SDC1_AB:
ab = 1;
case M_SDC2_OB:
s = "sdc2";
fmt = COP12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
/* Itbl support may require additional care here. */
coproc = 1;
goto ld_st;
case M_SDL_OB:
s = "sdl";
fmt = MEM12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_SDR_AB:
ab = 1;
case M_SDR_OB:
s = "sdr";
fmt = MEM12_FMT;
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
goto ld_st;
case M_SWP_AB:
ab = 1;
gas_assert (mips_opts.micromips);
s = "swp";
fmt = "t,~(b)";
- off12 = 1;
+ offbits = 12;
goto ld_st;
case M_SDP_AB:
ab = 1;
gas_assert (mips_opts.micromips);
s = "sdp";
fmt = "t,~(b)";
- off12 = 1;
+ offbits = 12;
goto ld_st;
case M_SWM_AB:
ab = 1;
gas_assert (mips_opts.micromips);
s = "swm";
fmt = "n,~(b)";
- off12 = 1;
+ offbits = 12;
goto ld_st;
case M_SDM_AB:
ab = 1;
gas_assert (mips_opts.micromips);
s = "sdm";
fmt = "n,~(b)";
- off12 = 1;
+ offbits = 12;
ld_st:
tempreg = AT;
expr1.X_add_number = offset_expr.X_add_number;
normalize_address_expr (&expr1);
- if (!off12 && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
+ if ((offbits == 0 || offbits == 16)
+ && !IS_SEXT_16BIT_NUM (expr1.X_add_number))
{
expr1.X_add_number = ((expr1.X_add_number + 0x8000)
& ~(bfd_vma) 0xffff);
hipart = 1;
}
- else if (off12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
+ else if (offbits == 12 && !IS_SEXT_12BIT_NUM (expr1.X_add_number))
{
expr1.X_add_number = ((expr1.X_add_number + 0x800)
& ~(bfd_vma) 0xfff);
hipart = 1;
}
+ else if (offbits == 9 && !IS_SEXT_9BIT_NUM (expr1.X_add_number))
+ {
+ expr1.X_add_number = ((expr1.X_add_number + 0x100)
+ & ~(bfd_vma) 0x1ff);
+ hipart = 1;
+ }
if (hipart)
{
load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
tempreg, tempreg, breg);
breg = tempreg;
}
- if (off0)
+ if (offbits == 0)
{
if (offset_expr.X_add_number == 0)
tempreg = breg;
"t,r,j", tempreg, breg, BFD_RELOC_LO16);
macro_build (NULL, s, fmt, treg, tempreg);
}
- else if (!off12)
+ else if (offbits == 16)
macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, breg);
else
macro_build (NULL, s, fmt,
treg, (unsigned long) offset_expr.X_add_number, breg);
}
- else if (off12 || off0)
+ else if (offbits != 16)
{
- /* A 12-bit or 0-bit offset field is too narrow to be used
- for a low-part relocation, so load the whole address into
- the auxillary register. In the case of "A(b)" addresses,
- we first load absolute address "A" into the register and
- then add base register "b". In the case of "o(b)" addresses,
- we simply need to add 16-bit offset "o" to base register "b", and
+ /* The offset field is too narrow to be used for a low-part
+ relocation, so load the whole address into the auxillary
+ register. In the case of "A(b)" addresses, we first load
+ absolute address "A" into the register and then add base
+ register "b". In the case of "o(b)" addresses, we simply
+ need to add 16-bit offset "o" to base register "b", and
offset_reloc already contains the relocations associated
with "o". */
if (ab)
tempreg, breg, -1,
offset_reloc[0], offset_reloc[1], offset_reloc[2]);
expr1.X_add_number = 0;
- if (off0)
+ if (offbits == 0)
macro_build (NULL, s, fmt, treg, tempreg);
else
macro_build (NULL, s, fmt,
ab = 1;
case M_SAA_OB:
s = "saa";
- off0 = 1;
+ offbits = 0;
fmt = "t,(b)";
goto ld_st;
case M_SAAD_AB:
ab = 1;
case M_SAAD_OB:
s = "saad";
- off0 = 1;
+ offbits = 0;
fmt = "t,(b)";
goto ld_st;
case M_ULW:
s = "lwl";
s2 = "lwr";
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
off = 3;
goto uld_st;
case M_ULD_A:
case M_ULD:
s = "ldl";
s2 = "ldr";
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
off = 7;
goto uld_st;
case M_USH_A:
case M_USW:
s = "swl";
s2 = "swr";
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
off = 3;
ust = 1;
goto uld_st;
case M_USD:
s = "sdl";
s2 = "sdr";
- off12 = mips_opts.micromips;
+ offbits = (mips_opts.micromips ? 12 : 16);
off = 7;
ust = 1;
tempreg = treg;
ep = &expr1;
}
- else if (off12
+ else if (offbits == 12
&& (offset_expr.X_op != O_constant
|| !IS_SEXT_12BIT_NUM (offset_expr.X_add_number)
|| !IS_SEXT_12BIT_NUM (offset_expr.X_add_number + off)))
if (!target_big_endian)
ep->X_add_number += off;
- if (!off12)
+ if (offbits != 12)
macro_build (ep, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
else
macro_build (NULL, s, "t,~(b)",
ep->X_add_number -= off;
else
ep->X_add_number += off;
- if (!off12)
+ if (offbits != 12)
macro_build (ep, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
else
macro_build (NULL, s2, "t,~(b)",
case 'a': USE_BITS (OP_MASK_OFFSET_A, OP_SH_OFFSET_A); break;
case 'b': USE_BITS (OP_MASK_OFFSET_B, OP_SH_OFFSET_B); break;
case 'c': USE_BITS (OP_MASK_OFFSET_C, OP_SH_OFFSET_C); break;
+ case 'j': USE_BITS (OP_MASK_EVAOFFSET, OP_SH_EVAOFFSET); break;
default:
as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
case 'F': USE_BITS (INSMSB); break;
case 'G': USE_BITS (EXTMSBD); break;
case 'H': USE_BITS (EXTMSBD); break;
+ case 'j': USE_BITS (EVAOFFSET); break;
default:
as_bad (_("Internal error: bad mips opcode "
"(unknown extension operand type `%c%c'): %s %s"),
INSERT_OPERAND (0, FZ, *ip, regno);
continue;
+ case 'j':
+ {
+ int shift = 8;
+ size_t i;
+ /* Check whether there is only a single bracketed expression
+ left. If so, it must be the base register and the
+ constant must be zero. */
+ if (*s == '(' && strchr (s + 1, '(') == 0)
+ continue;
+
+ /* If this value won't fit into the offset, then go find
+ a macro that will generate a 16- or 32-bit offset code
+ pattern. */
+ i = my_getSmallExpression (&imm_expr, imm_reloc, s);
+ if ((i == 0 && (imm_expr.X_op != O_constant
+ || imm_expr.X_add_number >= 1 << shift
+ || imm_expr.X_add_number < -1 << shift))
+ || i > 0)
+ {
+ imm_expr.X_op = O_absent;
+ break;
+ }
+ INSERT_OPERAND (mips_opts.micromips, EVAOFFSET, *ip,
+ imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ }
+ continue;
+
default:
as_bad (_("Internal error: bad %s opcode "
"(unknown extension operand type `+%c'): %s %s"),
OPTION_NO_SMARTMIPS,
OPTION_DSPR2,
OPTION_NO_DSPR2,
+ OPTION_EVA,
+ OPTION_NO_EVA,
OPTION_MICROMIPS,
OPTION_NO_MICROMIPS,
OPTION_MCU,
{"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
{"mdspr2", no_argument, NULL, OPTION_DSPR2},
{"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
+ {"meva", no_argument, NULL, OPTION_EVA},
+ {"mno-eva", no_argument, NULL, OPTION_NO_EVA},
{"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
{"mno-micromips", no_argument, NULL, OPTION_NO_MICROMIPS},
{"mmcu", no_argument, NULL, OPTION_MCU},
mips_opts.ase_dsp = 0;
break;
+ case OPTION_EVA:
+ mips_opts.ase_eva = 1;
+ break;
+
+ case OPTION_NO_EVA:
+ mips_opts.ase_eva = 0;
+ break;
+
case OPTION_MT:
mips_opts.ase_mt = 1;
break;
if (mips_opts.micromips == -1)
mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0;
if (mips_opts.ase_mips3d == -1)
- mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
+ mips_opts.ase_mips3d = ((arch_info->ase & ASE_MIPS3D)
&& file_mips_fp32 == 0) ? 1 : 0;
if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
as_bad (_("-mfp32 used with -mips3d"));
if (mips_opts.ase_mdmx == -1)
- mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
+ mips_opts.ase_mdmx = ((arch_info->ase & ASE_MDMX)
&& file_mips_fp32 == 0) ? 1 : 0;
if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
as_bad (_("-mfp32 used with -mdmx"));
if (mips_opts.ase_smartmips == -1)
- mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
+ mips_opts.ase_smartmips = (arch_info->ase & ASE_SMARTMIPS) ? 1 : 0;
if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
as_warn (_("%s ISA does not support SmartMIPS"),
mips_cpu_info_from_isa (mips_opts.isa)->name);
if (mips_opts.ase_dsp == -1)
- mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
+ mips_opts.ase_dsp = (arch_info->ase & ASE_DSP) ? 1 : 0;
if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
as_warn (_("%s ISA does not support DSP ASE"),
mips_cpu_info_from_isa (mips_opts.isa)->name);
if (mips_opts.ase_dspr2 == -1)
{
- mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
- mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
+ mips_opts.ase_dspr2 = (arch_info->ase & ASE_DSPR2) ? 1 : 0;
+ mips_opts.ase_dsp = (arch_info->ase & ASE_DSP) ? 1 : 0;
}
if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
as_warn (_("%s ISA does not support DSP R2 ASE"),
mips_cpu_info_from_isa (mips_opts.isa)->name);
+ if (mips_opts.ase_eva == -1)
+ mips_opts.ase_eva = (arch_info->ase & ASE_EVA) ? 1 : 0;
+ if (mips_opts.ase_eva && !ISA_SUPPORTS_EVA_ASE)
+ as_warn (_("%s ISA does not support EVA ASE"),
+ mips_cpu_info_from_isa (mips_opts.isa)->name);
+
if (mips_opts.ase_mt == -1)
- mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
+ mips_opts.ase_mt = (arch_info->ase & ASE_MT) ? 1 : 0;
if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
as_warn (_("%s ISA does not support MT ASE"),
mips_cpu_info_from_isa (mips_opts.isa)->name);
if (mips_opts.ase_mcu == -1)
- mips_opts.ase_mcu = (arch_info->flags & MIPS_CPU_ASE_MCU) ? 1 : 0;
+ mips_opts.ase_mcu = (arch_info->ase & ASE_MCU) ? 1 : 0;
if (mips_opts.ase_mcu && !ISA_SUPPORTS_MCU_ASE)
as_warn (_("%s ISA does not support MCU ASE"),
mips_cpu_info_from_isa (mips_opts.isa)->name);
if (mips_opts.ase_virt == -1)
- mips_opts.ase_virt = (arch_info->flags & MIPS_CPU_ASE_VIRT) ? 1 : 0;
+ mips_opts.ase_virt = (arch_info->ase & ASE_VIRT) ? 1 : 0;
if (mips_opts.ase_virt && !ISA_SUPPORTS_VIRT_ASE)
as_warn (_("%s ISA does not support Virtualization ASE"),
mips_cpu_info_from_isa (mips_opts.isa)->name);
file_ase_smartmips = mips_opts.ase_smartmips;
file_ase_dsp = mips_opts.ase_dsp;
file_ase_dspr2 = mips_opts.ase_dspr2;
+ file_ase_eva = mips_opts.ase_eva;
file_ase_mt = mips_opts.ase_mt;
file_ase_virt = mips_opts.ase_virt;
mips_opts.gp32 = file_mips_gp32;
mips_opts.ase_dspr2 = 0;
mips_opts.ase_dsp = 0;
}
+ else if (strcmp (name, "eva") == 0)
+ {
+ if (!ISA_SUPPORTS_EVA_ASE)
+ as_warn (_("%s ISA does not support EVA ASE"),
+ mips_cpu_info_from_isa (mips_opts.isa)->name);
+ mips_opts.ase_eva = 1;
+ }
+ else if (strcmp (name, "noeva") == 0)
+ mips_opts.ase_eva = 0;
else if (strcmp (name, "mt") == 0)
{
if (!ISA_SUPPORTS_MT_ASE)
demand_empty_rest_of_line ();
}
+/* Handle the .ehword pseudo-op. This is used when generating unwinding
+ tables. It generates a R_MIPS_EH reloc. */
+
+static void
+s_ehword (int ignore ATTRIBUTE_UNUSED)
+{
+ expressionS ex;
+ char *p;
+
+ mips_emit_delays ();
+
+ expression (&ex);
+ mips_clear_insn_labels ();
+
+ if (ex.X_op != O_symbol || ex.X_add_number != 0)
+ {
+ as_bad (_("Unsupported use of .ehword"));
+ ignore_rest_of_line ();
+ }
+
+ p = frag_more (4);
+ md_number_to_chars (p, 0, 4);
+ fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
+ BFD_RELOC_MIPS_EH);
+
+ demand_empty_rest_of_line ();
+}
+
/* Handle the .cpadd pseudo-op. This is used when dealing with switch
tables in SVR4 PIC code. */
switch ((insn >> 28) & 0xf)
{
case 4:
- /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
- have the condition reversed by tweaking a single
- bit, and their opcodes all have 0x4???????. */
- gas_assert ((insn & 0xf1000000) == 0x41000000);
+ /* bc[0-3][tf]l? instructions can have the condition
+ reversed by tweaking a single TF bit, and their
+ opcodes all have 0x4???????. */
+ gas_assert ((insn & 0xf3e00000) == 0x41000000);
insn ^= 0x00010000;
break;
static const struct mips_cpu_info mips_cpu_info_table[] =
{
/* Entries for generic ISAs */
- { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
- { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
- { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
- { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
- { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
- { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
- { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
- { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
+ { "mips1", MIPS_CPU_IS_ISA, 0, ISA_MIPS1, CPU_R3000 },
+ { "mips2", MIPS_CPU_IS_ISA, 0, ISA_MIPS2, CPU_R6000 },
+ { "mips3", MIPS_CPU_IS_ISA, 0, ISA_MIPS3, CPU_R4000 },
+ { "mips4", MIPS_CPU_IS_ISA, 0, ISA_MIPS4, CPU_R8000 },
+ { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 },
+ { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 },
+ { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 },
+ { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 },
/* MIPS I */
- { "r3000", 0, ISA_MIPS1, CPU_R3000 },
- { "r2000", 0, ISA_MIPS1, CPU_R3000 },
- { "r3900", 0, ISA_MIPS1, CPU_R3900 },
+ { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 },
+ { "r2000", 0, 0, ISA_MIPS1, CPU_R3000 },
+ { "r3900", 0, 0, ISA_MIPS1, CPU_R3900 },
/* MIPS II */
- { "r6000", 0, ISA_MIPS2, CPU_R6000 },
+ { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
/* MIPS III */
- { "r4000", 0, ISA_MIPS3, CPU_R4000 },
- { "r4010", 0, ISA_MIPS2, CPU_R4010 },
- { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
- { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
- { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
- { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
- { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
- { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
- { "r4400", 0, ISA_MIPS3, CPU_R4400 },
- { "r4600", 0, ISA_MIPS3, CPU_R4600 },
- { "orion", 0, ISA_MIPS3, CPU_R4600 },
- { "r4650", 0, ISA_MIPS3, CPU_R4650 },
- { "r5900", 0, ISA_MIPS3, CPU_R5900 },
+ { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
+ { "r4010", 0, 0, ISA_MIPS2, CPU_R4010 },
+ { "vr4100", 0, 0, ISA_MIPS3, CPU_VR4100 },
+ { "vr4111", 0, 0, ISA_MIPS3, CPU_R4111 },
+ { "vr4120", 0, 0, ISA_MIPS3, CPU_VR4120 },
+ { "vr4130", 0, 0, ISA_MIPS3, CPU_VR4120 },
+ { "vr4181", 0, 0, ISA_MIPS3, CPU_R4111 },
+ { "vr4300", 0, 0, ISA_MIPS3, CPU_R4300 },
+ { "r4400", 0, 0, ISA_MIPS3, CPU_R4400 },
+ { "r4600", 0, 0, ISA_MIPS3, CPU_R4600 },
+ { "orion", 0, 0, ISA_MIPS3, CPU_R4600 },
+ { "r4650", 0, 0, ISA_MIPS3, CPU_R4650 },
+ { "r5900", 0, 0, ISA_MIPS3, CPU_R5900 },
/* ST Microelectronics Loongson 2E and 2F cores */
- { "loongson2e", 0, ISA_MIPS3, CPU_LOONGSON_2E },
- { "loongson2f", 0, ISA_MIPS3, CPU_LOONGSON_2F },
+ { "loongson2e", 0, 0, ISA_MIPS3, CPU_LOONGSON_2E },
+ { "loongson2f", 0, 0, ISA_MIPS3, CPU_LOONGSON_2F },
/* MIPS IV */
- { "r8000", 0, ISA_MIPS4, CPU_R8000 },
- { "r10000", 0, ISA_MIPS4, CPU_R10000 },
- { "r12000", 0, ISA_MIPS4, CPU_R12000 },
- { "r14000", 0, ISA_MIPS4, CPU_R14000 },
- { "r16000", 0, ISA_MIPS4, CPU_R16000 },
- { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
- { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
- { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
- { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
- { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
- { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
- { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
- { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
- { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
- { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
+ { "r8000", 0, 0, ISA_MIPS4, CPU_R8000 },
+ { "r10000", 0, 0, ISA_MIPS4, CPU_R10000 },
+ { "r12000", 0, 0, ISA_MIPS4, CPU_R12000 },
+ { "r14000", 0, 0, ISA_MIPS4, CPU_R14000 },
+ { "r16000", 0, 0, ISA_MIPS4, CPU_R16000 },
+ { "vr5000", 0, 0, ISA_MIPS4, CPU_R5000 },
+ { "vr5400", 0, 0, ISA_MIPS4, CPU_VR5400 },
+ { "vr5500", 0, 0, ISA_MIPS4, CPU_VR5500 },
+ { "rm5200", 0, 0, ISA_MIPS4, CPU_R5000 },
+ { "rm5230", 0, 0, ISA_MIPS4, CPU_R5000 },
+ { "rm5231", 0, 0, ISA_MIPS4, CPU_R5000 },
+ { "rm5261", 0, 0, ISA_MIPS4, CPU_R5000 },
+ { "rm5721", 0, 0, ISA_MIPS4, CPU_R5000 },
+ { "rm7000", 0, 0, ISA_MIPS4, CPU_RM7000 },
+ { "rm9000", 0, 0, ISA_MIPS4, CPU_RM9000 },
/* MIPS 32 */
- { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
- { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
- { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
- { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
+ { "4kc", 0, 0, ISA_MIPS32, CPU_MIPS32 },
+ { "4km", 0, 0, ISA_MIPS32, CPU_MIPS32 },
+ { "4kp", 0, 0, ISA_MIPS32, CPU_MIPS32 },
+ { "4ksc", 0, ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
/* MIPS 32 Release 2 */
- { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "m14k", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "m14kc", MIPS_CPU_ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "m14ke", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
- ISA_MIPS32R2, CPU_MIPS32R2 },
- { "m14kec", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2 | MIPS_CPU_ASE_MCU,
- ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "4kec", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "4kem", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "4kep", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "4ksd", 0, ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "m4k", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "m4kp", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "m14k", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "m14kc", 0, ASE_MCU, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "m14ke", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "m14kec", 0, ASE_DSP | ASE_DSPR2 | ASE_MCU,
+ ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kc", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kf2_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kf", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kf1_1", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
/* Deprecated forms of the above. */
- { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kfx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kx", 0, 0, ISA_MIPS32R2, CPU_MIPS32R2 },
/* 24KE is a 24K with DSP ASE, other ASEs are optional. */
- { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kec", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kef2_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kef", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kef1_1", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
/* Deprecated forms of the above. */
- { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
- { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kefx", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "24kex", 0, ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
/* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
- { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
- ISA_MIPS32R2, CPU_MIPS32R2 },
- { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
- ISA_MIPS32R2, CPU_MIPS32R2 },
- { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
- ISA_MIPS32R2, CPU_MIPS32R2 },
- { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
- ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
/* Deprecated forms of the above. */
- { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
- ISA_MIPS32R2, CPU_MIPS32R2 },
- { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
- ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kfx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kx", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
/* 34Kn is a 34kc without DSP. */
- { "34kn", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "34kn", 0, ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
/* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
- { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
- ISA_MIPS32R2, CPU_MIPS32R2 },
- { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
- ISA_MIPS32R2, CPU_MIPS32R2 },
- { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
- ISA_MIPS32R2, CPU_MIPS32R2 },
- { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
- ISA_MIPS32R2, CPU_MIPS32R2 },
- { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
- ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "74kc", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "74kf2_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "74kf", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "74kf1_1", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "74kf3_2", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
/* Deprecated forms of the above. */
- { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
- ISA_MIPS32R2, CPU_MIPS32R2 },
- { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
- ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "74kfx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "74kx", 0, ASE_DSP | ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 },
/* 1004K cores are multiprocessor versions of the 34K. */
- { "1004kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
- ISA_MIPS32R2, CPU_MIPS32R2 },
- { "1004kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
- ISA_MIPS32R2, CPU_MIPS32R2 },
- { "1004kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
- ISA_MIPS32R2, CPU_MIPS32R2 },
- { "1004kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
- ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "1004kc", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
+ { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
/* MIPS 64 */
- { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
- { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
- { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
- { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
+ { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
+ { "5kf", 0, 0, ISA_MIPS64, CPU_MIPS64 },
+ { "20kc", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
+ { "25kf", 0, ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
/* Broadcom SB-1 CPU core */
- { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
- ISA_MIPS64, CPU_SB1 },
+ { "sb1", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
/* Broadcom SB-1A CPU core */
- { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
- ISA_MIPS64, CPU_SB1 },
+ { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 },
- { "loongson3a", 0, ISA_MIPS64, CPU_LOONGSON_3A },
+ { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A },
/* MIPS 64 Release 2 */
/* Cavium Networks Octeon CPU core */
- { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
- { "octeon+", 0, ISA_MIPS64R2, CPU_OCTEONP },
- { "octeon2", 0, ISA_MIPS64R2, CPU_OCTEON2 },
+ { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
+ { "octeon+", 0, 0, ISA_MIPS64R2, CPU_OCTEONP },
+ { "octeon2", 0, 0, ISA_MIPS64R2, CPU_OCTEON2 },
/* RMI Xlr */
- { "xlr", 0, ISA_MIPS64, CPU_XLR },
+ { "xlr", 0, 0, ISA_MIPS64, CPU_XLR },
/* Broadcom XLP.
XLP is mostly like XLR, with the prominent exception that it is
MIPS64R2 rather than MIPS64. */
- { "xlp", 0, ISA_MIPS64R2, CPU_XLR },
+ { "xlp", 0, 0, ISA_MIPS64R2, CPU_XLR },
/* End marker */
- { NULL, 0, 0, 0 }
+ { NULL, 0, 0, 0, 0 }
};
-msoft-float do not allow floating-point instructions\n\
-msingle-float only allow 32-bit floating-point operations\n\
-mdouble-float allow 32-bit and 64-bit floating-point operations\n\
---[no-]construct-floats [dis]allow floating point values to be constructed\n"
+--[no-]construct-floats [dis]allow floating point values to be constructed\n\
+--[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n"
));
#ifdef OBJ_ELF
fprintf (stream, _("\
projects / deliverable / binutils-gdb.git / blobdiff