* config/tc-ppc.c (ppc_setup_opcodes): Tidy. Add code to test

[deliverable/binutils-gdb.git] / gas / config / tc-mips.c

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index f19299e1c3000ea867d598325e1d6d1b929d2570..f089345456f944f6f8ff402bb1851c1066168955 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1,6 +1,6 @@
 /* tc-mips.c -- assemble code for a MIPS chip.
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
+   2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
    Contributed by the OSF and Ralph Campbell.
    Written by Keith Knowles and Ralph Campbell, working independently.
    Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
@@ -9133,6 +9133,19 @@ do_msbd:
                  if (c == 'z' && regno != 0)
                    break;
 
+                 if (c == 's' && !strcmp (ip->insn_mo->name, "jalr"))
+                   {
+                     if (regno == lastregno)
+                       {
+                         insn_error = _("source and destinationations must be different");
+                         continue;
+                       }
+                     if (regno == 31 && lastregno == 0)
+                       {
+                         insn_error = _("a destination register must be supplied");
+                         continue;
+                       }
+                   }
        /* Now that we have assembled one operand, we use the args string
         * to figure out where it goes in the instruction.  */
                  switch (c)
@@ -14852,6 +14865,9 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   { "loongson2e",     0,      ISA_MIPS3,      CPU_LOONGSON_2E },
   { "loongson2f",     0,      ISA_MIPS3,      CPU_LOONGSON_2F },
 
+  /* Cavium Networks Octeon CPU core */
+  { "octeon",        0,      ISA_MIPS64R2,   CPU_OCTEON },
+
   /* End marker */
   { NULL, 0, 0, 0 }
 };