extern int target_big_endian;
/* The name of the readonly data section. */
-#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
- ? ".data" \
- : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
+#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
? ".rdata" \
: OUTPUT_FLAVOR == bfd_target_coff_flavour \
? ".rdata" \
#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
-/* We can only have 64bit addresses if the object file format
- supports it. */
+/* True if relocations are stored in-place. */
+#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
+
+/* We can only have 64bit addresses if the object file format supports it. */
#define HAVE_32BIT_ADDRESSES \
(HAVE_32BIT_GPRS \
- || ((bfd_arch_bits_per_address (stdoutput) == 32 \
- || ! HAVE_64BIT_OBJECTS) \
- && mips_pic != EMBEDDED_PIC))
+ || (bfd_arch_bits_per_address (stdoutput) == 32 \
+ || ! HAVE_64BIT_OBJECTS)) \
#define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
/* True if CPU has a ror instruction. */
#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
-/* Whether the processor uses hardware interlocks to protect
- reads from the HI and LO registers, and thus does not
- require nops to be inserted. */
-
-#define hilo_interlocks (mips_opts.arch == CPU_R4010 \
- || mips_opts.arch == CPU_VR5500 \
- || mips_opts.arch == CPU_RM7000 \
- || mips_opts.arch == CPU_SB1 \
- )
+/* True if mflo and mfhi can be immediately followed by instructions
+ which write to the HI and LO registers.
+
+ According to MIPS specifications, MIPS ISAs I, II, and III need
+ (at least) two instructions between the reads of HI/LO and
+ instructions which write them, and later ISAs do not. Contradicting
+ the MIPS specifications, some MIPS IV processor user manuals (e.g.
+ the UM for the NEC Vr5000) document needing the instructions between
+ HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
+ MIPS64 and later ISAs to have the interlocks, plus any specific
+ earlier-ISA CPUs for which CPU documentation declares that the
+ instructions are really interlocked. */
+#define hilo_interlocks \
+ (mips_opts.isa == ISA_MIPS32 \
+ || mips_opts.isa == ISA_MIPS32R2 \
+ || mips_opts.isa == ISA_MIPS64 \
+ || mips_opts.isa == ISA_MIPS64R2 \
+ || mips_opts.arch == CPU_R4010 \
+ || mips_opts.arch == CPU_R10000 \
+ || mips_opts.arch == CPU_R12000 \
+ || mips_opts.arch == CPU_RM7000 \
+ || mips_opts.arch == CPU_VR5500 \
+ )
/* Whether the processor uses hardware interlocks to protect reads
from the GPRs after they are loaded from memory, and thus does not
level I. */
#define gpr_interlocks \
(mips_opts.isa != ISA_MIPS1 \
- || mips_opts.arch == CPU_VR5400 \
- || mips_opts.arch == CPU_VR5500 \
|| mips_opts.arch == CPU_R3900)
/* Whether the processor uses hardware interlocks to avoid delays
&& mips_opts.isa != ISA_MIPS2 \
&& mips_opts.isa != ISA_MIPS3) \
|| mips_opts.arch == CPU_R4300 \
- || mips_opts.arch == CPU_VR5400 \
- || mips_opts.arch == CPU_VR5500 \
- || mips_opts.arch == CPU_SB1 \
)
/* Whether the processor uses hardware interlocks to protect reads
16, 17, 2, 3, 4, 5, 6, 7
};
-static int mips_fix_4122_bugs;
+static int mips_fix_vr4120;
/* We don't relax branches by default, since this causes us to expand
`la .l2 - .l1' if there's a branch between .l1 and .l2, because we
(struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
static void mips_no_prev_insn (int);
static void mips16_macro_build
- (int *, expressionS *, const char *, const char *, va_list);
-static void load_register (int *, int, expressionS *, int);
+ (expressionS *, const char *, const char *, va_list);
+static void load_register (int, expressionS *, int);
static void macro_start (void);
static void macro_end (void);
static void macro (struct mips_cl_insn * ip);
{
switch (OUTPUT_FLAVOR)
{
- case bfd_target_aout_flavour:
- return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
case bfd_target_ecoff_flavour:
return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
case bfd_target_coff_flavour:
/* set the default alignment for the text section (2**2) */
record_alignment (text_section, 2);
- if (USE_GLOBAL_POINTER_OPT)
- bfd_set_gp_size (stdoutput, g_switch_value);
+ bfd_set_gp_size (stdoutput, g_switch_value);
if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
{
static inline bfd_boolean
reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
{
- return (reloc == BFD_RELOC_HI16_S
- || reloc == BFD_RELOC_MIPS_GOT16);
+ return (HAVE_IN_PLACE_ADDENDS
+ && (reloc == BFD_RELOC_HI16_S
+ || reloc == BFD_RELOC_MIPS_GOT16));
}
/* Return true if the given fixup is followed by a matching R_MIPS_LO16
if (prev_prev_nop && nops == 0)
++nops;
- if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
+ if (mips_fix_vr4120 && prev_insn.insn_mo->name)
{
/* We're out of bits in pinfo, so we must resort to string
ops here. Shortcuts are selected based on opcodes being
- limited to the VR4122 instruction set. */
+ limited to the VR4120 instruction set. */
int min_nops = 0;
const char *pn = prev_insn.insn_mo->name;
const char *tn = ip->insn_mo->name;
- if (strncmp(pn, "macc", 4) == 0
- || strncmp(pn, "dmacc", 5) == 0)
+ if (strncmp (pn, "macc", 4) == 0
+ || strncmp (pn, "dmacc", 5) == 0)
{
/* Errata 21 - [D]DIV[U] after [D]MACC */
if (strstr (tn, "div"))
- {
- min_nops = 1;
- }
+ min_nops = 1;
- /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
- if (pn[0] == 'd' /* dmacc */
- && (strncmp(tn, "dmult", 5) == 0
- || strncmp(tn, "dmacc", 5) == 0))
- {
- min_nops = 1;
- }
+ /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
+ instruction is executed immediately after a MACC or
+ DMACC instruction, the result of [either instruction]
+ is incorrect." */
+ if (strncmp (tn, "mult", 4) == 0
+ || strncmp (tn, "dmult", 5) == 0)
+ min_nops = 1;
+
+ /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
+ Applies on top of VR4181A MD(1) errata. */
+ if (pn[0] == 'd' && strncmp (tn, "dmacc", 5) == 0)
+ min_nops = 1;
/* Errata 24 - MT{LO,HI} after [D]MACC */
if (strcmp (tn, "mtlo") == 0
|| strcmp (tn, "mthi") == 0)
- {
- min_nops = 1;
- }
-
+ min_nops = 1;
}
- else if (strncmp(pn, "dmult", 5) == 0
- && (strncmp(tn, "dmult", 5) == 0
- || strncmp(tn, "dmacc", 5) == 0))
+ else if (strncmp (pn, "dmult", 5) == 0
+ && (strncmp (tn, "dmult", 5) == 0
+ || strncmp (tn, "dmacc", 5) == 0))
{
/* Here is the rest of errata 23. */
min_nops = 1;
}
+ else if ((strncmp (pn, "dmult", 5) == 0 || strstr (pn, "div"))
+ && (strncmp (tn, "macc", 4) == 0
+ || strncmp (tn, "dmacc", 5) == 0))
+ {
+ /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
+ executed immediately after a DMULT, DMULTU, DIV, DIVU,
+ DDIV or DDIVU instruction, the result of the MACC or
+ DMACC instruction is incorrect.". This partly overlaps
+ the workaround for errata 23. */
+ min_nops = 1;
+ }
if (nops < min_nops)
nops = min_nops;
}
}
fixp[0] = fixp[1] = fixp[2] = NULL;
- if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
+ if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
{
if (address_expr->X_op == O_constant)
{
ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
break;
+ case BFD_RELOC_UNUSED:
case BFD_RELOC_LO16:
case BFD_RELOC_MIPS_GOT_DISP:
ip->insn_opcode |= address_expr->X_add_number & 0xffff;
internalError ();
}
}
- else
+ else if (*reloc_type < BFD_RELOC_UNUSED)
need_reloc:
{
reloc_howto_type *howto;
md_number_to_chars (f, ip->insn_opcode >> 16, 2);
md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
#ifdef OBJ_ELF
- dwarf2_emit_insn (4);
+ /* The value passed to dwarf2_emit_insn is the distance between
+ the end of the current instruction and the address that should
+ be recorded in the debug tables. Since we want to use ISA-encoded
+ addresses in MIPS16 debug info, the value is one byte less than
+ the real instruction length. */
+ dwarf2_emit_insn (3);
#endif
}
else
}
md_number_to_chars (f, ip->insn_opcode, 2);
#ifdef OBJ_ELF
- dwarf2_emit_insn (ip->use_extend ? 4 : 2);
+ dwarf2_emit_insn (ip->use_extend ? 3 : 1);
#endif
}
|| (mips_opts.mips16
&& (pinfo & MIPS16_INSN_WRITE_31)
&& insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
- /* If we are generating embedded PIC code, the branch
- might be expanded into a sequence which uses $at, so
- we can't swap with an instruction which reads it. */
- || (mips_pic == EMBEDDED_PIC
- && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
/* If the previous previous instruction has a load
delay, and sets a register that the branch reads, we
can not swap. */
prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
prev_insn_extended = 0;
+ prev_insn_is_delay_slot = 1;
}
else
{
++nops;
}
- if (mips_fix_4122_bugs && prev_insn.insn_mo->name)
+ if (mips_fix_vr4120 && prev_insn.insn_mo->name)
{
int min_nops = 0;
const char *pn = prev_insn.insn_mo->name;
- if (strncmp(pn, "macc", 4) == 0
- || strncmp(pn, "dmacc", 5) == 0
- || strncmp(pn, "dmult", 5) == 0)
- {
- min_nops = 1;
- }
+ if (strncmp (pn, "macc", 4) == 0
+ || strncmp (pn, "dmacc", 5) == 0
+ || strncmp (pn, "dmult", 5) == 0
+ || strstr (pn, "div"))
+ min_nops = 1;
if (nops < min_nops)
nops = min_nops;
}
string, and corresponding arguments. */
static void
-macro_build (char *place ATTRIBUTE_UNUSED, int *counter,
- expressionS *ep, const char *name, const char *fmt, ...)
+macro_build (expressionS *ep, const char *name, const char *fmt, ...)
{
struct mips_cl_insn insn;
bfd_reloc_code_real_type r[3];
if (mips_opts.mips16)
{
- mips16_macro_build (counter, ep, name, fmt, args);
+ mips16_macro_build (ep, name, fmt, args);
va_end (args);
return;
}
|| *r == BFD_RELOC_MIPS_GOT_PAGE
|| *r == BFD_RELOC_MIPS_GOT_OFST
|| *r == BFD_RELOC_MIPS_GOT_LO16
- || *r == BFD_RELOC_MIPS_CALL_LO16
- || (ep->X_op == O_subtract
- && *r == BFD_RELOC_PCREL_LO16));
+ || *r == BFD_RELOC_MIPS_CALL_LO16);
continue;
case 'u':
|| *r == BFD_RELOC_HI16
|| *r == BFD_RELOC_GPREL16
|| *r == BFD_RELOC_MIPS_GOT_HI16
- || *r == BFD_RELOC_MIPS_CALL_HI16))
- || (ep->X_op == O_subtract
- && *r == BFD_RELOC_PCREL_HI16_S)));
+ || *r == BFD_RELOC_MIPS_CALL_HI16))));
continue;
case 'p':
}
static void
-mips16_macro_build (int *counter ATTRIBUTE_UNUSED,
- expressionS *ep, const char *name, const char *fmt,
+mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
va_list args)
{
struct mips_cl_insn insn;
* function. This occurs in NewABI PIC code.
*/
static void
-macro_build_jalr (int icnt, expressionS *ep)
+macro_build_jalr (expressionS *ep)
{
char *f = NULL;
frag_grow (8);
f = frag_more (0);
}
- macro_build (NULL, &icnt, NULL, "jalr", "d,s", RA, PIC_CALL_REG);
+ macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
if (HAVE_NEWABI)
fix_new_exp (frag_now, f - frag_now->fr_literal,
4, ep, FALSE, BFD_RELOC_MIPS_JALR);
* Generate a "lui" instruction.
*/
static void
-macro_build_lui (char *place ATTRIBUTE_UNUSED, int *counter ATTRIBUTE_UNUSED,
- expressionS *ep, int regnum)
+macro_build_lui (expressionS *ep, int regnum)
{
expressionS high_expr;
struct mips_cl_insn insn;
offset off of a base register (breg) into/from a target register (treg),
using AT if necessary. */
static void
-macro_build_ldst_constoffset (char *place, int *counter, expressionS *ep,
- const char *op, int treg, int breg, int dbl)
+macro_build_ldst_constoffset (expressionS *ep, const char *op,
+ int treg, int breg, int dbl)
{
assert (ep->X_op == O_constant);
if (IS_SEXT_16BIT_NUM(ep->X_add_number))
{
/* Signed 16-bit offset will fit in the op. Easy! */
- macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
- breg);
+ macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
}
else
{
addu $tempreg,$tempreg,$breg
<op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
to handle the complete offset. */
- macro_build_lui (place, counter, ep, AT);
- if (place != NULL)
- place += 4;
- macro_build (place, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT,
- breg);
- if (place != NULL)
- place += 4;
- macro_build (place, counter, ep, op, "t,o(b)", treg, BFD_RELOC_LO16,
- AT);
+ macro_build_lui (ep, AT);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
+ macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
if (mips_opts.noat)
as_warn (_("Macro used $at after \".set noat\""));
* if reg is less than the immediate expression.
*/
static void
-set_at (int *counter, int reg, int unsignedp)
+set_at (int reg, int unsignedp)
{
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= -0x8000
&& imm_expr.X_add_number < 0x8000)
- macro_build (NULL, counter, &imm_expr, unsignedp ? "sltiu" : "slti",
- "t,r,j", AT, reg, BFD_RELOC_LO16);
+ macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
+ AT, reg, BFD_RELOC_LO16);
else
{
- load_register (counter, AT, &imm_expr, HAVE_64BIT_GPRS);
- macro_build (NULL, counter, NULL, unsignedp ? "sltu" : "slt",
- "d,v,t", AT, reg, AT);
+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
+ macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
}
}
* an absolute expression value into a register.
*/
static void
-load_register (int *counter, int reg, expressionS *ep, int dbl)
+load_register (int reg, expressionS *ep, int dbl)
{
int freg;
expressionS hi32, lo32;
/* We can handle 16 bit signed values with an addiu to
$zero. No need to ever use daddiu here, since $zero and
the result are always correct in 32 bit mode. */
- macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
- BFD_RELOC_LO16);
+ macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
return;
}
else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
{
/* We can handle 16 bit unsigned values with an ori to
$zero. */
- macro_build (NULL, counter, ep, "ori", "t,r,i", reg, 0,
- BFD_RELOC_LO16);
+ macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
return;
}
else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
{
/* 32 bit values require an lui. */
- macro_build (NULL, counter, ep, "lui", "t,u", reg, BFD_RELOC_HI16);
+ macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
if ((ep->X_add_number & 0xffff) != 0)
- macro_build (NULL, counter, ep, "ori", "t,r,i", reg, reg,
- BFD_RELOC_LO16);
+ macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
return;
}
}
{
as_bad (_("Number (0x%lx) larger than 32 bits"),
(unsigned long) ep->X_add_number);
- macro_build (NULL, counter, ep, "addiu", "t,r,j", reg, 0,
- BFD_RELOC_LO16);
+ macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
return;
}
{
if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
{
- macro_build (NULL, counter, &lo32, "addiu", "t,r,j", reg, 0,
- BFD_RELOC_LO16);
+ macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
return;
}
if (lo32.X_add_number & 0x80000000)
{
- macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
- BFD_RELOC_HI16);
+ macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
if (lo32.X_add_number & 0xffff)
- macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, reg,
- BFD_RELOC_LO16);
+ macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
return;
}
}
| (lo32.X_add_number >> shift));
else
tmp.X_add_number = hi32.X_add_number >> (shift - 32);
- macro_build (NULL, counter, &tmp, "ori", "t,r,i", reg, 0,
- BFD_RELOC_LO16);
- macro_build (NULL, counter, NULL,
- (shift >= 32) ? "dsll32" : "dsll",
- "d,w,<", reg, reg,
- (shift >= 32) ? shift - 32 : shift);
+ macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
+ macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
+ reg, reg, (shift >= 32) ? shift - 32 : shift);
return;
}
++shift;
ones. */
tmp.X_op = O_constant;
tmp.X_add_number = (offsetT) -1;
- macro_build (NULL, counter, &tmp, "addiu", "t,r,j", reg, 0,
- BFD_RELOC_LO16);
+ macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
if (bit != 0)
{
bit += shift;
- macro_build (NULL, counter, NULL,
- (bit >= 32) ? "dsll32" : "dsll",
- "d,w,<", reg, reg,
- (bit >= 32) ? bit - 32 : bit);
+ macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
+ reg, reg, (bit >= 32) ? bit - 32 : bit);
}
- macro_build (NULL, counter, NULL,
- (shift >= 32) ? "dsrl32" : "dsrl",
- "d,w,<", reg, reg,
- (shift >= 32) ? shift - 32 : shift);
+ macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
+ reg, reg, (shift >= 32) ? shift - 32 : shift);
return;
}
}
generally get better code when we load a sign extended value. */
if ((hi32.X_add_number & 0x80000000) != 0)
hi32.X_add_number |= ~(offsetT) 0xffffffff;
- load_register (counter, reg, &hi32, 0);
+ load_register (reg, &hi32, 0);
freg = reg;
}
if ((lo32.X_add_number & 0xffff0000) == 0)
{
if (freg != 0)
{
- macro_build (NULL, counter, NULL, "dsll32", "d,w,<", reg, freg, 0);
+ macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
freg = reg;
}
}
if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
{
- macro_build (NULL, counter, &lo32, "lui", "t,u", reg,
- BFD_RELOC_HI16);
- macro_build (NULL, counter, NULL, "dsrl32", "d,w,<", reg, reg, 0);
+ macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
+ macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
return;
}
if (freg != 0)
{
- macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, freg, 16);
+ macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
freg = reg;
}
mid16 = lo32;
mid16.X_add_number >>= 16;
- macro_build (NULL, counter, &mid16, "ori", "t,r,i", reg, freg,
- BFD_RELOC_LO16);
- macro_build (NULL, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
+ macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
+ macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
freg = reg;
}
if ((lo32.X_add_number & 0xffff) != 0)
- macro_build (NULL, counter, &lo32, "ori", "t,r,i", reg, freg,
- BFD_RELOC_LO16);
+ macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
+}
+
+static inline void
+load_delay_nop (void)
+{
+ if (!gpr_interlocks)
+ macro_build (NULL, "nop", "");
}
/* Load an address into a register. */
static void
-load_address (int *counter, int reg, expressionS *ep, int *used_at)
+load_address (int reg, expressionS *ep, int *used_at)
{
- char *p = NULL;
-
if (ep->X_op != O_constant
&& ep->X_op != O_symbol)
{
if (ep->X_op == O_constant)
{
- load_register (counter, reg, ep, HAVE_64BIT_ADDRESSES);
+ load_register (reg, ep, HAVE_64BIT_ADDRESSES);
return;
}
*/
if (HAVE_64BIT_ADDRESSES)
{
- /* We don't do GP optimization for now because RELAX_ENCODE can't
- hold the data for such large chunks. */
+ /* ??? We don't provide a GP-relative alternative for these macros.
+ It used not to be possible with the original relaxation code,
+ but it could be done now. */
if (*used_at == 0 && ! mips_opts.noat)
{
- macro_build (p, counter, ep, "lui", "t,u",
- reg, BFD_RELOC_MIPS_HIGHEST);
- macro_build (p, counter, ep, "lui", "t,u",
- AT, BFD_RELOC_HI16_S);
- macro_build (p, counter, ep, "daddiu", "t,r,j",
- reg, reg, BFD_RELOC_MIPS_HIGHER);
- macro_build (p, counter, ep, "daddiu", "t,r,j",
- AT, AT, BFD_RELOC_LO16);
- macro_build (p, counter, NULL, "dsll32", "d,w,<", reg, reg, 0);
- macro_build (p, counter, NULL, "daddu", "d,v,t", reg, reg, AT);
+ macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
+ macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
+ macro_build (ep, "daddiu", "t,r,j", reg, reg,
+ BFD_RELOC_MIPS_HIGHER);
+ macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
+ macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
+ macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
*used_at = 1;
}
else
{
- macro_build (p, counter, ep, "lui", "t,u",
- reg, BFD_RELOC_MIPS_HIGHEST);
- macro_build (p, counter, ep, "daddiu", "t,r,j",
- reg, reg, BFD_RELOC_MIPS_HIGHER);
- macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
- macro_build (p, counter, ep, "daddiu", "t,r,j",
- reg, reg, BFD_RELOC_HI16_S);
- macro_build (p, counter, NULL, "dsll", "d,w,<", reg, reg, 16);
- macro_build (p, counter, ep, "daddiu", "t,r,j",
- reg, reg, BFD_RELOC_LO16);
+ macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
+ macro_build (ep, "daddiu", "t,r,j", reg, reg,
+ BFD_RELOC_MIPS_HIGHER);
+ macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
+ macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
+ macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
+ macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
}
}
else
&& ! nopic_need_relax (ep->X_add_symbol, 1))
{
relax_start (ep->X_add_symbol);
- macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
+ macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
mips_gp_register, BFD_RELOC_GPREL16);
relax_switch ();
}
- macro_build_lui (p, counter, ep, reg);
- macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
- BFD_RELOC_LO16);
+ macro_build_lui (ep, reg);
+ macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
+ reg, reg, BFD_RELOC_LO16);
if (mips_relax.sequence)
relax_end ();
}
ex.X_add_number = ep->X_add_number;
ep->X_add_number = 0;
relax_start (ep->X_add_symbol);
- macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)",
- reg, BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
+ macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
+ BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
ex.X_op = O_constant;
- macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
+ macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
reg, reg, BFD_RELOC_LO16);
ep->X_add_number = ex.X_add_number;
relax_switch ();
}
- macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
+ macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
if (mips_relax.sequence)
relax_end ();
{
ex.X_add_number = ep->X_add_number;
ep->X_add_number = 0;
- macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
- BFD_RELOC_MIPS_GOT16,
- mips_gp_register);
- macro_build (NULL, counter, NULL, "nop", "");
+ macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
+ BFD_RELOC_MIPS_GOT16, mips_gp_register);
+ load_delay_nop ();
relax_start (ep->X_add_symbol);
relax_switch ();
- macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
+ macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
BFD_RELOC_LO16);
relax_end ();
if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
ex.X_op = O_constant;
- macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
+ macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
reg, reg, BFD_RELOC_LO16);
}
}
ex.X_add_number = ep->X_add_number;
ep->X_add_number = 0;
relax_start (ep->X_add_symbol);
- macro_build (NULL, counter, ep, "lui", "t,u", reg,
- BFD_RELOC_MIPS_GOT_HI16);
- macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
- reg, mips_gp_register);
- macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
- BFD_RELOC_MIPS_GOT_LO16, reg);
+ macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
+ reg, reg, mips_gp_register);
+ macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
+ reg, BFD_RELOC_MIPS_GOT_LO16, reg);
if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
else if (ex.X_add_number)
{
ex.X_op = O_constant;
- macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
- reg, reg, BFD_RELOC_LO16);
+ macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
+ BFD_RELOC_LO16);
}
ep->X_add_number = ex.X_add_number;
relax_switch ();
- macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
+ macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
- macro_build (p + 4, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
- reg, BFD_RELOC_MIPS_GOT_OFST);
+ macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
+ BFD_RELOC_MIPS_GOT_OFST);
relax_end ();
}
else
ex.X_add_number = ep->X_add_number;
ep->X_add_number = 0;
relax_start (ep->X_add_symbol);
- macro_build (NULL, counter, ep, "lui", "t,u", reg,
- BFD_RELOC_MIPS_GOT_HI16);
- macro_build (NULL, counter, NULL, ADDRESS_ADD_INSN, "d,v,t", reg,
- reg, mips_gp_register);
- macro_build (NULL, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
- BFD_RELOC_MIPS_GOT_LO16, reg);
+ macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
+ reg, reg, mips_gp_register);
+ macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
+ reg, BFD_RELOC_MIPS_GOT_LO16, reg);
relax_switch ();
if (reg_needs_delay (mips_gp_register))
{
check is required because the lui which starts the main
instruction stream does not refer to $gp, and so will not
insert the nop which may be required. */
- macro_build (p, counter, NULL, "nop", "");
+ macro_build (NULL, "nop", "");
}
- macro_build (p, counter, ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
+ macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
BFD_RELOC_MIPS_GOT16, mips_gp_register);
- macro_build (p, counter, NULL, "nop", "");
- macro_build (p, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
+ load_delay_nop ();
+ macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
BFD_RELOC_LO16);
relax_end ();
if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
ex.X_op = O_constant;
- macro_build (NULL, counter, &ex, ADDRESS_ADDI_INSN, "t,r,j",
- reg, reg, BFD_RELOC_LO16);
+ macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
+ BFD_RELOC_LO16);
}
}
}
- else if (mips_pic == EMBEDDED_PIC)
- {
- /* We always do
- addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
- */
- macro_build (NULL, counter, ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
- mips_gp_register, BFD_RELOC_GPREL16);
- }
else
abort ();
}
/* Move the contents of register SOURCE into register DEST. */
static void
-move_register (int *counter, int dest, int source)
+move_register (int dest, int source)
{
- macro_build (NULL, counter, NULL, HAVE_32BIT_GPRS ? "addu" : "daddu",
- "d,v,t", dest, source, 0);
+ macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
+ dest, source, 0);
}
/* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
- LOCAL is the sum of a symbol and a 16-bit displacement. The two
- alternatives are:
+ LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
+ The two alternatives are:
Global symbol Local sybmol
------------- ------------
addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
load_got_offset emits the first instruction and add_got_offset
- emits the second. */
+ emits the second for a 16-bit offset or add_got_offset_hilo emits
+ a sequence to add a 32-bit offset using a scratch register. */
static void
-load_got_offset (int *counter, int dest, expressionS *local)
+load_got_offset (int dest, expressionS *local)
{
expressionS global;
global.X_add_number = 0;
relax_start (local->X_add_symbol);
- macro_build (NULL, counter, &global, ADDRESS_LOAD_INSN, "t,o(b)",
- dest, BFD_RELOC_MIPS_GOT16, mips_gp_register);
+ macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
+ BFD_RELOC_MIPS_GOT16, mips_gp_register);
relax_switch ();
- macro_build (NULL, counter, local, ADDRESS_LOAD_INSN, "t,o(b)",
- dest, BFD_RELOC_MIPS_GOT16, mips_gp_register);
+ macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
+ BFD_RELOC_MIPS_GOT16, mips_gp_register);
relax_end ();
}
static void
-add_got_offset (int *counter, int dest, expressionS *local)
+add_got_offset (int dest, expressionS *local)
{
expressionS global;
global.X_add_number = local->X_add_number;
relax_start (local->X_add_symbol);
- macro_build (NULL, counter, &global, ADDRESS_ADDI_INSN, "t,r,j",
+ macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
dest, dest, BFD_RELOC_LO16);
relax_switch ();
- macro_build (NULL, counter, local, ADDRESS_ADDI_INSN, "t,r,j",
- dest, dest, BFD_RELOC_LO16);
+ macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
relax_end ();
}
+static void
+add_got_offset_hilo (int dest, expressionS *local, int tmp)
+{
+ expressionS global;
+ int hold_mips_optimize;
+
+ global.X_op = O_constant;
+ global.X_op_symbol = NULL;
+ global.X_add_symbol = NULL;
+ global.X_add_number = local->X_add_number;
+
+ relax_start (local->X_add_symbol);
+ load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
+ relax_switch ();
+ /* Set mips_optimize around the lui instruction to avoid
+ inserting an unnecessary nop after the lw. */
+ hold_mips_optimize = mips_optimize;
+ mips_optimize = 2;
+ macro_build_lui (&global, tmp);
+ mips_optimize = hold_mips_optimize;
+ macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
+ relax_end ();
+
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
+}
+
/*
* Build macros
* This routine implements the seemingly endless macro or synthesized
register int treg, sreg, dreg, breg;
int tempreg;
int mask;
- int icnt = 0;
int used_at = 0;
expressionS expr1;
const char *s;
int lr = 0;
int imm = 0;
int call = 0;
- offsetT maxnum;
int off;
+ offsetT maxnum;
bfd_reloc_code_real_type r;
int hold_mips_optimize;
mips_any_noreorder = 1;
expr1.X_add_number = 8;
- macro_build (NULL, &icnt, &expr1, "bgez", "s,p", sreg);
+ macro_build (&expr1, "bgez", "s,p", sreg);
if (dreg == sreg)
- macro_build (NULL, &icnt, NULL, "nop", "", 0);
+ macro_build (NULL, "nop", "", 0);
else
- move_register (&icnt, dreg, sreg);
- macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0,
- sreg);
+ move_register (dreg, sreg);
+ macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
--mips_opts.noreorder;
return;
&& imm_expr.X_add_number >= -0x8000
&& imm_expr.X_add_number < 0x8000)
{
- macro_build (NULL, &icnt, &imm_expr, s, "t,r,j", treg, sreg,
- BFD_RELOC_LO16);
+ macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
return;
}
- load_register (&icnt, AT, &imm_expr, dbl);
- macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
+ load_register (AT, &imm_expr, dbl);
+ macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
break;
case M_AND_I:
&& imm_expr.X_add_number < 0x10000)
{
if (mask != M_NOR_I)
- macro_build (NULL, &icnt, &imm_expr, s, "t,r,i", treg, sreg,
- BFD_RELOC_LO16);
+ macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
else
{
- macro_build (NULL, &icnt, &imm_expr, "ori", "t,r,i", treg, sreg,
- BFD_RELOC_LO16);
- macro_build (NULL, &icnt, NULL, "nor", "d,v,t", treg, treg, 0);
+ macro_build (&imm_expr, "ori", "t,r,i",
+ treg, sreg, BFD_RELOC_LO16);
+ macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
}
return;
}
- load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
- macro_build (NULL, &icnt, NULL, s2, "d,v,t", treg, sreg, AT);
+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
+ macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
break;
case M_BEQ_I:
beq_i:
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
{
- macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, 0);
+ macro_build (&offset_expr, s, "s,t,p", sreg, 0);
return;
}
- load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
- macro_build (NULL, &icnt, &offset_expr, s, "s,t,p", sreg, AT);
+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
+ macro_build (&offset_expr, s, "s,t,p", sreg, AT);
break;
case M_BGEL:
case M_BGE:
if (treg == 0)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
- "s,p", sreg);
+ macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
return;
}
if (sreg == 0)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
- "s,p", treg);
+ macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
return;
}
- macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
- macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
- "s,t,p", AT, 0);
+ macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
+ macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
break;
case M_BGTL_I:
do_false:
/* result is always false */
if (! likely)
- macro_build (NULL, &icnt, NULL, "nop", "", 0);
+ macro_build (NULL, "nop", "", 0);
else
- macro_build (NULL, &icnt, &offset_expr, "bnel", "s,t,p", 0, 0);
+ macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
return;
}
if (imm_expr.X_op != O_constant)
likely = 1;
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
- "s,p", sreg);
+ macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
return;
}
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
- "s,p", sreg);
+ macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
return;
}
maxnum = 0x7fffffff;
do_true:
/* result is always true */
as_warn (_("Branch %s is always true"), ip->insn_mo->name);
- macro_build (NULL, &icnt, &offset_expr, "b", "p");
+ macro_build (&offset_expr, "b", "p");
return;
}
- set_at (&icnt, sreg, 0);
- macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
- "s,t,p", AT, 0);
+ set_at (sreg, 0);
+ macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
break;
case M_BGEUL:
goto do_true;
if (sreg == 0)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
+ macro_build (&offset_expr, likely ? "beql" : "beq",
"s,t,p", 0, treg);
return;
}
- macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
- macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
- "s,t,p", AT, 0);
+ macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
+ macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
break;
case M_BGTUL_I:
goto do_true;
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
+ macro_build (&offset_expr, likely ? "bnel" : "bne",
"s,t,p", sreg, 0);
return;
}
- set_at (&icnt, sreg, 1);
- macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
- "s,t,p", AT, 0);
+ set_at (sreg, 1);
+ macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
break;
case M_BGTL:
case M_BGT:
if (treg == 0)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
- "s,p", sreg);
+ macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
return;
}
if (sreg == 0)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
- "s,p", treg);
+ macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
return;
}
- macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
- macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
- "s,t,p", AT, 0);
+ macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
+ macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
break;
case M_BGTUL:
case M_BGTU:
if (treg == 0)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
+ macro_build (&offset_expr, likely ? "bnel" : "bne",
"s,t,p", sreg, 0);
return;
}
if (sreg == 0)
goto do_false;
- macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
- macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
- "s,t,p", AT, 0);
+ macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
+ macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
break;
case M_BLEL:
case M_BLE:
if (treg == 0)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
- "s,p", sreg);
+ macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
return;
}
if (sreg == 0)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "bgezl" : "bgez",
- "s,p", treg);
+ macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
return;
}
- macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, treg, sreg);
- macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
- "s,t,p", AT, 0);
+ macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
+ macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
break;
case M_BLEL_I:
likely = 1;
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
- "s,p", sreg);
+ macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
return;
}
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "blezl" : "blez",
- "s,p", sreg);
+ macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
return;
}
- set_at (&icnt, sreg, 0);
- macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
- "s,t,p", AT, 0);
+ set_at (sreg, 0);
+ macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
break;
case M_BLEUL:
case M_BLEU:
if (treg == 0)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
+ macro_build (&offset_expr, likely ? "beql" : "beq",
"s,t,p", sreg, 0);
return;
}
if (sreg == 0)
goto do_true;
- macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, treg, sreg);
- macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
- "s,t,p", AT, 0);
+ macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
+ macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
break;
case M_BLEUL_I:
goto do_false;
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "beql" : "beq",
+ macro_build (&offset_expr, likely ? "beql" : "beq",
"s,t,p", sreg, 0);
return;
}
- set_at (&icnt, sreg, 1);
- macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
- "s,t,p", AT, 0);
+ set_at (sreg, 1);
+ macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
break;
case M_BLTL:
case M_BLT:
if (treg == 0)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "bltzl" : "bltz",
- "s,p", sreg);
+ macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
return;
}
if (sreg == 0)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "bgtzl" : "bgtz",
- "s,p", treg);
+ macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
return;
}
- macro_build (NULL, &icnt, NULL, "slt", "d,v,t", AT, sreg, treg);
- macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
- "s,t,p", AT, 0);
+ macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
+ macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
break;
case M_BLTUL:
goto do_false;
if (sreg == 0)
{
- macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
+ macro_build (&offset_expr, likely ? "bnel" : "bne",
"s,t,p", 0, treg);
return;
}
- macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", AT, sreg, treg);
- macro_build (NULL, &icnt, &offset_expr, likely ? "bnel" : "bne",
- "s,t,p", AT, 0);
+ macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
+ macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
break;
case M_DEXT:
s = "dextm";
fmt = "t,r,+A,+G";
}
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
- fmt, treg, sreg, pos, size - 1);
+ macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
}
return;
s = "dinsm";
fmt = "t,r,+A,+F";
}
- macro_build ((char *) NULL, &icnt, (expressionS *) NULL, s,
- fmt, treg, sreg, pos, pos + size - 1);
+ macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
+ pos + size - 1);
}
return;
{
as_warn (_("Divide by zero."));
if (mips_trap)
- macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
+ macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
else
- macro_build (NULL, &icnt, NULL, "break", "c", 7);
+ macro_build (NULL, "break", "c", 7);
return;
}
mips_any_noreorder = 1;
if (mips_trap)
{
- macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
- macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
- sreg, treg);
+ macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
+ macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
}
else
{
expr1.X_add_number = 8;
- macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
- macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "z,s,t",
- sreg, treg);
- macro_build (NULL, &icnt, NULL, "break", "c", 7);
+ macro_build (&expr1, "bne", "s,t,p", treg, 0);
+ macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
+ macro_build (NULL, "break", "c", 7);
}
expr1.X_add_number = -1;
- macro_build (NULL, &icnt, &expr1, dbl ? "daddiu" : "addiu", "t,r,j",
- AT, 0, BFD_RELOC_LO16);
+ load_register (AT, &expr1, dbl);
expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
- macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, AT);
+ macro_build (&expr1, "bne", "s,t,p", treg, AT);
if (dbl)
{
expr1.X_add_number = 1;
- macro_build (NULL, &icnt, &expr1, "daddiu", "t,r,j", AT, 0,
- BFD_RELOC_LO16);
- macro_build (NULL, &icnt, NULL, "dsll32", "d,w,<", AT, AT, 31);
+ load_register (AT, &expr1, dbl);
+ macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
}
else
{
expr1.X_add_number = 0x80000000;
- macro_build (NULL, &icnt, &expr1, "lui", "t,u", AT,
- BFD_RELOC_HI16);
+ macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
}
if (mips_trap)
{
- macro_build (NULL, &icnt, NULL, "teq", "s,t,q", sreg, AT, 6);
+ macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
/* We want to close the noreorder block as soon as possible, so
that later insns are available for delay slot filling. */
--mips_opts.noreorder;
else
{
expr1.X_add_number = 8;
- macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", sreg, AT);
- macro_build (NULL, &icnt, NULL, "nop", "", 0);
+ macro_build (&expr1, "bne", "s,t,p", sreg, AT);
+ macro_build (NULL, "nop", "", 0);
/* We want to close the noreorder block as soon as possible, so
that later insns are available for delay slot filling. */
--mips_opts.noreorder;
- macro_build (NULL, &icnt, NULL, "break", "c", 6);
+ macro_build (NULL, "break", "c", 6);
}
- macro_build (NULL, &icnt, NULL, s, "d", dreg);
+ macro_build (NULL, s, "d", dreg);
break;
case M_DIV_3I:
{
as_warn (_("Divide by zero."));
if (mips_trap)
- macro_build (NULL, &icnt, NULL, "teq", "s,t,q", 0, 0, 7);
+ macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
else
- macro_build (NULL, &icnt, NULL, "break", "c", 7);
+ macro_build (NULL, "break", "c", 7);
return;
}
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
{
if (strcmp (s2, "mflo") == 0)
- move_register (&icnt, dreg, sreg);
+ move_register (dreg, sreg);
else
- move_register (&icnt, dreg, 0);
+ move_register (dreg, 0);
return;
}
if (imm_expr.X_op == O_constant
{
if (strcmp (s2, "mflo") == 0)
{
- macro_build (NULL, &icnt, NULL, dbl ? "dneg" : "neg", "d,w",
- dreg, sreg);
+ macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
}
else
- move_register (&icnt, dreg, 0);
+ move_register (dreg, 0);
return;
}
- load_register (&icnt, AT, &imm_expr, dbl);
- macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, AT);
- macro_build (NULL, &icnt, NULL, s2, "d", dreg);
+ load_register (AT, &imm_expr, dbl);
+ macro_build (NULL, s, "z,s,t", sreg, AT);
+ macro_build (NULL, s2, "d", dreg);
break;
case M_DIVU_3:
mips_any_noreorder = 1;
if (mips_trap)
{
- macro_build (NULL, &icnt, NULL, "teq", "s,t,q", treg, 0, 7);
- macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
+ macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
+ macro_build (NULL, s, "z,s,t", sreg, treg);
/* We want to close the noreorder block as soon as possible, so
that later insns are available for delay slot filling. */
--mips_opts.noreorder;
else
{
expr1.X_add_number = 8;
- macro_build (NULL, &icnt, &expr1, "bne", "s,t,p", treg, 0);
- macro_build (NULL, &icnt, NULL, s, "z,s,t", sreg, treg);
+ macro_build (&expr1, "bne", "s,t,p", treg, 0);
+ macro_build (NULL, s, "z,s,t", sreg, treg);
/* We want to close the noreorder block as soon as possible, so
that later insns are available for delay slot filling. */
--mips_opts.noreorder;
- macro_build (NULL, &icnt, NULL, "break", "c", 7);
+ macro_build (NULL, "break", "c", 7);
}
- macro_build (NULL, &icnt, NULL, s2, "d", dreg);
+ macro_build (NULL, s2, "d", dreg);
return;
case M_DLCA_AB:
&& offset_expr.X_add_number >= -0x8000
&& offset_expr.X_add_number < 0x8000)
{
- macro_build (NULL, &icnt, &offset_expr,
+ macro_build (&offset_expr,
(dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
"t,r,j", treg, sreg, BFD_RELOC_LO16);
return;
used_at = 0;
}
- /* When generating embedded PIC code, we permit expressions of
- the form
- la $treg,foo-bar
- la $treg,foo-bar($breg)
- where bar is an address in the current section. These are used
- when getting the addresses of functions. We don't permit
- X_add_number to be non-zero, because if the symbol is
- external the relaxing code needs to know that any addend is
- purely the offset to X_op_symbol. */
- if (mips_pic == EMBEDDED_PIC
- && offset_expr.X_op == O_subtract
- && (symbol_constant_p (offset_expr.X_op_symbol)
- ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
- : (symbol_equated_p (offset_expr.X_op_symbol)
- && (S_GET_SEGMENT
- (symbol_get_value_expression (offset_expr.X_op_symbol)
- ->X_add_symbol)
- == now_seg)))
- && (offset_expr.X_add_number == 0
- || OUTPUT_FLAVOR == bfd_target_elf_flavour))
- {
- if (breg == 0)
- {
- tempreg = treg;
- used_at = 0;
- macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
- BFD_RELOC_PCREL_HI16_S);
- }
- else
- {
- macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
- BFD_RELOC_PCREL_HI16_S);
- macro_build (NULL, &icnt, NULL,
- (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
- "d,v,t", tempreg, tempreg, breg);
- }
- macro_build (NULL, &icnt, &offset_expr,
- (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
- "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
- if (! used_at)
- return;
- break;
- }
-
if (offset_expr.X_op != O_symbol
&& offset_expr.X_op != O_constant)
{
}
if (offset_expr.X_op == O_constant)
- load_register (&icnt, tempreg, &offset_expr,
- ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
+ load_register (tempreg, &offset_expr,
+ (mips_pic == NO_PIC
? (dbl || HAVE_64BIT_ADDRESSES)
: HAVE_64BIT_ADDRESSES));
else if (mips_pic == NO_PIC)
dsll $tempreg,16
daddiu $tempreg,<sym> (BFD_RELOC_LO16)
*/
- char *p = NULL;
if (HAVE_64BIT_ADDRESSES)
{
- /* We don't do GP optimization for now because RELAX_ENCODE can't
- hold the data for such large chunks. */
+ /* ??? We don't provide a GP-relative alternative for
+ these macros. It used not to be possible with the
+ original relaxation code, but it could be done now. */
if (used_at == 0 && ! mips_opts.noat)
{
- macro_build (p, &icnt, &offset_expr, "lui", "t,u",
+ macro_build (&offset_expr, "lui", "t,u",
tempreg, BFD_RELOC_MIPS_HIGHEST);
- macro_build (p, &icnt, &offset_expr, "lui", "t,u",
+ macro_build (&offset_expr, "lui", "t,u",
AT, BFD_RELOC_HI16_S);
- macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
+ macro_build (&offset_expr, "daddiu", "t,r,j",
tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
- macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
+ macro_build (&offset_expr, "daddiu", "t,r,j",
AT, AT, BFD_RELOC_LO16);
- macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
- tempreg, tempreg, 0);
- macro_build (p, &icnt, NULL, "daddu", "d,v,t",
- tempreg, tempreg, AT);
+ macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
+ macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
used_at = 1;
}
else
{
- macro_build (p, &icnt, &offset_expr, "lui", "t,u",
+ macro_build (&offset_expr, "lui", "t,u",
tempreg, BFD_RELOC_MIPS_HIGHEST);
- macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
+ macro_build (&offset_expr, "daddiu", "t,r,j",
tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
- macro_build (p, &icnt, NULL, "dsll", "d,w,<",
- tempreg, tempreg, 16);
- macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
+ macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
+ macro_build (&offset_expr, "daddiu", "t,r,j",
tempreg, tempreg, BFD_RELOC_HI16_S);
- macro_build (p, &icnt, NULL, "dsll", "d,w,<",
- tempreg, tempreg, 16);
- macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
+ macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
+ macro_build (&offset_expr, "daddiu", "t,r,j",
tempreg, tempreg, BFD_RELOC_LO16);
}
}
&& ! nopic_need_relax (offset_expr.X_add_symbol, 1))
{
relax_start (offset_expr.X_add_symbol);
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
- "t,r,j", tempreg, mips_gp_register,
- BFD_RELOC_GPREL16);
+ macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
+ tempreg, mips_gp_register, BFD_RELOC_GPREL16);
relax_switch ();
}
- macro_build_lui (p, &icnt, &offset_expr, tempreg);
- macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
- "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
+ macro_build_lui (&offset_expr, tempreg);
+ macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
+ tempreg, tempreg, BFD_RELOC_LO16);
if (mips_relax.sequence)
relax_end ();
}
if (offset_expr.X_add_number == 0)
{
- char *p = NULL;
-
if (breg == 0 && (call || tempreg == PIC_CALL_REG))
lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
relax_start (offset_expr.X_add_symbol);
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", tempreg, lw_reloc_type, mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ lw_reloc_type, mips_gp_register);
if (breg != 0)
{
/* We're going to put in an addu instruction using
tempreg, so we may as well insert the nop right
now. */
- macro_build (NULL, &icnt, NULL, "nop", "");
+ load_delay_nop ();
}
relax_switch ();
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT16,
- mips_gp_register);
- macro_build (p, &icnt, NULL, "nop", "");
- macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
- "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
+ tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
+ load_delay_nop ();
+ macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
+ tempreg, tempreg, BFD_RELOC_LO16);
relax_end ();
/* FIXME: If breg == 0, and the next instruction uses
$tempreg, then if this variant case is used an extra
else if (offset_expr.X_add_number >= -0x8000
&& offset_expr.X_add_number < 0x8000)
{
- load_got_offset (&icnt, tempreg, &offset_expr);
- macro_build (NULL, &icnt, NULL, "nop", "");
- add_got_offset (&icnt, tempreg, &offset_expr);
+ load_got_offset (tempreg, &offset_expr);
+ load_delay_nop ();
+ add_got_offset (tempreg, &offset_expr);
}
else
{
- int off1;
-
expr1.X_add_number = offset_expr.X_add_number;
offset_expr.X_add_number =
((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
- load_got_offset (&icnt, tempreg, &offset_expr);
+ load_got_offset (tempreg, &offset_expr);
+ offset_expr.X_add_number = expr1.X_add_number;
/* If we are going to add in a base register, and the
target register and the base register are the same,
then we are using AT as a temporary register. Since
current AT (from the global offset table) and the
register into the register now, and pretend we were
not using a base register. */
- if (breg != treg)
- off1 = 0;
- else
+ if (breg == treg)
{
- macro_build (NULL, &icnt, NULL, "nop", "");
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ load_delay_nop ();
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
treg, AT, breg);
breg = 0;
tempreg = treg;
- off1 = -8;
}
-
- /* Set mips_optimize around the lui instruction to avoid
- inserting an unnecessary nop after the lw. */
- hold_mips_optimize = mips_optimize;
- mips_optimize = 2;
- macro_build_lui (NULL, &icnt, &expr1, AT);
- mips_optimize = hold_mips_optimize;
-
- add_got_offset (&icnt, AT, &offset_expr);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- tempreg, tempreg, AT);
+ add_got_offset_hilo (tempreg, &offset_expr, AT);
used_at = 1;
}
}
else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
{
- char *p = NULL;
- int adj = 0;
+ int add_breg_early = 0;
/* If this is a reference to an external, and there is no
constant, or local symbol (*), with or without a
offset_expr.X_add_number = 0;
relax_start (offset_expr.X_add_symbol);
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
- mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
if (expr1.X_add_number >= -0x8000
&& expr1.X_add_number < 0x8000)
{
- macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
- "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
+ macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
+ tempreg, tempreg, BFD_RELOC_LO16);
}
else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
{
else
{
assert (tempreg == AT);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN,
- "d,v,t", treg, AT, breg);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
+ treg, AT, breg);
dreg = treg;
- adj = 4;
+ add_breg_early = 1;
}
- macro_build_lui (NULL, &icnt, &expr1, AT);
- macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
- "t,r,j", AT, AT, BFD_RELOC_LO16);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
dreg, dreg, AT);
used_at = 1;
relax_switch ();
offset_expr.X_add_number = expr1.X_add_number;
- macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
- mips_gp_register);
- if (adj)
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
+ if (add_breg_early)
{
- macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
treg, tempreg, breg);
breg = 0;
tempreg = treg;
else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
{
relax_start (offset_expr.X_add_symbol);
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", tempreg, BFD_RELOC_MIPS_CALL16,
- mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ BFD_RELOC_MIPS_CALL16, mips_gp_register);
relax_switch ();
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
- mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
relax_end ();
}
else
{
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_DISP,
- mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
}
}
else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
{
- int gpdel;
- char *p = NULL;
+ int gpdelay;
int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
expr1.X_add_number = offset_expr.X_add_number;
offset_expr.X_add_number = 0;
relax_start (offset_expr.X_add_symbol);
- if (reg_needs_delay (mips_gp_register))
- gpdel = 4;
- else
- gpdel = 0;
+ gpdelay = reg_needs_delay (mips_gp_register);
if (expr1.X_add_number == 0 && breg == 0
&& (call || tempreg == PIC_CALL_REG))
{
lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
}
- macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
- tempreg, lui_reloc_type);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, tempreg, mips_gp_register);
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
tempreg, lw_reloc_type, tempreg);
if (expr1.X_add_number == 0)
{
- int off;
-
- if (breg == 0)
- off = 0;
- else
+ if (breg != 0)
{
/* We're going to put in an addu instruction using
tempreg, so we may as well insert the nop right
now. */
- macro_build (NULL, &icnt, NULL, "nop", "");
- off = 4;
+ load_delay_nop ();
}
}
else if (expr1.X_add_number >= -0x8000
&& expr1.X_add_number < 0x8000)
{
- macro_build (NULL, &icnt, NULL, "nop", "");
- macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
+ load_delay_nop ();
+ macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
tempreg, tempreg, BFD_RELOC_LO16);
}
else
{
- int adj, dreg;
+ int dreg;
/* If we are going to add in a base register, and the
target register and the base register are the same,
register into the register now, and pretend we were
not using a base register. */
if (breg != treg)
- {
- adj = 0;
- dreg = tempreg;
- }
+ dreg = tempreg;
else
{
assert (tempreg == AT);
- macro_build (NULL, &icnt, NULL, "nop", "");
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ load_delay_nop ();
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
treg, AT, breg);
dreg = treg;
- adj = 8;
}
- /* Set mips_optimize around the lui instruction to avoid
- inserting an unnecessary nop after the lw. */
- hold_mips_optimize = mips_optimize;
- mips_optimize = 2;
- macro_build_lui (NULL, &icnt, &expr1, AT);
- mips_optimize = hold_mips_optimize;
-
- macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
- AT, AT, BFD_RELOC_LO16);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- dreg, dreg, AT);
+ load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
used_at = 1;
}
((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
relax_switch ();
- if (gpdel > 0)
+ if (gpdelay)
{
/* This is needed because this instruction uses $gp, but
the first instruction on the main stream does not. */
- macro_build (p, &icnt, NULL, "nop", "");
+ macro_build (NULL, "nop", "");
}
- macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
- tempreg, local_reloc_type, mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ local_reloc_type, mips_gp_register);
if (expr1.X_add_number >= -0x8000
&& expr1.X_add_number < 0x8000)
{
- macro_build (p, &icnt, NULL, "nop", "");
- macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
- "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
+ load_delay_nop ();
+ macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
+ tempreg, tempreg, BFD_RELOC_LO16);
/* FIXME: If add_number is 0, and there was no base
register, the external symbol case ended with a load,
so if the symbol turns out to not be external, and
/* We must add in the base register now, as in the
external symbol case. */
assert (tempreg == AT);
- macro_build (p, &icnt, NULL, "nop", "");
- macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ load_delay_nop ();
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
treg, AT, breg);
tempreg = treg;
/* We set breg to 0 because we have arranged to add
breg = 0;
}
- macro_build_lui (p, &icnt, &expr1, AT);
- macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
+ macro_build_lui (&expr1, AT);
+ macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
AT, AT, BFD_RELOC_LO16);
- macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, tempreg, AT);
}
relax_end ();
}
else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
{
- char *p = NULL;
int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
- int adj = 0;
+ int add_breg_early = 0;
/* This is the large GOT case. If this is a reference to an
external symbol, and there is no constant, we want
lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
}
- macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
- tempreg, lui_reloc_type);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, tempreg, mips_gp_register);
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", tempreg, lw_reloc_type, tempreg);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
+ tempreg, lw_reloc_type, tempreg);
if (expr1.X_add_number == 0)
;
else if (expr1.X_add_number >= -0x8000
&& expr1.X_add_number < 0x8000)
{
- macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN, "t,r,j",
+ macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
tempreg, tempreg, BFD_RELOC_LO16);
}
else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
else
{
assert (tempreg == AT);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
treg, AT, breg);
dreg = treg;
- adj = 4;
+ add_breg_early = 1;
}
- /* Set mips_optimize around the lui instruction to avoid
- inserting an unnecessary nop after the lw. */
- macro_build_lui (NULL, &icnt, &expr1, AT);
- macro_build (NULL, &icnt, &expr1, ADDRESS_ADDI_INSN,
- "t,r,j", AT, AT, BFD_RELOC_LO16);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- dreg, dreg, AT);
+ load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
used_at = 1;
}
relax_switch ();
offset_expr.X_add_number = expr1.X_add_number;
- macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
- tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
- macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
- tempreg, tempreg, BFD_RELOC_MIPS_GOT_OFST);
- if (adj)
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
+ tempreg, BFD_RELOC_MIPS_GOT_OFST);
+ if (add_breg_early)
{
- macro_build (p + 8, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
treg, tempreg, breg);
breg = 0;
tempreg = treg;
}
relax_end ();
}
- else if (mips_pic == EMBEDDED_PIC)
- {
- /* We use
- addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
- */
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
- tempreg, mips_gp_register, BFD_RELOC_GPREL16);
- }
else
abort ();
{
char *s;
- if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
+ if (mips_pic == NO_PIC)
s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
else
s = ADDRESS_ADD_INSN;
- macro_build (NULL, &icnt, NULL, s, "d,v,t", treg, tempreg, breg);
+ macro_build (NULL, s, "d,v,t", treg, tempreg, breg);
}
if (! used_at)
requires an absolute address. We convert it to a b
instruction. */
if (mips_pic == NO_PIC)
- macro_build (NULL, &icnt, &offset_expr, "j", "a");
+ macro_build (&offset_expr, "j", "a");
else
- macro_build (NULL, &icnt, &offset_expr, "b", "p");
+ macro_build (&offset_expr, "b", "p");
return;
/* The jal instructions must be handled as macros because when
dreg = RA;
/* Fall through. */
case M_JAL_2:
- if (mips_pic == NO_PIC
- || mips_pic == EMBEDDED_PIC)
- macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
+ if (mips_pic == NO_PIC)
+ macro_build (NULL, "jalr", "d,s", dreg, sreg);
else if (mips_pic == SVR4_PIC)
{
if (sreg != PIC_CALL_REG)
as_warn (_("MIPS PIC call to register other than $25"));
- macro_build (NULL, &icnt, NULL, "jalr", "d,s", dreg, sreg);
+ macro_build (NULL, "jalr", "d,s", dreg, sreg);
if (! HAVE_NEWABI)
{
if (mips_cprestore_offset < 0)
mips_cprestore_valid = 1;
}
expr1.X_add_number = mips_cprestore_offset;
- macro_build_ldst_constoffset (NULL, &icnt, &expr1,
- ADDRESS_LOAD_INSN,
+ macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
mips_gp_register,
mips_frame_reg,
HAVE_64BIT_ADDRESSES);
case M_JAL_A:
if (mips_pic == NO_PIC)
- macro_build (NULL, &icnt, &offset_expr, "jal", "a");
+ macro_build (&offset_expr, "jal", "a");
else if (mips_pic == SVR4_PIC)
{
- char *p = NULL;
-
/* If this is a reference to an external symbol, and we are
using a small GOT, we want
lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
if (! mips_big_got)
{
relax_start (offset_expr.X_add_symbol);
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
+ PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
mips_gp_register);
relax_switch ();
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
+ PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
mips_gp_register);
relax_end ();
}
else
{
relax_start (offset_expr.X_add_symbol);
- macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
- PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", PIC_CALL_REG,
- BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
+ macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
+ BFD_RELOC_MIPS_CALL_HI16);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
+ PIC_CALL_REG, mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
+ PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
+ PIC_CALL_REG);
relax_switch ();
- macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", PIC_CALL_REG,
- BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
- macro_build (p + 4, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
- "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
+ PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
+ mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
+ PIC_CALL_REG, PIC_CALL_REG,
BFD_RELOC_MIPS_GOT_OFST);
relax_end ();
}
- macro_build_jalr (icnt, &offset_expr);
+ macro_build_jalr (&offset_expr);
}
else
{
relax_start (offset_expr.X_add_symbol);
if (! mips_big_got)
{
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
+ PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
mips_gp_register);
- macro_build (NULL, &icnt, NULL, "nop", "");
+ load_delay_nop ();
relax_switch ();
}
else
{
- int gpdel;
-
- if (reg_needs_delay (mips_gp_register))
- gpdel = 4;
- else
- gpdel = 0;
- macro_build (NULL, &icnt, &offset_expr, "lui", "t,u",
- PIC_CALL_REG, BFD_RELOC_MIPS_CALL_HI16);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- PIC_CALL_REG, PIC_CALL_REG, mips_gp_register);
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", PIC_CALL_REG,
- BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
- macro_build (NULL, &icnt, NULL, "nop", "");
+ int gpdelay;
+
+ gpdelay = reg_needs_delay (mips_gp_register);
+ macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
+ BFD_RELOC_MIPS_CALL_HI16);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
+ PIC_CALL_REG, mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
+ PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
+ PIC_CALL_REG);
+ load_delay_nop ();
relax_switch ();
- if (gpdel > 0)
- {
- macro_build (p, &icnt, NULL, "nop", "");
- p += 4;
- }
+ if (gpdelay)
+ macro_build (NULL, "nop", "");
}
- macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
+ PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
mips_gp_register);
- macro_build (p, &icnt, NULL, "nop", "");
- macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
- "t,r,j", PIC_CALL_REG, PIC_CALL_REG,
- BFD_RELOC_LO16);
+ load_delay_nop ();
+ macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
+ PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
relax_end ();
- macro_build_jalr (icnt, &offset_expr);
+ macro_build_jalr (&offset_expr);
if (mips_cprestore_offset < 0)
as_warn (_("No .cprestore pseudo-op used in PIC code"));
mips_cprestore_valid = 1;
}
if (mips_opts.noreorder)
- macro_build (NULL, &icnt, NULL, "nop", "");
+ macro_build (NULL, "nop", "");
expr1.X_add_number = mips_cprestore_offset;
- macro_build_ldst_constoffset (NULL, &icnt, &expr1,
- ADDRESS_LOAD_INSN,
+ macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
mips_gp_register,
mips_frame_reg,
HAVE_64BIT_ADDRESSES);
}
}
}
- else if (mips_pic == EMBEDDED_PIC)
- {
- macro_build (NULL, &icnt, &offset_expr, "bal", "p");
- /* The linker may expand the call to a longer sequence which
- uses $at, so we must break rather than return. */
- break;
- }
else
abort ();
^ 0x80000000) - 0x80000000);
}
- /* For embedded PIC, we allow loads where the offset is calculated
- by subtracting a symbol in the current segment from an unknown
- symbol, relative to a base register, e.g.:
- <op> $treg, <sym>-<localsym>($breg)
- This is used by the compiler for switch statements. */
- if (mips_pic == EMBEDDED_PIC
- && offset_expr.X_op == O_subtract
- && (symbol_constant_p (offset_expr.X_op_symbol)
- ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
- : (symbol_equated_p (offset_expr.X_op_symbol)
- && (S_GET_SEGMENT
- (symbol_get_value_expression (offset_expr.X_op_symbol)
- ->X_add_symbol)
- == now_seg)))
- && breg != 0
- && (offset_expr.X_add_number == 0
- || OUTPUT_FLAVOR == bfd_target_elf_flavour))
- {
- /* For this case, we output the instructions:
- lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
- addiu $tempreg,$tempreg,$breg
- <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
- If the relocation would fit entirely in 16 bits, it would be
- nice to emit:
- <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
- instead, but that seems quite difficult. */
- macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
- BFD_RELOC_PCREL_HI16_S);
- macro_build (NULL, &icnt, NULL,
- ((bfd_arch_bits_per_address (stdoutput) == 32
- || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
- ? "addu" : "daddu"),
- "d,v,t", tempreg, tempreg, breg);
- macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
- BFD_RELOC_PCREL_LO16, tempreg);
- if (! used_at)
- return;
- break;
- }
-
if (offset_expr.X_op != O_constant
&& offset_expr.X_op != O_symbol)
{
if (mips_pic == NO_PIC
|| offset_expr.X_op == O_constant)
{
- char *p = NULL;
-
/* If this is a reference to a GP relative symbol, and there
is no base register, we want
<op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
&& offset_expr.X_op == O_constant
&& ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
{
- p = NULL;
-
- /* We don't do GP optimization for now because RELAX_ENCODE can't
- hold the data for such large chunks. */
+ /* ??? We don't provide a GP-relative alternative for
+ these macros. It used not to be possible with the
+ original relaxation code, but it could be done now. */
if (used_at == 0 && ! mips_opts.noat)
{
- macro_build (p, &icnt, &offset_expr, "lui", "t,u",
- tempreg, BFD_RELOC_MIPS_HIGHEST);
- macro_build (p, &icnt, &offset_expr, "lui", "t,u",
- AT, BFD_RELOC_HI16_S);
- macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
- tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
+ macro_build (&offset_expr, "lui", "t,u", tempreg,
+ BFD_RELOC_MIPS_HIGHEST);
+ macro_build (&offset_expr, "lui", "t,u", AT,
+ BFD_RELOC_HI16_S);
+ macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
+ tempreg, BFD_RELOC_MIPS_HIGHER);
if (breg != 0)
- macro_build (p, &icnt, NULL, "daddu", "d,v,t",
- AT, AT, breg);
- macro_build (p, &icnt, NULL, "dsll32", "d,w,<",
- tempreg, tempreg, 0);
- macro_build (p, &icnt, NULL, "daddu", "d,v,t",
- tempreg, tempreg, AT);
- macro_build (p, &icnt, &offset_expr, s, fmt, treg,
- BFD_RELOC_LO16, tempreg);
+ macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
+ macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
+ macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
+ macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
+ tempreg);
used_at = 1;
}
else
{
- macro_build (p, &icnt, &offset_expr, "lui", "t,u",
- tempreg, BFD_RELOC_MIPS_HIGHEST);
- macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
- tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
- macro_build (p, &icnt, NULL, "dsll", "d,w,<",
- tempreg, tempreg, 16);
- macro_build (p, &icnt, &offset_expr, "daddiu", "t,r,j",
- tempreg, tempreg, BFD_RELOC_HI16_S);
- macro_build (p, &icnt, NULL, "dsll", "d,w,<",
- tempreg, tempreg, 16);
+ macro_build (&offset_expr, "lui", "t,u", tempreg,
+ BFD_RELOC_MIPS_HIGHEST);
+ macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
+ tempreg, BFD_RELOC_MIPS_HIGHER);
+ macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
+ macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
+ tempreg, BFD_RELOC_HI16_S);
+ macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
if (breg != 0)
- macro_build (p, &icnt, NULL, "daddu", "d,v,t",
+ macro_build (NULL, "daddu", "d,v,t",
tempreg, tempreg, breg);
- macro_build (p, &icnt, &offset_expr, s, fmt, treg,
+ macro_build (&offset_expr, s, fmt, treg,
BFD_RELOC_LO16, tempreg);
}
if (breg == 0)
{
- if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
- || nopic_need_relax (offset_expr.X_add_symbol, 1))
- p = NULL;
- else
+ if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
+ && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
{
relax_start (offset_expr.X_add_symbol);
- macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
- BFD_RELOC_GPREL16, mips_gp_register);
+ macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
+ mips_gp_register);
relax_switch ();
used_at = 0;
}
- macro_build_lui (p, &icnt, &offset_expr, tempreg);
- macro_build (p, &icnt, &offset_expr, s, fmt, treg,
+ macro_build_lui (&offset_expr, tempreg);
+ macro_build (&offset_expr, s, fmt, treg,
BFD_RELOC_LO16, tempreg);
if (mips_relax.sequence)
relax_end ();
}
else
{
- if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
- || nopic_need_relax (offset_expr.X_add_symbol, 1))
- p = NULL;
- else
+ if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
+ && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
{
relax_start (offset_expr.X_add_symbol);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, breg, mips_gp_register);
- macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
+ macro_build (&offset_expr, s, fmt, treg,
BFD_RELOC_GPREL16, tempreg);
relax_switch ();
}
- macro_build_lui (p, &icnt, &offset_expr, tempreg);
- macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build_lui (&offset_expr, tempreg);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, tempreg, breg);
- macro_build (p, &icnt, &offset_expr, s, fmt, treg,
+ macro_build (&offset_expr, s, fmt, treg,
BFD_RELOC_LO16, tempreg);
if (mips_relax.sequence)
relax_end ();
}
else if (mips_pic == SVR4_PIC && ! mips_big_got)
{
- char *p = NULL;
int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
/* If this is a reference to an external symbol, we want
assert (offset_expr.X_op == O_symbol);
if (HAVE_NEWABI)
{
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", tempreg, BFD_RELOC_MIPS_GOT_PAGE,
- mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
if (breg != 0)
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, tempreg, breg);
- macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
+ macro_build (&offset_expr, s, fmt, treg,
BFD_RELOC_MIPS_GOT_OFST, tempreg);
if (! used_at)
if (expr1.X_add_number < -0x8000
|| expr1.X_add_number >= 0x8000)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
- tempreg, lw_reloc_type, mips_gp_register);
- macro_build (NULL, &icnt, NULL, "nop", "");
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ lw_reloc_type, mips_gp_register);
+ load_delay_nop ();
relax_start (offset_expr.X_add_symbol);
relax_switch ();
- macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN,
- "t,r,j", tempreg, tempreg, BFD_RELOC_LO16);
+ macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
+ tempreg, BFD_RELOC_LO16);
relax_end ();
if (breg != 0)
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, tempreg, breg);
- macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
- tempreg);
+ macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
}
else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
{
- int gpdel;
- char *p = NULL;
+ int gpdelay;
/* If this is a reference to an external symbol, we want
lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
if (expr1.X_add_number < -0x8000
|| expr1.X_add_number >= 0x8000)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
- if (reg_needs_delay (mips_gp_register))
- gpdel = 4;
- else
- gpdel = 0;
+ gpdelay = reg_needs_delay (mips_gp_register);
relax_start (offset_expr.X_add_symbol);
- macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
+ macro_build (&offset_expr, "lui", "t,u", tempreg,
BFD_RELOC_MIPS_GOT_HI16);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- tempreg, tempreg, mips_gp_register);
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
- tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
+ mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ BFD_RELOC_MIPS_GOT_LO16, tempreg);
relax_switch ();
- if (gpdel > 0)
- macro_build (p, &icnt, NULL, "nop", "");
- macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
- tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
- macro_build (p, &icnt, NULL, "nop", "");
- macro_build (p, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
- tempreg, tempreg, BFD_RELOC_LO16);
+ if (gpdelay)
+ macro_build (NULL, "nop", "");
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ BFD_RELOC_MIPS_GOT16, mips_gp_register);
+ load_delay_nop ();
+ macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
+ tempreg, BFD_RELOC_LO16);
relax_end ();
if (breg != 0)
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, tempreg, breg);
- macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
- tempreg);
+ macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
}
else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
{
- char *p = NULL;
- int bregsz = breg != 0 ? 4 : 0;
-
/* If this is a reference to an external symbol, we want
lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
add $tempreg,$tempreg,$gp
|| expr1.X_add_number >= 0x8000)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
relax_start (offset_expr.X_add_symbol);
- macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", tempreg,
+ macro_build (&offset_expr, "lui", "t,u", tempreg,
BFD_RELOC_MIPS_GOT_HI16);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- tempreg, tempreg, mips_gp_register);
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
- tempreg, BFD_RELOC_MIPS_GOT_LO16, tempreg);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
+ mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ BFD_RELOC_MIPS_GOT_LO16, tempreg);
if (breg != 0)
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, tempreg, breg);
- macro_build (NULL, &icnt, &expr1, s, fmt, treg, BFD_RELOC_LO16,
- tempreg);
+ macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
relax_switch ();
offset_expr.X_add_number = expr1.X_add_number;
- macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
- tempreg, BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
+ BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
if (breg != 0)
- macro_build (p + 4, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
tempreg, tempreg, breg);
- macro_build (p + 4 + bregsz, &icnt, &offset_expr, s, fmt, treg,
+ macro_build (&offset_expr, s, fmt, treg,
BFD_RELOC_MIPS_GOT_OFST, tempreg);
relax_end ();
}
- else if (mips_pic == EMBEDDED_PIC)
- {
- /* If there is no base register, we want
- <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
- If there is a base register, we want
- addu $tempreg,$breg,$gp
- <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
- */
- assert (offset_expr.X_op == O_symbol);
- if (breg == 0)
- {
- macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
- BFD_RELOC_GPREL16, mips_gp_register);
- used_at = 0;
- }
- else
- {
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- tempreg, breg, mips_gp_register);
- macro_build (NULL, &icnt, &offset_expr, s, fmt, treg,
- BFD_RELOC_GPREL16, tempreg);
- }
- }
else
abort ();
case M_LI:
case M_LI_S:
- load_register (&icnt, treg, &imm_expr, 0);
+ load_register (treg, &imm_expr, 0);
return;
case M_DLI:
- load_register (&icnt, treg, &imm_expr, 1);
+ load_register (treg, &imm_expr, 1);
return;
case M_LI_SS:
if (imm_expr.X_op == O_constant)
{
- load_register (&icnt, AT, &imm_expr, 0);
- macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
+ load_register (AT, &imm_expr, 0);
+ macro_build (NULL, "mtc1", "t,G", AT, treg);
break;
}
else
(offset_expr.X_add_symbol)),
".lit4") == 0
&& offset_expr.X_add_number == 0);
- macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)", treg,
+ macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
BFD_RELOC_MIPS_LITERAL, mips_gp_register);
return;
}
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
{
if (HAVE_64BIT_GPRS)
- load_register (&icnt, treg, &imm_expr, 1);
+ load_register (treg, &imm_expr, 1);
else
{
int hreg, lreg;
}
if (hreg <= 31)
- load_register (&icnt, hreg, &imm_expr, 0);
+ load_register (hreg, &imm_expr, 0);
if (lreg <= 31)
{
if (offset_expr.X_op == O_absent)
- move_register (&icnt, lreg, 0);
+ move_register (lreg, 0);
else
{
assert (offset_expr.X_op == O_constant);
- load_register (&icnt, lreg, &offset_expr, 0);
+ load_register (lreg, &offset_expr, 0);
}
}
}
upper 16 bits of the address. */
if (mips_pic == NO_PIC)
{
- macro_build_lui (NULL, &icnt, &offset_expr, AT);
+ macro_build_lui (&offset_expr, AT);
}
else if (mips_pic == SVR4_PIC)
{
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
- AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
- }
- else if (mips_pic == EMBEDDED_PIC)
- {
- /* For embedded PIC we pick up the entire address off $gp in
- a single instruction. */
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
- AT, mips_gp_register, BFD_RELOC_GPREL16);
- offset_expr.X_op = O_constant;
- offset_expr.X_add_number = 0;
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
+ BFD_RELOC_MIPS_GOT16, mips_gp_register);
}
else
abort ();
/* Now we load the register(s). */
if (HAVE_64BIT_GPRS)
- macro_build (NULL, &icnt, &offset_expr, "ld", "t,o(b)", treg,
- BFD_RELOC_LO16, AT);
+ macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
else
{
- macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)", treg,
- BFD_RELOC_LO16, AT);
+ macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
if (treg != RA)
{
/* FIXME: How in the world do we deal with the possible
overflow here? */
offset_expr.X_add_number += 4;
- macro_build (NULL, &icnt, &offset_expr, "lw", "t,o(b)",
+ macro_build (&offset_expr, "lw", "t,o(b)",
treg + 1, BFD_RELOC_LO16, AT);
}
}
OFFSET_EXPR. */
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
{
- load_register (&icnt, AT, &imm_expr, HAVE_64BIT_FPRS);
+ load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
if (HAVE_64BIT_FPRS)
{
assert (HAVE_64BIT_GPRS);
- macro_build (NULL, &icnt, NULL, "dmtc1", "t,S", AT, treg);
+ macro_build (NULL, "dmtc1", "t,S", AT, treg);
}
else
{
- macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg + 1);
+ macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
if (offset_expr.X_op == O_absent)
- macro_build (NULL, &icnt, NULL, "mtc1", "t,G", 0, treg);
+ macro_build (NULL, "mtc1", "t,G", 0, treg);
else
{
assert (offset_expr.X_op == O_constant);
- load_register (&icnt, AT, &offset_expr, 0);
- macro_build (NULL, &icnt, NULL, "mtc1", "t,G", AT, treg);
+ load_register (AT, &offset_expr, 0);
+ macro_build (NULL, "mtc1", "t,G", AT, treg);
}
}
break;
{
if (mips_opts.isa != ISA_MIPS1)
{
- macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
+ macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
BFD_RELOC_MIPS_LITERAL, mips_gp_register);
return;
}
{
assert (strcmp (s, RDATA_SECTION_NAME) == 0);
if (mips_pic == SVR4_PIC)
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN,
- "t,o(b)", AT, BFD_RELOC_MIPS_GOT16,
- mips_gp_register);
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
+ BFD_RELOC_MIPS_GOT16, mips_gp_register);
else
{
/* FIXME: This won't work for a 64 bit address. */
- macro_build_lui (NULL, &icnt, &offset_expr, AT);
+ macro_build_lui (&offset_expr, AT);
}
if (mips_opts.isa != ISA_MIPS1)
{
- macro_build (NULL, &icnt, &offset_expr, "ldc1", "T,o(b)", treg,
- BFD_RELOC_LO16, AT);
+ macro_build (&offset_expr, "ldc1", "T,o(b)",
+ treg, BFD_RELOC_LO16, AT);
break;
}
breg = AT;
r = BFD_RELOC_LO16;
dob:
assert (mips_opts.isa == ISA_MIPS1);
- macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
+ macro_build (&offset_expr, "lwc1", "T,o(b)",
target_big_endian ? treg + 1 : treg, r, breg);
/* FIXME: A possible overflow which I don't know how to deal
with. */
offset_expr.X_add_number += 4;
- macro_build (NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
+ macro_build (&offset_expr, "lwc1", "T,o(b)",
target_big_endian ? treg : treg + 1, r, breg);
if (breg != AT)
fmt = "t,o(b)";
ldd_std:
- /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
- loads for the case of doing a pair of loads to simulate an 'ld'.
- This is not currently done by the compiler, and assembly coders
- writing embedded-pic code can cope. */
-
if (offset_expr.X_op != O_symbol
&& offset_expr.X_op != O_constant)
{
if (mips_pic == NO_PIC
|| offset_expr.X_op == O_constant)
{
- char *p = NULL;
-
/* If this is a reference to a GP relative symbol, we want
<op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
<op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
the last case. */
if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
|| nopic_need_relax (offset_expr.X_add_symbol, 1))
- {
- p = NULL;
- used_at = 1;
- }
+ used_at = 1;
else
{
- int off;
-
relax_start (offset_expr.X_add_symbol);
if (breg == 0)
{
tempreg = mips_gp_register;
- off = 0;
used_at = 0;
}
else
{
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
AT, breg, mips_gp_register);
tempreg = AT;
- off = 4;
used_at = 1;
}
/* Itbl support may require additional care here. */
- macro_build (NULL, &icnt, &offset_expr, s, fmt,
- coproc ? treg + 1 : treg,
+ macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
BFD_RELOC_GPREL16, tempreg);
offset_expr.X_add_number += 4;
hold_mips_optimize = mips_optimize;
mips_optimize = 2;
/* Itbl support may require additional care here. */
- macro_build (NULL, &icnt, &offset_expr, s, fmt,
- coproc ? treg : treg + 1,
+ macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
BFD_RELOC_GPREL16, tempreg);
mips_optimize = hold_mips_optimize;
offset_expr.X_op = O_constant;
}
}
- macro_build_lui (p, &icnt, &offset_expr, AT);
+ macro_build_lui (&offset_expr, AT);
if (breg != 0)
- macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- AT, breg, AT);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
- macro_build (p, &icnt, &offset_expr, s, fmt,
- coproc ? treg + 1 : treg,
+ macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
BFD_RELOC_LO16, AT);
/* FIXME: How do we handle overflow here? */
offset_expr.X_add_number += 4;
/* Itbl support may require additional care here. */
- macro_build (p, &icnt, &offset_expr, s, fmt,
- coproc ? treg : treg + 1,
+ macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
BFD_RELOC_LO16, AT);
if (mips_relax.sequence)
relax_end ();
}
else if (mips_pic == SVR4_PIC && ! mips_big_got)
{
- int off;
-
/* If this is a reference to an external symbol, we want
lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
nop
if (expr1.X_add_number < -0x8000
|| expr1.X_add_number >= 0x8000 - 4)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
- if (breg == 0)
- off = 0;
- else
- off = 4;
- load_got_offset (&icnt, AT, &offset_expr);
- macro_build (NULL, &icnt, NULL, "nop", "");
+ load_got_offset (AT, &offset_expr);
+ load_delay_nop ();
if (breg != 0)
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- AT, breg, AT);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
/* Set mips_optimize to 2 to avoid inserting an undesired
nop. */
/* Itbl support may require additional care here. */
relax_start (offset_expr.X_add_symbol);
- macro_build (NULL, &icnt, &expr1, s, fmt,
- coproc ? treg + 1 : treg, BFD_RELOC_LO16, AT);
+ macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
+ BFD_RELOC_LO16, AT);
expr1.X_add_number += 4;
- macro_build (NULL, &icnt, &expr1, s, fmt,
- coproc ? treg : treg + 1, BFD_RELOC_LO16, AT);
+ macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
+ BFD_RELOC_LO16, AT);
relax_switch ();
- macro_build (NULL, &icnt, &offset_expr, s, fmt,
- coproc ? treg + 1 : treg, BFD_RELOC_LO16, AT);
+ macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
+ BFD_RELOC_LO16, AT);
offset_expr.X_add_number += 4;
- macro_build (NULL, &icnt, &offset_expr, s, fmt,
- coproc ? treg : treg + 1, BFD_RELOC_LO16, AT);
+ macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
+ BFD_RELOC_LO16, AT);
relax_end ();
mips_optimize = hold_mips_optimize;
}
else if (mips_pic == SVR4_PIC)
{
- int gpdel, off;
- char *p = NULL;
+ int gpdelay;
/* If this is a reference to an external symbol, we want
lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
if (expr1.X_add_number < -0x8000
|| expr1.X_add_number >= 0x8000 - 4)
as_bad (_("PIC code offset overflow (max 16 signed bits)"));
- if (reg_needs_delay (mips_gp_register))
- gpdel = 4;
- else
- gpdel = 0;
- if (breg == 0)
- off = 0;
- else
- off = 4;
+ gpdelay = reg_needs_delay (mips_gp_register);
relax_start (offset_expr.X_add_symbol);
- macro_build (NULL, &icnt, &offset_expr, "lui", "t,u", AT,
- BFD_RELOC_MIPS_GOT_HI16);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
+ macro_build (&offset_expr, "lui", "t,u",
+ AT, BFD_RELOC_MIPS_GOT_HI16);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
AT, AT, mips_gp_register);
- macro_build (NULL, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
AT, BFD_RELOC_MIPS_GOT_LO16, AT);
- macro_build (NULL, &icnt, NULL, "nop", "");
+ load_delay_nop ();
if (breg != 0)
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- AT, breg, AT);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
- macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg + 1 : treg,
+ macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
BFD_RELOC_LO16, AT);
expr1.X_add_number += 4;
hold_mips_optimize = mips_optimize;
mips_optimize = 2;
/* Itbl support may require additional care here. */
- macro_build (NULL, &icnt, &expr1, s, fmt, coproc ? treg : treg + 1,
+ macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
BFD_RELOC_LO16, AT);
mips_optimize = hold_mips_optimize;
expr1.X_add_number -= 4;
relax_switch ();
offset_expr.X_add_number = expr1.X_add_number;
- if (gpdel > 0)
- macro_build (p, &icnt, NULL, "nop", "");
- macro_build (p, &icnt, &offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
- AT, BFD_RELOC_MIPS_GOT16, mips_gp_register);
- macro_build (p, &icnt, NULL, "nop", "");
+ if (gpdelay)
+ macro_build (NULL, "nop", "");
+ macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
+ BFD_RELOC_MIPS_GOT16, mips_gp_register);
+ load_delay_nop ();
if (breg != 0)
- macro_build (p, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- AT, breg, AT);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
- macro_build (p, &icnt, &offset_expr, s, fmt,
- coproc ? treg + 1 : treg, BFD_RELOC_LO16, AT);
+ macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
+ BFD_RELOC_LO16, AT);
offset_expr.X_add_number += 4;
/* Set mips_optimize to 2 to avoid inserting an undesired
hold_mips_optimize = mips_optimize;
mips_optimize = 2;
/* Itbl support may require additional care here. */
- macro_build (p, &icnt, &offset_expr, s, fmt,
- coproc ? treg : treg + 1, BFD_RELOC_LO16, AT);
+ macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
+ BFD_RELOC_LO16, AT);
mips_optimize = hold_mips_optimize;
relax_end ();
}
- else if (mips_pic == EMBEDDED_PIC)
- {
- /* If there is no base register, we use
- <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
- <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
- If we have a base register, we use
- addu $at,$breg,$gp
- <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
- <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
- */
- if (breg == 0)
- {
- tempreg = mips_gp_register;
- used_at = 0;
- }
- else
- {
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- AT, breg, mips_gp_register);
- tempreg = AT;
- used_at = 1;
- }
-
- /* Itbl support may require additional care here. */
- macro_build (NULL, &icnt, &offset_expr, s, fmt,
- coproc ? treg + 1 : treg,
- BFD_RELOC_GPREL16, tempreg);
- offset_expr.X_add_number += 4;
- /* Itbl support may require additional care here. */
- macro_build (NULL, &icnt, &offset_expr, s, fmt,
- coproc ? treg : treg + 1,
- BFD_RELOC_GPREL16, tempreg);
- }
else
abort ();
s = "sw";
sd_ob:
assert (HAVE_32BIT_ADDRESSES);
- macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
- BFD_RELOC_LO16, breg);
+ macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
offset_expr.X_add_number += 4;
- macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
- BFD_RELOC_LO16, breg);
+ macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
return;
/* New code added to support COPZ instructions.
copz:
/* For now we just do C (same as Cz). The parameter will be
stored in insn_opcode by mips_ip. */
- macro_build (NULL, &icnt, NULL, s, "C", ip->insn_opcode);
+ macro_build (NULL, s, "C", ip->insn_opcode);
return;
case M_MOVE:
- move_register (&icnt, dreg, sreg);
+ move_register (dreg, sreg);
return;
#ifdef LOSING_COMPILER
s = ip->insn_mo->name;
s2 = "cop3";
coproc = ITBL_DECODE_PNUM (immed_expr);;
- macro_build (NULL, &icnt, &immed_expr, s, "C");
+ macro_build (&immed_expr, s, "C");
return;
}
macro2 (ip);
register int treg, sreg, dreg, breg;
int tempreg;
int mask;
- int icnt = 0;
int used_at;
expressionS expr1;
const char *s;
int off;
offsetT maxnum;
bfd_reloc_code_real_type r;
- char *p;
treg = (ip->insn_opcode >> 16) & 0x1f;
dreg = (ip->insn_opcode >> 11) & 0x1f;
case M_DMUL:
dbl = 1;
case M_MUL:
- macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
- sreg, treg);
- macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
+ macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
+ macro_build (NULL, "mflo", "d", dreg);
return;
case M_DMUL_I:
/* The MIPS assembler some times generates shifts and adds. I'm
not trying to be that fancy. GCC should do this for us
anyway. */
- load_register (&icnt, AT, &imm_expr, dbl);
- macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
- sreg, AT);
- macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
+ load_register (AT, &imm_expr, dbl);
+ macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
+ macro_build (NULL, "mflo", "d", dreg);
break;
case M_DMULO_I:
++mips_opts.noreorder;
mips_any_noreorder = 1;
if (imm)
- load_register (&icnt, AT, &imm_expr, dbl);
- macro_build (NULL, &icnt, NULL, dbl ? "dmult" : "mult", "s,t",
- sreg, imm ? AT : treg);
- macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
- macro_build (NULL, &icnt, NULL, dbl ? "dsra32" : "sra", "d,w,<",
- dreg, dreg, RA);
- macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
+ load_register (AT, &imm_expr, dbl);
+ macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
+ macro_build (NULL, "mflo", "d", dreg);
+ macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
+ macro_build (NULL, "mfhi", "d", AT);
if (mips_trap)
- macro_build (NULL, &icnt, NULL, "tne", "s,t,q", dreg, AT, 6);
+ macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
else
{
expr1.X_add_number = 8;
- macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", dreg, AT);
- macro_build (NULL, &icnt, NULL, "nop", "", 0);
- macro_build (NULL, &icnt, NULL, "break", "c", 6);
+ macro_build (&expr1, "beq", "s,t,p", dreg, AT);
+ macro_build (NULL, "nop", "", 0);
+ macro_build (NULL, "break", "c", 6);
}
--mips_opts.noreorder;
- macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
+ macro_build (NULL, "mflo", "d", dreg);
break;
case M_DMULOU_I:
++mips_opts.noreorder;
mips_any_noreorder = 1;
if (imm)
- load_register (&icnt, AT, &imm_expr, dbl);
- macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "s,t",
+ load_register (AT, &imm_expr, dbl);
+ macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
sreg, imm ? AT : treg);
- macro_build (NULL, &icnt, NULL, "mfhi", "d", AT);
- macro_build (NULL, &icnt, NULL, "mflo", "d", dreg);
+ macro_build (NULL, "mfhi", "d", AT);
+ macro_build (NULL, "mflo", "d", dreg);
if (mips_trap)
- macro_build (NULL, &icnt, NULL, "tne", "s,t,q", AT, 0, 6);
+ macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
else
{
expr1.X_add_number = 8;
- macro_build (NULL, &icnt, &expr1, "beq", "s,t,p", AT, 0);
- macro_build (NULL, &icnt, NULL, "nop", "", 0);
- macro_build (NULL, &icnt, NULL, "break", "c", 6);
+ macro_build (&expr1, "beq", "s,t,p", AT, 0);
+ macro_build (NULL, "nop", "", 0);
+ macro_build (NULL, "break", "c", 6);
}
--mips_opts.noreorder;
break;
tempreg = dreg;
used_at = 0;
}
- macro_build (NULL, &icnt, NULL, "dnegu", "d,w", tempreg, treg);
- macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg,
- tempreg);
+ macro_build (NULL, "dnegu", "d,w", tempreg, treg);
+ macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
if (used_at)
break;
return;
}
- macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg);
- macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", AT, sreg, AT);
- macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", dreg, sreg, treg);
- macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
+ macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
+ macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
+ macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
+ macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
break;
case M_ROL:
tempreg = dreg;
used_at = 0;
}
- macro_build (NULL, &icnt, NULL, "negu", "d,w", tempreg, treg);
- macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg,
- tempreg);
+ macro_build (NULL, "negu", "d,w", tempreg, treg);
+ macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
if (used_at)
break;
return;
}
- macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
- macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", AT, sreg, AT);
- macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", dreg, sreg, treg);
- macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
+ macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
+ macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
+ macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
+ macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
break;
case M_DROL_I:
{
rot = (64 - rot) & 0x3f;
if (rot >= 32)
- macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
- dreg, sreg, rot - 32);
+ macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
else
- macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
- dreg, sreg, rot);
+ macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
return;
}
if (rot == 0)
{
- macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
+ macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
return;
}
l = (rot < 0x20) ? "dsll" : "dsll32";
r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
rot &= 0x1f;
- macro_build (NULL, &icnt, NULL, l, "d,w,<", AT, sreg, rot);
- macro_build (NULL, &icnt, NULL, r, "d,w,<", dreg, sreg,
- (0x20 - rot) & 0x1f);
- macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
+ macro_build (NULL, l, "d,w,<", AT, sreg, rot);
+ macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
}
break;
rot = imm_expr.X_add_number & 0x1f;
if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
{
- macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg,
- (32 - rot) & 0x1f);
+ macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
return;
}
if (rot == 0)
{
- macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
+ macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
return;
}
- macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, sreg, rot);
- macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg,
- (0x20 - rot) & 0x1f);
- macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
+ macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
+ macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
}
break;
case M_DROR:
if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
{
- macro_build (NULL, &icnt, NULL, "drorv", "d,t,s", dreg, sreg, treg);
+ macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
return;
}
- macro_build (NULL, &icnt, NULL, "dsubu", "d,v,t", AT, 0, treg);
- macro_build (NULL, &icnt, NULL, "dsllv", "d,t,s", AT, sreg, AT);
- macro_build (NULL, &icnt, NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
- macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
+ macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
+ macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
+ macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
+ macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
break;
case M_ROR:
if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
{
- macro_build (NULL, &icnt, NULL, "rorv", "d,t,s", dreg, sreg, treg);
+ macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
return;
}
- macro_build (NULL, &icnt, NULL, "subu", "d,v,t", AT, 0, treg);
- macro_build (NULL, &icnt, NULL, "sllv", "d,t,s", AT, sreg, AT);
- macro_build (NULL, &icnt, NULL, "srlv", "d,t,s", dreg, sreg, treg);
- macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
+ macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
+ macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
+ macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
+ macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
break;
case M_DROR_I:
if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
{
if (rot >= 32)
- macro_build (NULL, &icnt, NULL, "dror32", "d,w,<",
- dreg, sreg, rot - 32);
+ macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
else
- macro_build (NULL, &icnt, NULL, "dror", "d,w,<",
- dreg, sreg, rot);
+ macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
return;
}
if (rot == 0)
{
- macro_build (NULL, &icnt, NULL, "dsrl", "d,w,<", dreg, sreg, 0);
+ macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
return;
}
r = (rot < 0x20) ? "dsrl" : "dsrl32";
l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
rot &= 0x1f;
- macro_build (NULL, &icnt, NULL, r, "d,w,<", AT, sreg, rot);
- macro_build (NULL, &icnt, NULL, l, "d,w,<", dreg, sreg,
- (0x20 - rot) & 0x1f);
- macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
+ macro_build (NULL, r, "d,w,<", AT, sreg, rot);
+ macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
}
break;
rot = imm_expr.X_add_number & 0x1f;
if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
{
- macro_build (NULL, &icnt, NULL, "ror", "d,w,<", dreg, sreg, rot);
+ macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
return;
}
if (rot == 0)
{
- macro_build (NULL, &icnt, NULL, "srl", "d,w,<", dreg, sreg, 0);
+ macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
return;
}
- macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, sreg, rot);
- macro_build (NULL, &icnt, NULL, "sll", "d,w,<", dreg, sreg,
- (0x20 - rot) & 0x1f);
- macro_build (NULL, &icnt, NULL, "or", "d,v,t", dreg, dreg, AT);
+ macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
+ macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
+ macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
}
break;
assert (mips_opts.isa == ISA_MIPS1);
/* Even on a big endian machine $fn comes before $fn+1. We have
to adjust when storing to memory. */
- macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
- target_big_endian ? treg + 1 : treg,
- BFD_RELOC_LO16, breg);
+ macro_build (&offset_expr, "swc1", "T,o(b)",
+ target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
offset_expr.X_add_number += 4;
- macro_build (NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
- target_big_endian ? treg : treg + 1,
- BFD_RELOC_LO16, breg);
+ macro_build (&offset_expr, "swc1", "T,o(b)",
+ target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
return;
case M_SEQ:
if (sreg == 0)
- macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, treg,
- BFD_RELOC_LO16);
+ macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
else if (treg == 0)
- macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
- BFD_RELOC_LO16);
+ macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
else
{
- macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
- macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
- BFD_RELOC_LO16);
+ macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
+ macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
}
return;
case M_SEQ_I:
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
{
- macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, sreg,
- BFD_RELOC_LO16);
+ macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
return;
}
if (sreg == 0)
{
as_warn (_("Instruction %s: result is always false"),
ip->insn_mo->name);
- move_register (&icnt, dreg, 0);
+ move_register (dreg, 0);
return;
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= 0
&& imm_expr.X_add_number < 0x10000)
{
- macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
- BFD_RELOC_LO16);
+ macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
used_at = 0;
}
else if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number < 0)
{
imm_expr.X_add_number = -imm_expr.X_add_number;
- macro_build (NULL, &icnt, &imm_expr,
- HAVE_32BIT_GPRS ? "addiu" : "daddiu",
+ macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
"t,r,j", dreg, sreg, BFD_RELOC_LO16);
used_at = 0;
}
else
{
- load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
- macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
+ macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
used_at = 1;
}
- macro_build (NULL, &icnt, &expr1, "sltiu", "t,r,j", dreg, dreg,
- BFD_RELOC_LO16);
+ macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
if (used_at)
break;
return;
case M_SGEU:
s = "sltu";
sge:
- macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, sreg, treg);
- macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
- BFD_RELOC_LO16);
+ macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
+ macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
return;
case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
&& imm_expr.X_add_number >= -0x8000
&& imm_expr.X_add_number < 0x8000)
{
- macro_build (NULL, &icnt, &imm_expr,
- mask == M_SGE_I ? "slti" : "sltiu",
- "t,r,j", dreg, sreg, BFD_RELOC_LO16);
+ macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
+ dreg, sreg, BFD_RELOC_LO16);
used_at = 0;
}
else
{
- load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
- macro_build (NULL, &icnt, NULL, mask == M_SGE_I ? "slt" : "sltu",
- "d,v,t", dreg, sreg, AT);
+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
+ macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
+ dreg, sreg, AT);
used_at = 1;
}
- macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
- BFD_RELOC_LO16);
+ macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
if (used_at)
break;
return;
case M_SGTU:
s = "sltu";
sgt:
- macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
+ macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
return;
case M_SGT_I: /* sreg > I <==> I < sreg */
case M_SGTU_I:
s = "sltu";
sgti:
- load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
- macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
+ macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
break;
case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
case M_SLEU:
s = "sltu";
sle:
- macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, treg, sreg);
- macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
- BFD_RELOC_LO16);
+ macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
+ macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
return;
case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
case M_SLEU_I:
s = "sltu";
slei:
- load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
- macro_build (NULL, &icnt, NULL, s, "d,v,t", dreg, AT, sreg);
- macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", dreg, dreg,
- BFD_RELOC_LO16);
+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
+ macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
+ macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
break;
case M_SLT_I:
&& imm_expr.X_add_number >= -0x8000
&& imm_expr.X_add_number < 0x8000)
{
- macro_build (NULL, &icnt, &imm_expr, "slti", "t,r,j", dreg, sreg,
- BFD_RELOC_LO16);
+ macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
return;
}
- load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
- macro_build (NULL, &icnt, NULL, "slt", "d,v,t", dreg, sreg, AT);
+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
+ macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
break;
case M_SLTU_I:
&& imm_expr.X_add_number >= -0x8000
&& imm_expr.X_add_number < 0x8000)
{
- macro_build (NULL, &icnt, &imm_expr, "sltiu", "t,r,j", dreg, sreg,
+ macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
BFD_RELOC_LO16);
return;
}
- load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
- macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, sreg, AT);
+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
+ macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
break;
case M_SNE:
if (sreg == 0)
- macro_build (NULL, &icnt, NULL, "sltu","d,v,t", dreg, 0, treg);
+ macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
else if (treg == 0)
- macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
+ macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
else
{
- macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, treg);
- macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
+ macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
+ macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
}
return;
case M_SNE_I:
if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
{
- macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, sreg);
+ macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
return;
}
if (sreg == 0)
{
as_warn (_("Instruction %s: result is always true"),
ip->insn_mo->name);
- macro_build (NULL, &icnt, &expr1,
- HAVE_32BIT_GPRS ? "addiu" : "daddiu",
- "t,r,j", dreg, 0, BFD_RELOC_LO16);
+ macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
+ dreg, 0, BFD_RELOC_LO16);
return;
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= 0
&& imm_expr.X_add_number < 0x10000)
{
- macro_build (NULL, &icnt, &imm_expr, "xori", "t,r,i", dreg, sreg,
- BFD_RELOC_LO16);
+ macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
used_at = 0;
}
else if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number < 0)
{
imm_expr.X_add_number = -imm_expr.X_add_number;
- macro_build (NULL, &icnt, &imm_expr,
- HAVE_32BIT_GPRS ? "addiu" : "daddiu",
+ macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
"t,r,j", dreg, sreg, BFD_RELOC_LO16);
used_at = 0;
}
else
{
- load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
- macro_build (NULL, &icnt, NULL, "xor", "d,v,t", dreg, sreg, AT);
+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
+ macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
used_at = 1;
}
- macro_build (NULL, &icnt, NULL, "sltu", "d,v,t", dreg, 0, dreg);
+ macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
if (used_at)
break;
return;
&& imm_expr.X_add_number <= 0x8000)
{
imm_expr.X_add_number = -imm_expr.X_add_number;
- macro_build (NULL, &icnt, &imm_expr, dbl ? "daddi" : "addi",
- "t,r,j", dreg, sreg, BFD_RELOC_LO16);
+ macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
+ dreg, sreg, BFD_RELOC_LO16);
return;
}
- load_register (&icnt, AT, &imm_expr, dbl);
- macro_build (NULL, &icnt, NULL, dbl ? "dsub" : "sub", "d,v,t",
- dreg, sreg, AT);
+ load_register (AT, &imm_expr, dbl);
+ macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
break;
case M_DSUBU_I:
&& imm_expr.X_add_number <= 0x8000)
{
imm_expr.X_add_number = -imm_expr.X_add_number;
- macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu",
- "t,r,j", dreg, sreg, BFD_RELOC_LO16);
+ macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
+ dreg, sreg, BFD_RELOC_LO16);
return;
}
- load_register (&icnt, AT, &imm_expr, dbl);
- macro_build (NULL, &icnt, NULL, dbl ? "dsubu" : "subu", "d,v,t",
- dreg, sreg, AT);
+ load_register (AT, &imm_expr, dbl);
+ macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
break;
case M_TEQ_I:
case M_TNE_I:
s = "tne";
trap:
- load_register (&icnt, AT, &imm_expr, HAVE_64BIT_GPRS);
- macro_build (NULL, &icnt, NULL, s, "s,t", sreg, AT);
+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
+ macro_build (NULL, s, "s,t", sreg, AT);
break;
case M_TRUNCWS:
mips_emit_delays (TRUE);
++mips_opts.noreorder;
mips_any_noreorder = 1;
- macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
- macro_build (NULL, &icnt, NULL, "cfc1", "t,G", treg, RA);
- macro_build (NULL, &icnt, NULL, "nop", "");
+ macro_build (NULL, "cfc1", "t,G", treg, RA);
+ macro_build (NULL, "cfc1", "t,G", treg, RA);
+ macro_build (NULL, "nop", "");
expr1.X_add_number = 3;
- macro_build (NULL, &icnt, &expr1, "ori", "t,r,i", AT, treg,
- BFD_RELOC_LO16);
+ macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
expr1.X_add_number = 2;
- macro_build (NULL, &icnt, &expr1, "xori", "t,r,i", AT, AT,
- BFD_RELOC_LO16);
- macro_build (NULL, &icnt, NULL, "ctc1", "t,G", AT, RA);
- macro_build (NULL, &icnt, NULL, "nop", "");
- macro_build (NULL, &icnt, NULL,
- mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s",
- "D,S", dreg, sreg);
- macro_build (NULL, &icnt, NULL, "ctc1", "t,G", treg, RA);
- macro_build (NULL, &icnt, NULL, "nop", "");
+ macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
+ macro_build (NULL, "ctc1", "t,G", AT, RA);
+ macro_build (NULL, "nop", "");
+ macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
+ dreg, sreg);
+ macro_build (NULL, "ctc1", "t,G", treg, RA);
+ macro_build (NULL, "nop", "");
--mips_opts.noreorder;
break;
as_bad (_("operand overflow"));
if (! target_big_endian)
++offset_expr.X_add_number;
- macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", AT,
- BFD_RELOC_LO16, breg);
+ macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
if (! target_big_endian)
--offset_expr.X_add_number;
else
++offset_expr.X_add_number;
- macro_build (NULL, &icnt, &offset_expr, "lbu", "t,o(b)", treg,
- BFD_RELOC_LO16, breg);
- macro_build (NULL, &icnt, NULL, "sll", "d,w,<", AT, AT, 8);
- macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
+ macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
+ macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
+ macro_build (NULL, "or", "d,v,t", treg, treg, AT);
break;
case M_ULD:
tempreg = AT;
if (! target_big_endian)
offset_expr.X_add_number += off;
- macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", tempreg,
- BFD_RELOC_LO16, breg);
+ macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
if (! target_big_endian)
offset_expr.X_add_number -= off;
else
offset_expr.X_add_number += off;
- macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", tempreg,
- BFD_RELOC_LO16, breg);
+ macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
/* If necessary, move the result in tempreg the final destination. */
if (treg == tempreg)
return;
/* Protect second load's delay slot. */
- if (!gpr_interlocks)
- macro_build (NULL, &icnt, NULL, "nop", "");
- move_register (&icnt, treg, tempreg);
+ load_delay_nop ();
+ move_register (treg, tempreg);
break;
case M_ULD_A:
off = 3;
ulwa:
used_at = 1;
- load_address (&icnt, AT, &offset_expr, &used_at);
+ load_address (AT, &offset_expr, &used_at);
if (breg != 0)
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- AT, AT, breg);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
if (! target_big_endian)
expr1.X_add_number = off;
else
expr1.X_add_number = 0;
- macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
- BFD_RELOC_LO16, AT);
+ macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
if (! target_big_endian)
expr1.X_add_number = 0;
else
expr1.X_add_number = off;
- macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
- BFD_RELOC_LO16, AT);
+ macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
break;
case M_ULH_A:
case M_ULHU_A:
used_at = 1;
- load_address (&icnt, AT, &offset_expr, &used_at);
+ load_address (AT, &offset_expr, &used_at);
if (breg != 0)
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- AT, AT, breg);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
if (target_big_endian)
expr1.X_add_number = 0;
- macro_build (NULL, &icnt, &expr1,
- mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
+ macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
treg, BFD_RELOC_LO16, AT);
if (target_big_endian)
expr1.X_add_number = 1;
else
expr1.X_add_number = 0;
- macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)",
- AT, BFD_RELOC_LO16, AT);
- macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
- macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
+ macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
+ macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
+ macro_build (NULL, "or", "d,v,t", treg, treg, AT);
break;
case M_USH:
as_bad (_("operand overflow"));
if (target_big_endian)
++offset_expr.X_add_number;
- macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", treg,
- BFD_RELOC_LO16, breg);
- macro_build (NULL, &icnt, NULL, "srl", "d,w,<", AT, treg, 8);
+ macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
+ macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
if (target_big_endian)
--offset_expr.X_add_number;
else
++offset_expr.X_add_number;
- macro_build (NULL, &icnt, &offset_expr, "sb", "t,o(b)", AT,
- BFD_RELOC_LO16, breg);
+ macro_build (&offset_expr, "sb", "t,o(b)", AT, BFD_RELOC_LO16, breg);
break;
case M_USD:
as_bad (_("operand overflow"));
if (! target_big_endian)
offset_expr.X_add_number += off;
- macro_build (NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
- BFD_RELOC_LO16, breg);
+ macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
if (! target_big_endian)
offset_expr.X_add_number -= off;
else
offset_expr.X_add_number += off;
- macro_build (NULL, &icnt, &offset_expr, s2, "t,o(b)", treg,
- BFD_RELOC_LO16, breg);
+ macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
return;
case M_USD_A:
off = 3;
uswa:
used_at = 1;
- load_address (&icnt, AT, &offset_expr, &used_at);
+ load_address (AT, &offset_expr, &used_at);
if (breg != 0)
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- AT, AT, breg);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
if (! target_big_endian)
expr1.X_add_number = off;
else
expr1.X_add_number = 0;
- macro_build (NULL, &icnt, &expr1, s, "t,o(b)", treg,
- BFD_RELOC_LO16, AT);
+ macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
if (! target_big_endian)
expr1.X_add_number = 0;
else
expr1.X_add_number = off;
- macro_build (NULL, &icnt, &expr1, s2, "t,o(b)", treg,
- BFD_RELOC_LO16, AT);
+ macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
break;
case M_USH_A:
used_at = 1;
- load_address (&icnt, AT, &offset_expr, &used_at);
+ load_address (AT, &offset_expr, &used_at);
if (breg != 0)
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- AT, AT, breg);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
if (! target_big_endian)
expr1.X_add_number = 0;
- macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
- BFD_RELOC_LO16, AT);
- macro_build (NULL, &icnt, NULL, "srl", "d,w,<", treg, treg, 8);
+ macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
+ macro_build (NULL, "srl", "d,w,<", treg, treg, 8);
if (! target_big_endian)
expr1.X_add_number = 1;
else
expr1.X_add_number = 0;
- macro_build (NULL, &icnt, &expr1, "sb", "t,o(b)", treg,
- BFD_RELOC_LO16, AT);
+ macro_build (&expr1, "sb", "t,o(b)", treg, BFD_RELOC_LO16, AT);
if (! target_big_endian)
expr1.X_add_number = 0;
else
expr1.X_add_number = 1;
- macro_build (NULL, &icnt, &expr1, "lbu", "t,o(b)", AT,
- BFD_RELOC_LO16, AT);
- macro_build (NULL, &icnt, NULL, "sll", "d,w,<", treg, treg, 8);
- macro_build (NULL, &icnt, NULL, "or", "d,v,t", treg, treg, AT);
+ macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
+ macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
+ macro_build (NULL, "or", "d,v,t", treg, treg, AT);
break;
default:
{
int mask;
int xreg, yreg, zreg, tmp;
- int icnt;
expressionS expr1;
int dbl;
const char *s, *s2, *s3;
yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
- icnt = 0;
-
expr1.X_op = O_constant;
expr1.X_op_symbol = NULL;
expr1.X_add_symbol = NULL;
mips_emit_delays (TRUE);
++mips_opts.noreorder;
mips_any_noreorder = 1;
- macro_build (NULL, &icnt, NULL, dbl ? "ddiv" : "div", "0,x,y",
- xreg, yreg);
+ macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
expr1.X_add_number = 2;
- macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
- macro_build (NULL, &icnt, NULL, "break", "6", 7);
+ macro_build (&expr1, "bnez", "x,p", yreg);
+ macro_build (NULL, "break", "6", 7);
/* FIXME: The normal code checks for of -1 / -0x80000000 here,
since that causes an overflow. We should do that as well,
but I don't see how to do the comparisons without a temporary
register. */
--mips_opts.noreorder;
- macro_build (NULL, &icnt, NULL, s, "x", zreg);
+ macro_build (NULL, s, "x", zreg);
break;
case M_DIVU_3:
mips_emit_delays (TRUE);
++mips_opts.noreorder;
mips_any_noreorder = 1;
- macro_build (NULL, &icnt, NULL, s, "0,x,y", xreg, yreg);
+ macro_build (NULL, s, "0,x,y", xreg, yreg);
expr1.X_add_number = 2;
- macro_build (NULL, &icnt, &expr1, "bnez", "x,p", yreg);
- macro_build (NULL, &icnt, NULL, "break", "6", 7);
+ macro_build (&expr1, "bnez", "x,p", yreg);
+ macro_build (NULL, "break", "6", 7);
--mips_opts.noreorder;
- macro_build (NULL, &icnt, NULL, s2, "x", zreg);
+ macro_build (NULL, s2, "x", zreg);
break;
case M_DMUL:
dbl = 1;
case M_MUL:
- macro_build (NULL, &icnt, NULL, dbl ? "dmultu" : "multu", "x,y",
- xreg, yreg);
- macro_build (NULL, &icnt, NULL, "mflo", "x", zreg);
+ macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
+ macro_build (NULL, "mflo", "x", zreg);
return;
case M_DSUBU_I:
if (imm_expr.X_op != O_constant)
as_bad (_("Unsupported large constant"));
imm_expr.X_add_number = -imm_expr.X_add_number;
- macro_build (NULL, &icnt, &imm_expr, dbl ? "daddiu" : "addiu", "y,x,4",
- yreg, xreg);
+ macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "y,x,4", yreg, xreg);
break;
case M_SUBU_I_2:
if (imm_expr.X_op != O_constant)
as_bad (_("Unsupported large constant"));
imm_expr.X_add_number = -imm_expr.X_add_number;
- macro_build (NULL, &icnt, &imm_expr, "addiu", "x,k", xreg);
+ macro_build (&imm_expr, "addiu", "x,k", xreg);
break;
case M_DSUBU_I_2:
if (imm_expr.X_op != O_constant)
as_bad (_("Unsupported large constant"));
imm_expr.X_add_number = -imm_expr.X_add_number;
- macro_build (NULL, &icnt, &imm_expr, "daddiu", "y,j", yreg);
+ macro_build (&imm_expr, "daddiu", "y,j", yreg);
break;
case M_BEQ:
yreg = tmp;
do_branch:
- macro_build (NULL, &icnt, NULL, s, "x,y", xreg, yreg);
- macro_build (NULL, &icnt, &offset_expr, s2, "p");
+ macro_build (NULL, s, "x,y", xreg, yreg);
+ macro_build (&offset_expr, s2, "p");
break;
case M_BEQ_I:
++imm_expr.X_add_number;
do_branch_i:
- macro_build (NULL, &icnt, &imm_expr, s, s3, xreg);
- macro_build (NULL, &icnt, &offset_expr, s2, "p");
+ macro_build (&imm_expr, s, s3, xreg);
+ macro_build (&offset_expr, s2, "p");
break;
case M_ABS:
expr1.X_add_number = 0;
- macro_build (NULL, &icnt, &expr1, "slti", "x,8", yreg);
+ macro_build (&expr1, "slti", "x,8", yreg);
if (xreg != yreg)
- move_register (&icnt, xreg, yreg);
+ move_register (xreg, yreg);
expr1.X_add_number = 2;
- macro_build (NULL, &icnt, &expr1, "bteqz", "p");
- macro_build (NULL, &icnt, NULL, "neg", "x,w", xreg, xreg);
+ macro_build (&expr1, "bteqz", "p");
+ macro_build (NULL, "neg", "x,w", xreg, xreg);
}
}
ip->insn_opcode |= (imm_expr.X_add_number
<< (OP_SH_VSEL +
(is_qh ? 2 : 1)));
+ imm_expr.X_op = O_absent;
if (*s != ']')
as_warn(_("Expecting ']' found '%s'"), s);
else
The .lit4 and .lit8 sections are only used if
permitted by the -G argument.
- When generating embedded PIC code, we use the
- .lit8 section but not the .lit4 section (we can do
- .lit4 inline easily; we need to put .lit8
- somewhere in the data segment, and using .lit8
- permits the linker to eventually combine identical
- .lit8 entries).
-
The code below needs to know whether the target register
is 32 or 64 bits wide. It relies on the fact 'f' and
'F' are used with GPR-based instructions and 'l' and
if (*args == 'f'
|| (*args == 'l'
- && (! USE_GLOBAL_POINTER_OPT
- || mips_pic == EMBEDDED_PIC
- || g_switch_value < 4
+ && (g_switch_value < 4
|| (temp[0] == 0 && temp[1] == 0)
|| (temp[2] == 0 && temp[3] == 0))))
{
default: /* unused default case avoids warnings. */
case 'L':
newname = RDATA_SECTION_NAME;
- if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
- || mips_pic == EMBEDDED_PIC)
+ if (g_switch_value >= 8)
newname = ".lit8";
break;
case 'F':
- if (mips_pic == EMBEDDED_PIC)
- newname = ".lit8";
- else
- newname = RDATA_SECTION_NAME;
+ newname = RDATA_SECTION_NAME;
break;
case 'l':
- assert (!USE_GLOBAL_POINTER_OPT
- || g_switch_value >= 4);
+ assert (g_switch_value >= 4);
newname = ".lit4";
break;
}
{
as_bad ("relocation %s isn't supported by the current ABI",
percent_op[i].str);
- *reloc = BFD_RELOC_LO16;
+ *reloc = BFD_RELOC_UNUSED;
}
return TRUE;
}
expression in *EP and the relocations in the array starting
at RELOC. Return the number of relocation operators used.
- On exit, EXPR_END points to the first character after the expression.
- If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
+ On exit, EXPR_END points to the first character after the expression. */
static size_t
my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
expr_end = str;
- if (reloc_index == 0)
- reloc[0] = BFD_RELOC_LO16;
- else
+ if (reloc_index != 0)
{
prev_reloc_op_frag = frag_now;
for (i = 0; i < reloc_index; i++)
#define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
{"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
{"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
-#define OPTION_FIX_VR4122 (OPTION_FIX_BASE + 2)
-#define OPTION_NO_FIX_VR4122 (OPTION_FIX_BASE + 3)
- {"mfix-vr4122-bugs", no_argument, NULL, OPTION_FIX_VR4122},
- {"no-mfix-vr4122-bugs", no_argument, NULL, OPTION_NO_FIX_VR4122},
+#define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
+#define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
+ {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
+ {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
/* Miscellaneous options. */
#define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
-#define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
- {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
-#define OPTION_TRAP (OPTION_MISC_BASE + 1)
+#define OPTION_TRAP (OPTION_MISC_BASE + 0)
{"trap", no_argument, NULL, OPTION_TRAP},
{"no-break", no_argument, NULL, OPTION_TRAP},
-#define OPTION_BREAK (OPTION_MISC_BASE + 2)
+#define OPTION_BREAK (OPTION_MISC_BASE + 1)
{"break", no_argument, NULL, OPTION_BREAK},
{"no-trap", no_argument, NULL, OPTION_BREAK},
-#define OPTION_EB (OPTION_MISC_BASE + 3)
+#define OPTION_EB (OPTION_MISC_BASE + 2)
{"EB", no_argument, NULL, OPTION_EB},
-#define OPTION_EL (OPTION_MISC_BASE + 4)
+#define OPTION_EL (OPTION_MISC_BASE + 3)
{"EL", no_argument, NULL, OPTION_EL},
-#define OPTION_FP32 (OPTION_MISC_BASE + 5)
+#define OPTION_FP32 (OPTION_MISC_BASE + 4)
{"mfp32", no_argument, NULL, OPTION_FP32},
-#define OPTION_GP32 (OPTION_MISC_BASE + 6)
+#define OPTION_GP32 (OPTION_MISC_BASE + 5)
{"mgp32", no_argument, NULL, OPTION_GP32},
-#define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
+#define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
{"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
-#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
+#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
{"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
-#define OPTION_FP64 (OPTION_MISC_BASE + 9)
+#define OPTION_FP64 (OPTION_MISC_BASE + 8)
{"mfp64", no_argument, NULL, OPTION_FP64},
-#define OPTION_GP64 (OPTION_MISC_BASE + 10)
+#define OPTION_GP64 (OPTION_MISC_BASE + 9)
{"mgp64", no_argument, NULL, OPTION_GP64},
-#define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
-#define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
+#define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
+#define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
{"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
{"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
/* ELF-specific options. */
#ifdef OBJ_ELF
-#define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
+#define OPTION_ELF_BASE (OPTION_MISC_BASE + 12)
#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
{"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
{"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
mips_opts.ase_mips3d = 0;
break;
- case OPTION_MEMBEDDED_PIC:
- mips_pic = EMBEDDED_PIC;
- if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
- {
- as_bad (_("-G may not be used with embedded PIC code"));
- return 0;
- }
- g_switch_value = 0x7fffffff;
- break;
-
- case OPTION_FIX_VR4122:
- mips_fix_4122_bugs = 1;
+ case OPTION_FIX_VR4120:
+ mips_fix_vr4120 = 1;
break;
- case OPTION_NO_FIX_VR4122:
- mips_fix_4122_bugs = 0;
+ case OPTION_NO_FIX_VR4120:
+ mips_fix_vr4120 = 0;
break;
case OPTION_RELAX_BRANCH:
#endif /* OBJ_ELF */
case 'G':
- if (! USE_GLOBAL_POINTER_OPT)
- {
- as_bad (_("-G is not supported for this configuration"));
- return 0;
- }
- else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
+ if (mips_pic == SVR4_PIC)
{
- as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
+ as_bad (_("-G may not be used with SVR4 PIC code"));
return 0;
}
else
#endif
}
-/* Sort any unmatched HI16_S relocs so that they immediately precede
- the corresponding LO reloc. This is called before md_apply_fix3 and
- tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
- explicit use of the %hi modifier. */
+/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
+ the corresponding LO16 reloc. This is called before md_apply_fix3 and
+ tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
+ relocation operators.
+
+ For our purposes, a %lo() expression matches a %got() or %hi()
+ expression if:
+
+ (a) it refers to the same symbol; and
+ (b) the offset applied in the %lo() expression is no lower than
+ the offset applied in the %got() or %hi().
+
+ (b) allows us to cope with code like:
+
+ lui $4,%hi(foo)
+ lh $4,%lo(foo+2)($4)
+
+ ...which is legal on RELA targets, and has a well-defined behaviour
+ if the user knows that adding 2 to "foo" will not induce a carry to
+ the high 16 bits.
+
+ When several %lo()s match a particular %got() or %hi(), we use the
+ following rules to distinguish them:
+
+ (1) %lo()s with smaller offsets are a better match than %lo()s with
+ higher offsets.
+
+ (2) %lo()s with no matching %got() or %hi() are better than those
+ that already have a matching %got() or %hi().
+
+ (3) later %lo()s are better than earlier %lo()s.
+
+ These rules are applied in order.
+
+ (1) means, among other things, that %lo()s with identical offsets are
+ chosen if they exist.
+
+ (2) means that we won't associate several high-part relocations with
+ the same low-part relocation unless there's no alternative. Having
+ several high parts for the same low part is a GNU extension; this rule
+ allows careful users to avoid it.
+
+ (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
+ with the last high-part relocation being at the front of the list.
+ It therefore makes sense to choose the last matching low-part
+ relocation, all other things being equal. It's also easier
+ to code that way. */
void
mips_frob_file (void)
for (l = mips_hi_fixup_list; l != NULL; l = l->next)
{
segment_info_type *seginfo;
- int pass;
+ bfd_boolean matched_lo_p;
+ fixS **hi_pos, **lo_pos, **pos;
assert (reloc_needs_lo_p (l->fixp->fx_r_type));
if (fixup_has_matching_lo_p (l->fixp))
continue;
- /* Look through the fixups for this segment for a matching %lo.
- When we find one, move the %hi just in front of it. We do
- this in two passes. In the first pass, we try to find a
- unique %lo. In the second pass, we permit multiple %hi
- relocs for a single %lo (this is a GNU extension). */
seginfo = seg_info (l->seg);
- for (pass = 0; pass < 2; pass++)
- {
- fixS *f, *prev;
- prev = NULL;
- for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
+ /* Set HI_POS to the position of this relocation in the chain.
+ Set LO_POS to the position of the chosen low-part relocation.
+ MATCHED_LO_P is true on entry to the loop if *POS is a low-part
+ relocation that matches an immediately-preceding high-part
+ relocation. */
+ hi_pos = NULL;
+ lo_pos = NULL;
+ matched_lo_p = FALSE;
+ for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
+ {
+ if (*pos == l->fixp)
+ hi_pos = pos;
+
+ if ((*pos)->fx_r_type == BFD_RELOC_LO16
+ && (*pos)->fx_addsy == l->fixp->fx_addsy
+ && (*pos)->fx_offset >= l->fixp->fx_offset
+ && (lo_pos == NULL
+ || (*pos)->fx_offset < (*lo_pos)->fx_offset
+ || (!matched_lo_p
+ && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
+ lo_pos = pos;
+
+ matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
+ && fixup_has_matching_lo_p (*pos));
+ }
+
+ /* If we found a match, remove the high-part relocation from its
+ current position and insert it before the low-part relocation.
+ Make the offsets match so that fixup_has_matching_lo_p()
+ will return true.
+
+ We don't warn about unmatched high-part relocations since some
+ versions of gcc have been known to emit dead "lui ...%hi(...)"
+ instructions. */
+ if (lo_pos != NULL)
+ {
+ l->fixp->fx_offset = (*lo_pos)->fx_offset;
+ if (l->fixp->fx_next != *lo_pos)
{
- /* Check whether this is a %lo fixup which matches l->fixp. */
- if (f->fx_r_type == BFD_RELOC_LO16
- && f->fx_addsy == l->fixp->fx_addsy
- && f->fx_offset == l->fixp->fx_offset
- && (pass == 1
- || prev == NULL
- || !reloc_needs_lo_p (prev->fx_r_type)
- || !fixup_has_matching_lo_p (prev)))
- {
- fixS **pf;
-
- /* Move l->fixp before f. */
- for (pf = &seginfo->fix_root;
- *pf != l->fixp;
- pf = &(*pf)->fx_next)
- assert (*pf != NULL);
-
- *pf = l->fixp->fx_next;
-
- l->fixp->fx_next = f;
- if (prev == NULL)
- seginfo->fix_root = l->fixp;
- else
- prev->fx_next = l->fixp;
-
- break;
- }
-
- prev = f;
+ *hi_pos = l->fixp->fx_next;
+ l->fixp->fx_next = *lo_pos;
+ *lo_pos = l->fixp;
}
-
- if (f != NULL)
- break;
-
-#if 0 /* GCC code motion plus incomplete dead code elimination
- can leave a %hi without a %lo. */
- if (pass == 1)
- as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
- _("Unmatched %%hi reloc"));
-#endif
}
}
}
-/* When generating embedded PIC code we need to use a special
- relocation to represent the difference of two symbols in the .text
- section (switch tables use a difference of this sort). See
- include/coff/mips.h for details. This macro checks whether this
- fixup requires the special reloc. */
-#define SWITCH_TABLE(fixp) \
- ((fixp)->fx_r_type == BFD_RELOC_32 \
- && OUTPUT_FLAVOR != bfd_target_elf_flavour \
- && (fixp)->fx_addsy != NULL \
- && (fixp)->fx_subsy != NULL \
- && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
- && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
-
-/* When generating embedded PIC code we must keep all PC relative
- relocations, in case the linker has to relax a call. We also need
- to keep relocations for switch table entries.
-
- We may have combined relocations without symbols in the N32/N64 ABI.
+/* We may have combined relocations without symbols in the N32/N64 ABI.
We have to prevent gas from dropping them. */
int
|| fixp->fx_r_type == BFD_RELOC_LO16))
return 1;
- return (mips_pic == EMBEDDED_PIC
- && (fixp->fx_pcrel
- || SWITCH_TABLE (fixp)
- || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
- || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
+ return 0;
}
/* This hook is called before a fix is simplified. We don't really
whole function). */
if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
- && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
- || OUTPUT_FLAVOR == bfd_target_elf_flavour)
- && mips_pic != EMBEDDED_PIC)
+ && ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
+ || OUTPUT_FLAVOR == bfd_target_elf_flavour)
|| bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
&& fixP->fx_addsy)
{
buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
/* We are not done if this is a composite relocation to set up gp. */
- if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
+ assert (! fixP->fx_pcrel);
+ if (fixP->fx_addsy == NULL
&& !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
|| (fixP->fx_r_type == BFD_RELOC_64
&& (previous_fx_r_type == BFD_RELOC_GPREL32
case BFD_RELOC_MIPS_CALL_HI16:
case BFD_RELOC_MIPS_CALL_LO16:
case BFD_RELOC_MIPS16_GPREL:
- if (fixP->fx_pcrel)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid PC relative reloc"));
+ assert (! fixP->fx_pcrel);
/* Nothing needed to do. The value comes from the reloc entry */
break;
*valP = 0;
break;
- case BFD_RELOC_PCREL_HI16_S:
- /* The addend for this is tricky if it is internal, so we just
- do everything here rather than in bfd_install_relocation. */
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
- break;
- if (fixP->fx_addsy
- && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
- {
- /* For an external symbol adjust by the address to make it
- pcrel_offset. We use the address of the RELLO reloc
- which follows this one. */
- *valP += (fixP->fx_next->fx_frag->fr_address
- + fixP->fx_next->fx_where);
- }
- *valP = ((*valP + 0x8000) >> 16) & 0xffff;
- if (target_big_endian)
- buf += 2;
- md_number_to_chars (buf, *valP, 2);
- break;
-
- case BFD_RELOC_PCREL_LO16:
- /* The addend for this is tricky if it is internal, so we just
- do everything here rather than in bfd_install_relocation. */
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
- break;
- if (fixP->fx_addsy
- && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
- *valP += fixP->fx_frag->fr_address + fixP->fx_where;
- if (target_big_endian)
- buf += 2;
- md_number_to_chars (buf, *valP, 2);
- break;
-
case BFD_RELOC_64:
/* This is handled like BFD_RELOC_32, but we output a sign
extended value if we are only 32 bits. */
- if (fixP->fx_done
- || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
+ if (fixP->fx_done)
{
if (8 <= sizeof (valueT))
md_number_to_chars (buf, *valP, 8);
case BFD_RELOC_32:
/* If we are deleting this reloc entry, we must fill in the
value now. This can happen if we have a .word which is not
- resolved when it appears but is later defined. We also need
- to fill in the value if this is an embedded PIC switch table
- entry. */
- if (fixP->fx_done
- || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
+ resolved when it appears but is later defined. */
+ if (fixP->fx_done)
md_number_to_chars (buf, *valP, 4);
break;
break;
case BFD_RELOC_LO16:
+ /* FIXME: Now that embedded-PIC is gone, some of this code/comment
+ may be safe to remove, but if so it's not obvious. */
/* When handling an embedded PIC switch statement, we can wind
up deleting a LO16 reloc. See the 'o' case in mips_ip. */
if (fixP->fx_done)
&& fixP->fx_done
&& fixP->fx_frag->fr_address >= text_section->vma
&& (fixP->fx_frag->fr_address
- < text_section->vma + text_section->_raw_size)
+ < text_section->vma + bfd_get_section_size (text_section))
&& ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
|| (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
|| (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
{
segT seg;
- /* When generating embedded PIC code, we only use the .text, .lit8,
- .sdata and .sbss sections. We change the .data and .rdata
- pseudo-ops to use .sdata. */
- if (mips_pic == EMBEDDED_PIC
- && (sec == 'd' || sec == 'r'))
- sec = 's';
-
#ifdef OBJ_ELF
/* The ELF backend needs to know that we are changing sections, so
that .previous works correctly. We could do something like check
break;
case 'r':
- if (USE_GLOBAL_POINTER_OPT)
- {
- seg = subseg_new (RDATA_SECTION_NAME,
- (subsegT) get_absolute_expression ());
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
- {
- bfd_set_section_flags (stdoutput, seg,
- (SEC_ALLOC
- | SEC_LOAD
- | SEC_READONLY
- | SEC_RELOC
- | SEC_DATA));
- if (strcmp (TARGET_OS, "elf") != 0)
- record_alignment (seg, 4);
- }
- demand_empty_rest_of_line ();
- }
- else
+ seg = subseg_new (RDATA_SECTION_NAME,
+ (subsegT) get_absolute_expression ());
+ if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
{
- as_bad (_("No read only data section in this object file format"));
- demand_empty_rest_of_line ();
- return;
+ bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
+ | SEC_READONLY | SEC_RELOC
+ | SEC_DATA));
+ if (strcmp (TARGET_OS, "elf") != 0)
+ record_alignment (seg, 4);
}
+ demand_empty_rest_of_line ();
break;
case 's':
- if (USE_GLOBAL_POINTER_OPT)
- {
- seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
- {
- bfd_set_section_flags (stdoutput, seg,
- SEC_ALLOC | SEC_LOAD | SEC_RELOC
- | SEC_DATA);
- if (strcmp (TARGET_OS, "elf") != 0)
- record_alignment (seg, 4);
- }
- demand_empty_rest_of_line ();
- break;
- }
- else
+ seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
+ if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
{
- as_bad (_("Global pointers not supported; recompile -G 0"));
- demand_empty_rest_of_line ();
- return;
+ bfd_set_section_flags (stdoutput, seg,
+ SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
+ if (strcmp (TARGET_OS, "elf") != 0)
+ record_alignment (seg, 4);
}
+ demand_empty_rest_of_line ();
+ break;
}
auto_align = 1;
else
as_bad (_(".option pic%d not supported"), i);
- if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
+ if (mips_pic == SVR4_PIC)
{
if (g_switch_seen && g_switch_value != 0)
as_warn (_("-G may not be used with SVR4 PIC code"));
/* Permit the user to change the ISA and architecture on the fly.
Needless to say, misuse can cause serious problems. */
- if (strcmp (name, "mips0") == 0)
+ if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
{
reset = 1;
mips_opts.isa = file_mips_isa;
- }
- else if (strcmp (name, "mips1") == 0)
- mips_opts.isa = ISA_MIPS1;
- else if (strcmp (name, "mips2") == 0)
- mips_opts.isa = ISA_MIPS2;
- else if (strcmp (name, "mips3") == 0)
- mips_opts.isa = ISA_MIPS3;
- else if (strcmp (name, "mips4") == 0)
- mips_opts.isa = ISA_MIPS4;
- else if (strcmp (name, "mips5") == 0)
- mips_opts.isa = ISA_MIPS5;
- else if (strcmp (name, "mips32") == 0)
- mips_opts.isa = ISA_MIPS32;
- else if (strcmp (name, "mips32r2") == 0)
- mips_opts.isa = ISA_MIPS32R2;
- else if (strcmp (name, "mips64") == 0)
- mips_opts.isa = ISA_MIPS64;
- else if (strcmp (name, "mips64r2") == 0)
- mips_opts.isa = ISA_MIPS64R2;
- else if (strcmp (name, "arch=default") == 0)
- {
- reset = 1;
mips_opts.arch = file_mips_arch;
- mips_opts.isa = file_mips_isa;
}
else if (strncmp (name, "arch=", 5) == 0)
{
mips_opts.isa = p->isa;
}
}
+ else if (strncmp (name, "mips", 4) == 0)
+ {
+ const struct mips_cpu_info *p;
+
+ p = mips_parse_cpu("internal use", name);
+ if (!p)
+ as_bad (_("unknown ISA level %s"), name + 4);
+ else
+ {
+ mips_opts.arch = p->cpu;
+ mips_opts.isa = p->isa;
+ }
+ }
else
- as_bad (_("unknown ISA level %s"), name + 4);
+ as_bad (_("unknown ISA or architecture %s"), name);
switch (mips_opts.isa)
{
{
mips_pic = SVR4_PIC;
mips_abicalls = TRUE;
- if (USE_GLOBAL_POINTER_OPT)
- {
- if (g_switch_seen && g_switch_value != 0)
- as_warn (_("-G may not be used with SVR4 PIC code"));
- g_switch_value = 0;
- }
+
+ if (g_switch_seen && g_switch_value != 0)
+ as_warn (_("-G may not be used with SVR4 PIC code"));
+ g_switch_value = 0;
+
bfd_set_gp_size (stdoutput, 0);
demand_empty_rest_of_line ();
}
s_cpload (int ignore ATTRIBUTE_UNUSED)
{
expressionS ex;
- int icnt = 0;
/* If we are not generating SVR4 PIC code, or if this is NewABI code,
.cpload is ignored. */
symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
macro_start ();
- macro_build_lui (NULL, &icnt, &ex, mips_gp_register);
- macro_build (NULL, &icnt, &ex, "addiu", "t,r,j", mips_gp_register,
+ macro_build_lui (&ex, mips_gp_register);
+ macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
mips_gp_register, BFD_RELOC_LO16);
-
- macro_build (NULL, &icnt, NULL, "addu", "d,v,t", mips_gp_register,
+ macro_build (NULL, "addu", "d,v,t", mips_gp_register,
mips_gp_register, tc_get_register (0));
macro_end ();
expressionS ex_off;
expressionS ex_sym;
int reg1;
- int icnt = 0;
char *f;
/* If we are not generating SVR4 PIC code, .cpsetup is ignored.
ex_off.X_op_symbol = NULL;
ex_off.X_add_number = mips_cpreturn_offset;
- macro_build (NULL, &icnt, &ex_off, "sd", "t,o(b)", mips_gp_register,
+ macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
BFD_RELOC_LO16, SP);
}
else
- macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_cpreturn_register,
+ macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
mips_gp_register, 0);
/* Ensure there's room for the next two instructions, so that `f'
doesn't end up with an address in the wrong frag. */
frag_grow (8);
f = frag_more (0);
- macro_build (NULL, &icnt, &ex_sym, "lui", "t,u", mips_gp_register,
- BFD_RELOC_GPREL16);
+ macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16);
fix_new (frag_now, f - frag_now->fr_literal,
8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
fix_new (frag_now, f - frag_now->fr_literal,
4, NULL, 0, 0, BFD_RELOC_HI16_S);
f = frag_more (0);
- macro_build (NULL, &icnt, &ex_sym, "addiu", "t,r,j", mips_gp_register,
+ macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
mips_gp_register, BFD_RELOC_GPREL16);
fix_new (frag_now, f - frag_now->fr_literal,
8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
fix_new (frag_now, f - frag_now->fr_literal,
4, NULL, 0, 0, BFD_RELOC_LO16);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
mips_gp_register, reg1);
macro_end ();
s_cprestore (int ignore ATTRIBUTE_UNUSED)
{
expressionS ex;
- int icnt = 0;
/* If we are not generating SVR4 PIC code, or if this is NewABI code,
.cprestore is ignored. */
ex.X_add_number = mips_cprestore_offset;
macro_start ();
- macro_build_ldst_constoffset (NULL, &icnt, &ex, ADDRESS_STORE_INSN,
- mips_gp_register, SP, HAVE_64BIT_ADDRESSES);
+ macro_build_ldst_constoffset (&ex, ADDRESS_STORE_INSN, mips_gp_register,
+ SP, HAVE_64BIT_ADDRESSES);
macro_end ();
demand_empty_rest_of_line ();
s_cpreturn (int ignore ATTRIBUTE_UNUSED)
{
expressionS ex;
- int icnt = 0;
/* If we are not generating SVR4 PIC code, .cpreturn is ignored.
We also need NewABI support. */
ex.X_op_symbol = NULL;
ex.X_add_number = mips_cpreturn_offset;
- macro_build (NULL, &icnt, &ex, "ld", "t,o(b)", mips_gp_register,
- BFD_RELOC_LO16, SP);
+ macro_build (&ex, "ld", "t,o(b)", mips_gp_register, BFD_RELOC_LO16, SP);
}
else
- macro_build (NULL, &icnt, NULL, "daddu", "d,v,t", mips_gp_register,
+ macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
mips_cpreturn_register, 0);
macro_end ();
static void
s_cpadd (int ignore ATTRIBUTE_UNUSED)
{
- int icnt = 0;
int reg;
/* This is ignored when not generating SVR4 PIC code. */
/* Add $gp to the register named as an argument. */
macro_start ();
reg = tc_get_register (0);
- macro_build (NULL, &icnt, NULL, ADDRESS_ADD_INSN, "d,v,t",
- reg, reg, mips_gp_register);
+ macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", reg, reg, mips_gp_register);
macro_end ();
demand_empty_rest_of_line ();
if (sym == 0)
return 0;
- if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
+ if (g_switch_value > 0)
{
const char *symname;
int change;
#ifdef OBJ_ELF
/* A global or weak symbol is treated as external. */
&& (OUTPUT_FLAVOR != bfd_target_elf_flavour
- || (! S_IS_WEAK (sym)
- && (! S_IS_EXTERNAL (sym)
- || mips_pic == EMBEDDED_PIC)))
+ || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
#endif
);
}
}
/* This is called to see whether a reloc against a defined symbol
- should be converted into a reloc against a section. Don't adjust
- MIPS16 jump relocations, so we don't have to worry about the format
- of the offset in the .o file. Don't adjust relocations against
- mips16 symbols, so that the linker can find them if it needs to set
- up a stub. */
+ should be converted into a reloc against a section. */
int
mips_fix_adjustable (fixS *fixp)
{
+ /* Don't adjust MIPS16 jump relocations, so we don't have to worry
+ about the format of the offset in the .o file. */
if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
return 0;
if (fixp->fx_addsy == NULL)
return 1;
+ /* If symbol SYM is in a mergeable section, relocations of the form
+ SYM + 0 can usually be made section-relative. The mergeable data
+ is then identified by the section offset rather than by the symbol.
+
+ However, if we're generating REL LO16 relocations, the offset is split
+ between the LO16 and parterning high part relocation. The linker will
+ need to recalculate the complete offset in order to correctly identify
+ the merge data.
+
+ The linker has traditionally not looked for the parterning high part
+ relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
+ placed anywhere. Rather than break backwards compatibility by changing
+ this, it seems better not to force the issue, and instead keep the
+ original symbol. This will work with either linker behavior. */
+ if ((fixp->fx_r_type == BFD_RELOC_LO16 || reloc_needs_lo_p (fixp->fx_r_type))
+ && HAVE_IN_PLACE_ADDENDS
+ && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
+ return 0;
+
#ifdef OBJ_ELF
+ /* Don't adjust relocations against mips16 symbols, so that the linker
+ can find them if it needs to set up a stub. */
if (OUTPUT_FLAVOR == bfd_target_elf_flavour
&& S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
&& fixp->fx_subsy == NULL)
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
- if (mips_pic == EMBEDDED_PIC
- && SWITCH_TABLE (fixp))
- {
- /* For a switch table entry we use a special reloc. The addend
- is actually the difference between the reloc address and the
- subtrahend. */
- reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
- if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
- as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
- fixp->fx_r_type = BFD_RELOC_GPREL32;
- }
- else if (fixp->fx_pcrel)
- {
- bfd_vma pcrel_address;
-
- /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high
- high-part relocs is the address of the low-part reloc. */
- if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
- {
- assert (fixp->fx_next != NULL
- && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
- pcrel_address = (fixp->fx_next->fx_where
- + fixp->fx_next->fx_frag->fr_address);
- }
- else
- pcrel_address = reloc->address;
-
- if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
- {
- /* At this point, fx_addnumber is "symbol offset - pcrel_address".
- Relocations want only the symbol offset. */
- reloc->addend = fixp->fx_addnumber + pcrel_address;
- }
- else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16
- || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
- {
- /* We use a special addend for an internal RELLO or RELHI reloc. */
- if (symbol_section_p (fixp->fx_addsy))
- reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy);
- else
- reloc->addend = fixp->fx_addnumber + pcrel_address;
- }
- else
- {
- if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
- /* A gruesome hack which is a result of the gruesome gas reloc
- handling. */
- reloc->addend = pcrel_address;
- else
- reloc->addend = -pcrel_address;
- }
- }
- else
- reloc->addend = fixp->fx_addnumber;
+ assert (! fixp->fx_pcrel);
+ reloc->addend = fixp->fx_addnumber;
/* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
entry to be used in the relocation's section offset. */
reloc->addend = 0;
}
- /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
- fixup_segment converted a non-PC relative reloc into a PC
- relative reloc. In such a case, we need to convert the reloc
- code. */
code = fixp->fx_r_type;
- if (fixp->fx_pcrel)
- {
- switch (code)
- {
- case BFD_RELOC_8:
- code = BFD_RELOC_8_PCREL;
- break;
- case BFD_RELOC_16:
- code = BFD_RELOC_16_PCREL;
- break;
- case BFD_RELOC_32:
- code = BFD_RELOC_32_PCREL;
- break;
- case BFD_RELOC_64:
- code = BFD_RELOC_64_PCREL;
- break;
- case BFD_RELOC_8_PCREL:
- case BFD_RELOC_16_PCREL:
- case BFD_RELOC_32_PCREL:
- case BFD_RELOC_64_PCREL:
- case BFD_RELOC_16_PCREL_S2:
- case BFD_RELOC_PCREL_HI16_S:
- case BFD_RELOC_PCREL_LO16:
- break;
- default:
- as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Cannot make %s relocation PC relative"),
- bfd_get_reloc_code_name (code));
- }
- }
- /* To support a PC relative reloc when generating embedded PIC code
- for ECOFF, we use a Cygnus extension. We check for that here to
- make sure that we don't let such a reloc escape normally. */
+ /* To support a PC relative reloc, we used a Cygnus extension.
+ We check for that here to make sure that we don't let such a
+ reloc escape normally. (FIXME: This was formerly used by
+ embedded-PIC support, but is now used by branch handling in
+ general. That probably should be fixed.) */
if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
|| OUTPUT_FLAVOR == bfd_target_elf_flavour)
- && code == BFD_RELOC_16_PCREL_S2
- && mips_pic != EMBEDDED_PIC)
+ && code == BFD_RELOC_16_PCREL_S2)
reloc->howto = NULL;
else
reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
fprintf (stream, _("\
MIPS options:\n\
--membedded-pic generate embedded position independent code\n\
-EB generate big endian output\n\
-EL generate little endian output\n\
-g, -g2 do not remove unneeded NOPs or swap branches\n\
-mips16 generate mips16 instructions\n\
-no-mips16 do not generate mips16 instructions\n"));
fprintf (stream, _("\
+-mfix-vr4120 work around certain VR4120 errata\n\
-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
-O0 remove unneeded NOPs, do not swap branches\n\
else
return dwarf2_format_32bit;
}
+
+int
+mips_dwarf2_addr_size (void)
+{
+ if (mips_abi == N64_ABI)
+ return 8;
+ else
+ return 4;
+}
projects / deliverable / binutils-gdb.git / blobdiff