/* tc-msp430.c -- Assembler code for the Texas Instruments MSP430
- Copyright (C) 2002-2015 Free Software Foundation, Inc.
+ Copyright (C) 2002-2017 Free Software Foundation, Inc.
Contributed by Dmitry Diky <diwil@mail.ru>
This file is part of GAS, the GNU Assembler.
#include "as.h"
#include <limits.h>
-#define PUSH_1X_WORKAROUND
#include "subsegs.h"
#include "opcode/msp430.h"
#include "safe-ctype.h"
int msp430_enable_relax;
int msp430_enable_polys;
-/* Set linkrelax here to avoid fixups in most sections. */
-int linkrelax = 1;
-
/* GCC uses the some condition codes which we'll
implement as new polymorph instructions.
struct rcodes_s
{
- char * name;
+ const char * name;
int index; /* Corresponding insn_opnumb. */
int sop; /* Opcode if jump length is short. */
long lpos; /* Label position. */
struct hcodes_s
{
- char * name;
+ const char * name;
int index; /* Corresponding insn_opnumb. */
int tlab; /* Number of labels in short mode. */
int op0; /* Opcode for first word of short jump. */
? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16))
/* Generate a 16-bit pc-relative relocation.
- For the 430X we generate a relocation without linkwer range checking.
+ For the 430X we generate a relocation without linker range checking.
For the 430 we generate a relocation without assembler range checking
if we are handling an immediate value or a byte-width instruction. */
#undef CHECK_RELOC_MSP430_PCREL
subseg = now_subseg;
/* Now go to .profiler section. */
- obj_elf_change_section (".profiler", SHT_PROGBITS, 0, 0, 0, 0, 0);
+ obj_elf_change_section (".profiler", SHT_PROGBITS, 0, 0, 0, 0, 0, 0);
/* Save flags. */
emit_expr (& exp, 2);
#define OPTION_MOVE_DATA 'd'
static bfd_boolean move_data = FALSE;
+enum
+{
+ OPTION_SILICON_ERRATA = OPTION_MD_BASE,
+ OPTION_SILICON_ERRATA_WARN,
+};
+
+static unsigned int silicon_errata_fix = 0;
+static unsigned int silicon_errata_warn = 0;
+#define SILICON_ERRATA_CPU4 (1 << 0)
+#define SILICON_ERRATA_CPU8 (1 << 1)
+#define SILICON_ERRATA_CPU11 (1 << 2)
+#define SILICON_ERRATA_CPU12 (1 << 3)
+#define SILICON_ERRATA_CPU13 (1 << 4)
+#define SILICON_ERRATA_CPU19 (1 << 5)
+
static void
msp430_set_arch (int option)
{
- char *str = (char *) alloca (32); /* 32 for good measure. */
+ char str[32]; /* 32 for good measure. */
input_line_pointer = extract_word (input_line_pointer, str, 32);
/* This is a copy of the same data structure found in gcc/config/msp430/msp430.c
Keep these two structures in sync.
- The data in this structure has been extracted from the devices.csv file
- released by TI, updated as of 8 October 2015. */
+ The data in this structure has been extracted from version 1.194 of the
+ devices.csv file released by TI in September 2016. */
struct msp430_mcu_data
{
{ "msp430fg6626",2,8 },
{ "msp430fr2032",2,0 },
{ "msp430fr2033",2,0 },
+ { "msp430fr2110",2,0 },
+ { "msp430fr2111",2,0 },
+ { "msp430fr2310",2,0 },
+ { "msp430fr2311",2,0 },
{ "msp430fr2433",2,8 },
+ { "msp430fr2532",2,8 },
+ { "msp430fr2533",2,8 },
+ { "msp430fr2632",2,8 },
+ { "msp430fr2633",2,8 },
{ "msp430fr2xx_4xxgeneric",2,8 },
{ "msp430fr4131",2,0 },
{ "msp430fr4132",2,0 },
{ "msp430fr5957",2,8 },
{ "msp430fr5958",2,8 },
{ "msp430fr5959",2,8 },
+ { "msp430fr5962",2,8 },
+ { "msp430fr5964",2,8 },
{ "msp430fr5967",2,8 },
{ "msp430fr5968",2,8 },
{ "msp430fr5969",2,8 },
{ "msp430fr5988",2,8 },
{ "msp430fr5989",2,8 },
{ "msp430fr59891",2,8 },
+ { "msp430fr5992",2,8 },
+ { "msp430fr5994",2,8 },
+ { "msp430fr59941",2,8 },
{ "msp430fr5xx_6xxgeneric",2,8 },
{ "msp430fr6820",2,8 },
{ "msp430fr6822",2,8 },
};
int
-md_parse_option (int c, char * arg)
+md_parse_option (int c, const char * arg)
{
switch (c)
{
+ case OPTION_SILICON_ERRATA:
+ case OPTION_SILICON_ERRATA_WARN:
+ {
+ signed int i;
+ const struct
+ {
+ const char * name;
+ unsigned int length;
+ unsigned int bitfield;
+ } erratas[] =
+ {
+ { STRING_COMMA_LEN ("cpu4"), SILICON_ERRATA_CPU4 },
+ { STRING_COMMA_LEN ("cpu8"), SILICON_ERRATA_CPU8 },
+ { STRING_COMMA_LEN ("cpu11"), SILICON_ERRATA_CPU11 },
+ { STRING_COMMA_LEN ("cpu12"), SILICON_ERRATA_CPU12 },
+ { STRING_COMMA_LEN ("cpu13"), SILICON_ERRATA_CPU13 },
+ { STRING_COMMA_LEN ("cpu19"), SILICON_ERRATA_CPU19 },
+ };
+
+ do
+ {
+ for (i = ARRAY_SIZE (erratas); i--;)
+ if (strncasecmp (arg, erratas[i].name, erratas[i].length) == 0)
+ {
+ if (c == OPTION_SILICON_ERRATA)
+ silicon_errata_fix |= erratas[i].bitfield;
+ else
+ silicon_errata_warn |= erratas[i].bitfield;
+ arg += erratas[i].length;
+ break;
+ }
+ if (i < 0)
+ {
+ as_warn (_("Unrecognised CPU errata name starting here: %s"), arg);
+ break;
+ }
+ if (*arg == 0)
+ break;
+ if (*arg != ',')
+ as_warn (_("Expecting comma after CPU errata name, not: %s"), arg);
+ else
+ arg ++;
+ }
+ while (*arg != 0);
+ }
+ return 1;
+
case OPTION_MMCU:
if (arg == NULL)
as_fatal (_("MCU option requires a name\n"));
msp430_section (int arg)
{
char * saved_ilp = input_line_pointer;
- char * name = obj_elf_section_name ();
+ const char * name = obj_elf_section_name ();
msp430_make_init_symbols (name);
struct option md_longopts[] =
{
+ {"msilicon-errata", required_argument, NULL, OPTION_SILICON_ERRATA},
+ {"msilicon-errata-warn", required_argument, NULL, OPTION_SILICON_ERRATA_WARN},
{"mmcu", required_argument, NULL, OPTION_MMCU},
{"mcpu", required_argument, NULL, OPTION_MCPU},
{"mP", no_argument, NULL, OPTION_POLYMORPHS},
_("MSP430 options:\n"
" -mmcu=<msp430-name> - select microcontroller type\n"
" -mcpu={430|430x|430xv2} - select microcontroller architecture\n"));
+ fprintf (stream,
+ _(" -msilicon-errata=<name>[,<name>...] - enable fixups for silicon errata\n"
+ " -msilicon-errata-warn=<name>[,<name>...] - warn when a fixup might be needed\n"
+ " supported errata names: cpu4, cpu8, cpu11, cpu12, cpu13, cpu19\n"));
fprintf (stream,
_(" -mQ - enable relaxation at assembly time. DANGEROUS!\n"
" -mP - enable polymorph instructions\n"));
return from;
}
-char *
+const char *
md_atof (int type, char * litP, int * sizeP)
{
return ieee_md_atof (type, litP, sizeP, FALSE);
bfd_set_arch_mach (stdoutput, TARGET_ARCH,
target_is_430x () ? bfd_mach_msp430x : bfd_mach_msp11);
+
+ /* Set linkrelax here to avoid fixups in most sections. */
+ linkrelax = 1;
}
/* Returns the register number equivalent to the string T.
}
else if (x == 4)
{
-#ifdef PUSH_1X_WORKAROUND
- if (bin == 0x1200)
+ if (bin == 0x1200 && ! target_is_430x ())
{
- /* Remove warning as confusing.
- as_warn (_("Hardware push bug workaround")); */
+ /* CPU4: The shorter form of PUSH #4 is not supported on MSP430. */
+ if (silicon_errata_warn & SILICON_ERRATA_CPU4)
+ as_warn (_("cpu4: not converting PUSH #4 to shorter form"));
+ /* No need to check silicon_errata_fixes - this fix is always implemented. */
}
else
-#endif
{
op->reg = 2;
op->am = 2;
}
else if (x == 8)
{
-#ifdef PUSH_1X_WORKAROUND
- if (bin == 0x1200)
+ if (bin == 0x1200 && ! target_is_430x ())
{
- /* Remove warning as confusing.
- as_warn (_("Hardware push bug workaround")); */
+ /* CPU4: The shorter form of PUSH #8 is not supported on MSP430. */
+ if (silicon_errata_warn & SILICON_ERRATA_CPU4)
+ as_warn (_("cpu4: not converting PUSH #8 to shorter form"));
}
else
-#endif
{
op->reg = 2;
op->am = 3;
else
{
as_bad (_
- ("unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "),
+ ("unknown expression in operand %s. Use #llo(), #lhi(), #hlo() or #hhi()"),
l);
return 1;
}
op->ol = 0;
return 0;
}
+
+ if (op->reg == 1 && (x & 1))
+ {
+ if (silicon_errata_fix & SILICON_ERRATA_CPU8)
+ as_bad (_("CPU8: Stack pointer accessed with an odd offset"));
+ else if (silicon_errata_warn & SILICON_ERRATA_CPU8)
+ as_warn (_("CPU8: Stack pointer accessed with an odd offset"));
+ }
}
else if (op->exp.X_op == O_symbol)
;
if (op->am == 2)
{
- char *__tl = "0";
+ char *__tl = (char *) "0";
op->mode = OP_EXP;
op->am = 1;
return 0;
}
-static bfd_boolean check_for_nop = FALSE;
+#define NOP_CHECK_INTERRUPT (1 << 0)
+#define NOP_CHECK_CPU12 (1 << 1)
+#define NOP_CHECK_CPU19 (1 << 2)
+
+static signed int check_for_nop = 0;
#define is_opcode(NAME) (strcmp (opcode->name, NAME) == 0)
bfd_boolean addr_op;
const char * error_message;
static signed int repeat_count = 0;
+ static bfd_boolean prev_insn_is_nop = FALSE;
bfd_boolean fix_emitted;
- bfd_boolean nop_check_needed = FALSE;
/* Opcode is the one from opcodes table
line contains something like
instruction that does not support it. Look for an alternative extended
instruction that has the same name without the period. Eg: "add.a"
becomes "adda". Although this not an officially supported way of
- specifing instruction aliases other MSP430 assemblers allow it. So we
+ specifying instruction aliases other MSP430 assemblers allow it. So we
support it for compatibility purposes. */
if (addr_op && opcode->fmt >= 0)
{
- char * old_name = opcode->name;
+ const char * old_name = opcode->name;
char real_name[32];
sprintf (real_name, "%sa", old_name);
repeat_count = 0;
}
- if (check_for_nop && is_opcode ("nop"))
- check_for_nop = FALSE;
-
- switch (fmt)
+ if (check_for_nop)
{
- case 0: /* Emulated. */
- switch (opcode->insn_opnumb)
+ if (! is_opcode ("nop"))
{
- case 0:
- if (is_opcode ("eint") || is_opcode ("dint"))
+ bfd_boolean doit = FALSE;
+
+ do
{
- if (check_for_nop)
+ switch (check_for_nop & - check_for_nop)
{
+ case NOP_CHECK_INTERRUPT:
if (warn_interrupt_nops)
{
if (gen_interrupt_nops)
as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
}
+ if (gen_interrupt_nops)
+ /* Emit a NOP between interrupt enable/disable.
+ See 1.3.4.1 of the MSP430x5xx User Guide. */
+ doit = TRUE;
+ break;
+
+ case NOP_CHECK_CPU12:
+ if (silicon_errata_warn & SILICON_ERRATA_CPU12)
+ as_warn (_("CPU12: CMP/BIT with PC destinstion ignores next instruction"));
+
+ if (silicon_errata_fix & SILICON_ERRATA_CPU12)
+ doit = TRUE;
+ break;
+
+ case NOP_CHECK_CPU19:
+ if (silicon_errata_warn & SILICON_ERRATA_CPU19)
+ as_warn (_("CPU19: Instruction setting CPUOFF must be followed by a NOP"));
+
+ if (silicon_errata_fix & SILICON_ERRATA_CPU19)
+ doit = TRUE;
+ break;
+
+ default:
+ as_bad (_("internal error: unknown nop check state"));
+ break;
+ }
+ check_for_nop &= ~ (check_for_nop & - check_for_nop);
+ }
+ while (check_for_nop);
+
+ if (doit)
+ {
+ frag = frag_more (2);
+ bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
+ dwarf2_emit_insn (2);
+ }
+ }
+
+ check_for_nop = 0;
+ }
+
+ switch (fmt)
+ {
+ case 0: /* Emulated. */
+ switch (opcode->insn_opnumb)
+ {
+ case 0:
+ if (is_opcode ("eint"))
+ {
+ if (! prev_insn_is_nop)
+ {
if (gen_interrupt_nops)
{
- /* Emit a NOP between interrupt enable/disable.
- See 1.3.4.1 of the MSP430x5xx User Guide. */
- insn_length += 2;
frag = frag_more (2);
bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
+ dwarf2_emit_insn (2);
+
+ if (warn_interrupt_nops)
+ as_warn (_("inserting a NOP before EINT"));
}
+ else if (warn_interrupt_nops)
+ as_warn (_("a NOP might be needed before the EINT"));
}
-
- nop_check_needed = TRUE;
}
+ else if (is_opcode ("dint"))
+ check_for_nop |= NOP_CHECK_INTERRUPT;
/* Set/clear bits instructions. */
if (extended_op)
bin |= (op1.reg | (op1.am << 7));
- if (is_opcode ("clr") && bin == 0x4302 /* CLR R2*/)
+ /* If the PC is the destination... */
+ if (op1.am == 0 && op1.reg == 0
+ /* ... and the opcode alters the SR. */
+ && !(is_opcode ("bic") || is_opcode ("bis") || is_opcode ("mov")
+ || is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
{
- if (check_for_nop)
- {
- if (warn_interrupt_nops)
- {
- if (gen_interrupt_nops)
- as_warn (_("NOP inserted between two instructions that change interrupt state"));
- else
- as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
- }
-
- if (gen_interrupt_nops)
- {
- /* Emit a NOP between interrupt enable/disable.
- See 1.3.4.1 of the MSP430x5xx User Guide. */
- insn_length += 2;
- frag = frag_more (2);
- bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
- }
- }
-
- nop_check_needed = TRUE;
+ if (silicon_errata_fix & SILICON_ERRATA_CPU11)
+ as_bad (_("CPU11: PC is destinstion of SR altering instruction"));
+ else if (silicon_errata_warn & SILICON_ERRATA_CPU11)
+ as_warn (_("CPU11: PC is destinstion of SR altering instruction"));
}
+
+ /* If the status register is the destination... */
+ if (op1.am == 0 && op1.reg == 2
+ /* ... and the opcode alters the SR. */
+ && (is_opcode ("adc") || is_opcode ("dec") || is_opcode ("decd")
+ || is_opcode ("inc") || is_opcode ("incd") || is_opcode ("inv")
+ || is_opcode ("sbc") || is_opcode ("sxt")
+ || is_opcode ("adcx") || is_opcode ("decx") || is_opcode ("decdx")
+ || is_opcode ("incx") || is_opcode ("incdx") || is_opcode ("invx")
+ || is_opcode ("sbcx")
+ ))
+ {
+ if (silicon_errata_fix & SILICON_ERRATA_CPU13)
+ as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+ else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
+ as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+ }
+
+ if (is_opcode ("clr") && bin == 0x4302 /* CLR R2*/)
+ check_for_nop |= NOP_CHECK_INTERRUPT;
/* Compute the entire instruction length, in bytes. */
op_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2);
break;
}
+ /* If the status register is the destination... */
+ if (op1.am == 0 && op1.reg == 2
+ /* ... and the opcode alters the SR. */
+ && (is_opcode ("rla") || is_opcode ("rlc")
+ || is_opcode ("rlax") || is_opcode ("rlcx")
+ ))
+ {
+ if (silicon_errata_fix & SILICON_ERRATA_CPU13)
+ as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+ else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
+ as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+ }
+
if (extended_op)
{
if (!addr_op)
parse_exp (l1 + 1, &(op1.exp));
if (op1.exp.X_op != O_constant)
{
- as_bad (_("expected constant expression for first argument of %s"),
+ as_bad (_("expected constant expression as first argument of %s"),
opcode->name);
break;
}
parse_exp (l1 + 1, &(op1.exp));
if (op1.exp.X_op != O_constant)
{
- as_bad (_("expected constant expression for first argument of %s"),
+ as_bad (_("expected constant expression as first argument of %s"),
opcode->name);
break;
}
break;
}
- case 7:
- {
- int reg;
-
- /* RRUX: Synthetic unsigned right shift of a register by one bit. */
- if (extended & 0xff)
- {
- as_bad (_("repeat count cannot be used with %s"), opcode->name);
- break;
- }
-
- line = extract_operand (line, l1, sizeof (l1));
- if ((reg = check_reg (l1)) == -1)
- {
- as_bad (_("expected register as argument of %s"),
- opcode->name);
- break;
- }
-
- if (target_is_430xv2 () && reg == 0)
- {
- as_bad (_("%s: attempt to rotate the PC register"), opcode->name);
- break;
- }
-
- if (byte_op)
- {
- /* Tricky - there is no single instruction that will do this.
- Encode as: RRA.B rN { BIC.B #0x80, rN */
- op_length = 6;
- frag = frag_more (op_length);
- where = frag - frag_now->fr_literal;
- bin = 0x1140 | reg;
- bfd_putl16 ((bfd_vma) bin, frag);
- dwarf2_emit_insn (2);
- bin = 0xc070 | reg;
- bfd_putl16 ((bfd_vma) bin, frag + 2);
- bin = 0x0080;
- bfd_putl16 ((bfd_vma) bin, frag + 4);
- dwarf2_emit_insn (4);
- }
- else
- {
- /* Encode as RRUM[.A] rN. */
- bin = opcode->bin_opcode;
- if (! addr_op)
- bin |= 0x10;
- bin |= reg;
- op_length = 2;
- frag = frag_more (op_length);
- where = frag - frag_now->fr_literal;
- bfd_putl16 ((bfd_vma) bin, frag);
- dwarf2_emit_insn (op_length);
- }
- break;
- }
-
case 8:
{
bfd_boolean need_reloc = FALSE;
break;
default:
- as_bad (_("Illegal emulated instruction "));
+ as_bad (_("Illegal emulated instruction"));
break;
}
break;
bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
+ /* If the PC is the destination... */
+ if (op2.am == 0 && op2.reg == 0
+ /* ... and the opcode alters the SR. */
+ && !(is_opcode ("bic") || is_opcode ("bis") || is_opcode ("mov")
+ || is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
+ {
+ if (silicon_errata_fix & SILICON_ERRATA_CPU11)
+ as_bad (_("CPU11: PC is destinstion of SR altering instruction"));
+ else if (silicon_errata_warn & SILICON_ERRATA_CPU11)
+ as_warn (_("CPU11: PC is destinstion of SR altering instruction"));
+ }
+
+ /* If the status register is the destination... */
+ if (op2.am == 0 && op2.reg == 2
+ /* ... and the opcode alters the SR. */
+ && (is_opcode ("add") || is_opcode ("addc") || is_opcode ("and")
+ || is_opcode ("dadd") || is_opcode ("sub") || is_opcode ("subc")
+ || is_opcode ("xor")
+ || is_opcode ("addx") || is_opcode ("addcx") || is_opcode ("andx")
+ || is_opcode ("daddx") || is_opcode ("subx") || is_opcode ("subcx")
+ || is_opcode ("xorx")
+ ))
+ {
+ if (silicon_errata_fix & SILICON_ERRATA_CPU13)
+ as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+ else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
+ as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+ }
+
if ( (is_opcode ("bic") && bin == 0xc232)
|| (is_opcode ("bis") && bin == 0xd232)
|| (is_opcode ("mov") && op2.mode == OP_REG && op2.reg == 2))
{
- if (check_for_nop)
- {
- if (warn_interrupt_nops)
- {
- if (gen_interrupt_nops)
- as_warn (_("NOP inserted between two instructions that change interrupt state"));
- else
- as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
- }
-
- if (gen_interrupt_nops)
- {
- /* Emit a NOP between interrupt enable/disable.
- See 1.3.4.1 of the MSP430x5xx User Guide. */
- insn_length += 2;
- frag = frag_more (2);
- bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
- }
- }
-
- nop_check_needed = TRUE;
+ /* Avoid false checks when a constant value is being put into the SR. */
+ if (op1.mode == OP_EXP
+ && op1.exp.X_op == O_constant
+ && (op1.exp.X_add_number & 0x8) != 0x8)
+ ;
+ else
+ check_for_nop |= NOP_CHECK_INTERRUPT;
}
+ if (((is_opcode ("bis") && bin == 0xd032)
+ || (is_opcode ("mov") && bin == 0x4032)
+ || (is_opcode ("xor") && bin == 0xe032))
+ && op1.mode == OP_EXP
+ && op1.exp.X_op == O_constant
+ && (op1.exp.X_add_number & 0x10) == 0x10)
+ check_for_nop |= NOP_CHECK_CPU19;
+
/* Compute the entire length of the instruction in bytes. */
op_length = (extended_op ? 2 : 0) /* The extension word. */
+ 2 /* The opcode */
}
dwarf2_emit_insn (insn_length);
+
+ /* If the PC is the destination... */
+ if (op2.am == 0 && op2.reg == 0
+ /* ... but the opcode does not alter the destination. */
+ && (is_opcode ("cmp") || is_opcode ("bit") || is_opcode ("cmpx")))
+ check_for_nop |= NOP_CHECK_CPU12;
break;
case 2: /* Single-operand mostly instr. */
break;
}
+ /* If the status register is the destination... */
+ if (op1.am == 0 && op1.reg == 2
+ /* ... and the opcode alters the SR. */
+ && (is_opcode ("rra") || is_opcode ("rrc") || is_opcode ("sxt")))
+ {
+ if (silicon_errata_fix & SILICON_ERRATA_CPU13)
+ as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+ else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
+ as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+ }
+
insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2);
frag = frag_more (insn_length);
where = frag - frag_now->fr_literal;
else if (! addr_op)
extended |= BYTE_OPERATION;
+ if (is_opcode ("rrux"))
+ extended |= IGNORE_CARRY_BIT;
+
if (op1.ol != 0 && ((extended & 0xf) != 0))
{
as_bad (_("repeat instruction used with non-register mode instruction"));
if (x > 512 || x < -511)
{
- as_bad (_("Wrong displacement %d"), x << 1);
+ as_bad (_("Wrong displacement %d"), x << 1);
break;
}
as_bad (_("Illegal instruction or not implemented opcode."));
}
+ if (is_opcode ("nop"))
+ prev_insn_is_nop = TRUE;
+ else
+ prev_insn_is_nop = FALSE;
+
input_line_pointer = line;
- check_for_nop = nop_check_needed;
return 0;
}
if (!cmd[0])
{
- as_bad (_("can't find opcode "));
+ as_bad (_("can't find opcode"));
return;
}
{
int align = bfd_get_section_alignment (stdoutput, seg);
- return ((addr + (1 << align) - 1) & (-1 << align));
+ return ((addr + (1 << align) - 1) & -(1 << align));
}
/* If you define this macro, it should return the offset between the
return fixp->fx_frag->fr_address + fixp->fx_where;
}
-/* Replaces standard TC_FORCE_RELOCATION_LOCAL.
+/* Addition to the standard TC_FORCE_RELOCATION_LOCAL.
Now it handles the situation when relocations
have to be passed to linker. */
int
&& !msp430_enable_relax)
return 1;
- return (!fixp->fx_pcrel
- || generic_force_reloc (fixp));
+ return 0;
}
static arelent * relocs[MAX_RELOC_EXPANSION + 1];
arelent *reloc;
- reloc = xmalloc (sizeof (arelent));
+ reloc = XNEW (arelent);
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
because there can be multiple incarnations of the same label, with
exactly the same name, in any given section and the linker will have
no way to identify the correct one. Instead we just have to hope
- that no relaxtion will occur between the local label and the other
+ that no relaxation will occur between the local label and the other
symbol in the expression.
Similarly we have to compute differences between symbols in the .eh_frame
&& ! S_IS_GAS_LOCAL (fixp->fx_addsy)
&& ! S_IS_GAS_LOCAL (fixp->fx_subsy))
{
- arelent * reloc2 = xmalloc (sizeof * reloc);
+ arelent * reloc2 = XNEW (arelent);
relocs[0] = reloc2;
relocs[1] = reloc;
reloc2->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
else
{
- reloc2->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+ reloc2->sym_ptr_ptr = XNEW (asymbol *);
*reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy);
}
}
else
{
- reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+ reloc->sym_ptr_ptr = XNEW (asymbol *);
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
}
return & no_relocs;
}
#endif
- reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+ reloc->sym_ptr_ptr = XNEW (asymbol *);
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
reloc->addend = fixp->fx_offset;
}
else if (fragP->fr_symbol)
{
- /* Its got a segment, but its not ours. Even if fr_symbol is in
+ /* It's got a segment, but it's not ours. Even if fr_symbol is in
an absolute segment, we don't know a displacement until we link
object files. So it will always be long. This also applies to
labels in a subsegment of current. Liker may relax it to short
break;
default:
- as_fatal (_("internal inconsistency problem in %s: %lx"),
+ as_fatal (_("internal inconsistency problem in %s: %lx"),
__FUNCTION__, (long) fragP->fr_subtype);
break;
}
void
msp430_md_end (void)
{
- if (check_for_nop == TRUE && warn_interrupt_nops)
- as_warn ("assembly finished with the last instruction changing interrupt state - a NOP might be needed");
+ if (check_for_nop)
+ as_warn ("assembly finished without a possibly needed NOP instruction");
bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_ISA,
target_is_430x () ? 2 : 1);
projects / deliverable / binutils-gdb.git / blobdiff