/* tc-msp430.c -- Assembler code for the Texas Instruments MSP430
- Copyright (C) 2002-2015 Free Software Foundation, Inc.
+ Copyright (C) 2002-2017 Free Software Foundation, Inc.
Contributed by Dmitry Diky <diwil@mail.ru>
This file is part of GAS, the GNU Assembler.
int msp430_enable_relax;
int msp430_enable_polys;
-/* Set linkrelax here to avoid fixups in most sections. */
-int linkrelax = 1;
-
/* GCC uses the some condition codes which we'll
implement as new polymorph instructions.
struct rcodes_s
{
- char * name;
+ const char * name;
int index; /* Corresponding insn_opnumb. */
int sop; /* Opcode if jump length is short. */
long lpos; /* Label position. */
struct hcodes_s
{
- char * name;
+ const char * name;
int index; /* Corresponding insn_opnumb. */
int tlab; /* Number of labels in short mode. */
int op0; /* Opcode for first word of short jump. */
? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16))
/* Generate a 16-bit pc-relative relocation.
- For the 430X we generate a relocation without linkwer range checking.
+ For the 430X we generate a relocation without linker range checking.
For the 430 we generate a relocation without assembler range checking
if we are handling an immediate value or a byte-width instruction. */
#undef CHECK_RELOC_MSP430_PCREL
expression (op);
if (op->X_op == O_absent)
as_bad (_("missing operand"));
+ /* Our caller is likely to check that the entire expression was parsed.
+ If we have found a hex constant with an 'h' suffix, ilp will be left
+ pointing at the 'h', so skip it here. */
+ if (input_line_pointer != NULL
+ && op->X_op == O_constant
+ && (*input_line_pointer == 'h' || *input_line_pointer == 'H'))
+ ++ input_line_pointer;
return input_line_pointer;
}
subseg = now_subseg;
/* Now go to .profiler section. */
- obj_elf_change_section (".profiler", SHT_PROGBITS, 0, 0, 0, 0, 0);
+ obj_elf_change_section (".profiler", SHT_PROGBITS, 0, 0, 0, 0, 0, 0);
/* Save flags. */
emit_expr (& exp, 2);
/* Now get profiling info. */
halt = extract_operand (input_line_pointer, str, 1024);
/* Process like ".word xxx" directive. */
- parse_exp (str, & exp);
+ (void) parse_exp (str, & exp);
emit_expr (& exp, 2);
input_line_pointer = halt;
}
#define OPTION_MCPU 'c'
#define OPTION_MOVE_DATA 'd'
static bfd_boolean move_data = FALSE;
+#define OPTION_DATA_REGION 'r'
+static bfd_boolean upper_data_region_in_use = FALSE;
enum
{
OPTION_SILICON_ERRATA = OPTION_MD_BASE,
OPTION_SILICON_ERRATA_WARN,
-} option_numbers;
+};
static unsigned int silicon_errata_fix = 0;
static unsigned int silicon_errata_warn = 0;
#define SILICON_ERRATA_CPU12 (1 << 3)
#define SILICON_ERRATA_CPU13 (1 << 4)
#define SILICON_ERRATA_CPU19 (1 << 5)
-#define SILICON_ERRATA_CPU42 (1 << 6)
-#define SILICON_ERRATA_CPU42_PLUS (1 << 7)
static void
msp430_set_arch (int option)
{
- char *str = (char *) alloca (32); /* 32 for good measure. */
+ char str[32]; /* 32 for good measure. */
input_line_pointer = extract_word (input_line_pointer, str, 32);
/* This is a copy of the same data structure found in gcc/config/msp430/msp430.c
Keep these two structures in sync.
- The data in this structure has been extracted from the devices.csv file
- released by TI, updated as of 8 October 2015. */
+ The data in this structure has been extracted from version 1.194 of the
+ devices.csv file released by TI in September 2016. */
struct msp430_mcu_data
{
{ "msp430fg6626",2,8 },
{ "msp430fr2032",2,0 },
{ "msp430fr2033",2,0 },
+ { "msp430fr2110",2,0 },
+ { "msp430fr2111",2,0 },
+ { "msp430fr2310",2,0 },
+ { "msp430fr2311",2,0 },
{ "msp430fr2433",2,8 },
+ { "msp430fr2532",2,8 },
+ { "msp430fr2533",2,8 },
+ { "msp430fr2632",2,8 },
+ { "msp430fr2633",2,8 },
{ "msp430fr2xx_4xxgeneric",2,8 },
{ "msp430fr4131",2,0 },
{ "msp430fr4132",2,0 },
{ "msp430fr5957",2,8 },
{ "msp430fr5958",2,8 },
{ "msp430fr5959",2,8 },
+ { "msp430fr5962",2,8 },
+ { "msp430fr5964",2,8 },
{ "msp430fr5967",2,8 },
{ "msp430fr5968",2,8 },
{ "msp430fr5969",2,8 },
{ "msp430fr5988",2,8 },
{ "msp430fr5989",2,8 },
{ "msp430fr59891",2,8 },
+ { "msp430fr5992",2,8 },
+ { "msp430fr5994",2,8 },
+ { "msp430fr59941",2,8 },
{ "msp430fr5xx_6xxgeneric",2,8 },
{ "msp430fr6820",2,8 },
{ "msp430fr6822",2,8 },
};
int
-md_parse_option (int c, char * arg)
+md_parse_option (int c, const char * arg)
{
switch (c)
{
signed int i;
const struct
{
- char * name;
+ const char * name;
unsigned int length;
unsigned int bitfield;
} erratas[] =
{ STRING_COMMA_LEN ("cpu12"), SILICON_ERRATA_CPU12 },
{ STRING_COMMA_LEN ("cpu13"), SILICON_ERRATA_CPU13 },
{ STRING_COMMA_LEN ("cpu19"), SILICON_ERRATA_CPU19 },
- { STRING_COMMA_LEN ("cpu42"), SILICON_ERRATA_CPU42 },
- { STRING_COMMA_LEN ("cpu42+"), SILICON_ERRATA_CPU42_PLUS },
};
do
case OPTION_MOVE_DATA:
move_data = TRUE;
return 1;
+
+ case OPTION_DATA_REGION:
+ if (strcmp (arg, "upper") == 0
+ || strcmp (arg, "either") == 0)
+ upper_data_region_in_use = TRUE;
+ return 1;
}
return 0;
/* Note - data assigned to the .either.data section may end up being
placed in the .upper.data section if the .lower.data section is
- full. Hence the need to define the crt0 symbol. */
+ full. Hence the need to define the crt0 symbol.
+ The linker may create upper or either data sections, even when none exist
+ at the moment, so use the value of the data-region flag to determine if
+ the symbol is needed. */
if (strncmp (name, ".either.data", 12) == 0
- || strncmp (name, ".upper.data", 11) == 0)
+ || strncmp (name, ".upper.data", 11) == 0
+ || upper_data_region_in_use)
(void) symbol_find_or_make ("__crt0_move_highdata");
/* See note about .either.data above. */
if (strncmp (name, ".upper.bss", 10) == 0
- || strncmp (name, ".either.bss", 11) == 0)
+ || strncmp (name, ".either.bss", 11) == 0
+ || upper_data_region_in_use)
(void) symbol_find_or_make ("__crt0_init_highbss");
}
msp430_section (int arg)
{
char * saved_ilp = input_line_pointer;
- char * name = obj_elf_section_name ();
+ const char * name = obj_elf_section_name ();
msp430_make_init_symbols (name);
{"mY", no_argument, NULL, OPTION_NO_WARN_INTR_NOPS},
{"my", no_argument, NULL, OPTION_WARN_INTR_NOPS},
{"md", no_argument, NULL, OPTION_MOVE_DATA},
+ {"mdata-region", required_argument, NULL, OPTION_DATA_REGION},
{NULL, no_argument, NULL, 0}
};
fprintf (stream,
_(" -msilicon-errata=<name>[,<name>...] - enable fixups for silicon errata\n"
" -msilicon-errata-warn=<name>[,<name>...] - warn when a fixup might be needed\n"
- " supported errata names: cpu4, cpu8, cpu11, cpu12, cpu13, cpu19, cpu42, cpu42+\n"));
+ " supported errata names: cpu4, cpu8, cpu11, cpu12, cpu13, cpu19\n"));
fprintf (stream,
_(" -mQ - enable relaxation at assembly time. DANGEROUS!\n"
" -mP - enable polymorph instructions\n"));
_(" -my - warn about missing NOPs after changing interrupts (default)\n"));
fprintf (stream,
_(" -md - Force copying of data from ROM to RAM at startup\n"));
+ fprintf (stream,
+ _(" -mdata-region={none|lower|upper|either} - select region data will be\n"
+ " placed in.\n"));
}
symbolS *
return from;
}
-char *
+const char *
md_atof (int type, char * litP, int * sizeP)
{
return ieee_md_atof (type, litP, sizeP, FALSE);
bfd_set_arch_mach (stdoutput, TARGET_ARCH,
target_is_430x () ? bfd_mach_msp430x : bfd_mach_msp11);
+
+ /* Set linkrelax here to avoid fixups in most sections. */
+ linkrelax = 1;
}
/* Returns the register number equivalent to the string T.
bfd_boolean allow_20bit_values,
bfd_boolean constants_allowed)
{
+ char * end;
char *__tl = l;
/* Check if an immediate #VALUE. The hash sign should be only at the beginning! */
op->mode = OP_EXP;
op->vshift = vshift;
- parse_exp (__tl, &(op->exp));
+ end = parse_exp (__tl, &(op->exp));
+ if (end != NULL && *end != 0 && *end != ')' )
+ {
+ as_bad (_("extra characters '%s' at end of immediate expression '%s'"), end, l);
+ return 1;
+ }
if (op->exp.X_op == O_constant)
{
int x = op->exp.X_add_number;
else
{
as_bad (_
- ("unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "),
+ ("unknown expression in operand %s. Use #llo(), #lhi(), #hlo() or #hhi()"),
l);
return 1;
}
op->am = 1; /* mode As == 01 bin. */
op->ol = 1; /* Immediate value followed by instruction. */
__tl = h + 1;
- parse_exp (__tl, &(op->exp));
+ end = parse_exp (__tl, &(op->exp));
+ if (end != NULL && *end != 0)
+ {
+ as_bad (_("extra characters '%s' at the end of absolute operand '%s'"), end, l);
+ return 1;
+ }
op->mode = OP_EXP;
op->vshift = 0;
if (op->exp.X_op == O_constant)
*h = 0;
op->mode = OP_EXP;
op->vshift = 0;
- parse_exp (__tl, &(op->exp));
+ end = parse_exp (__tl, &(op->exp));
+ if (end != NULL && *end != 0)
+ {
+ as_bad (_("extra characters '%s' at end of operand '%s'"), end, l);
+ return 1;
+ }
if (op->exp.X_op == O_constant)
{
int x = op->exp.X_add_number;
}
/* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'. */
- do
+ op->mode = OP_EXP;
+ op->reg = 0; /* PC relative... be careful. */
+ /* An expression starting with a minus sign is a constant, not an address. */
+ op->am = (*l == '-' ? 3 : 1);
+ op->ol = 1;
+ op->vshift = 0;
+ __tl = l;
+ end = parse_exp (__tl, &(op->exp));
+ if (end != NULL && * end != 0)
{
- op->mode = OP_EXP;
- op->reg = 0; /* PC relative... be careful. */
- /* An expression starting with a minus sign is a constant, not an address. */
- op->am = (*l == '-' ? 3 : 1);
- op->ol = 1;
- op->vshift = 0;
- __tl = l;
- parse_exp (__tl, &(op->exp));
- return 0;
+ as_bad (_("extra characters '%s' at end of operand '%s'"), end, l);
+ return 1;
}
- while (0);
-
- /* Unreachable. */
- as_bad (_("unknown addressing mode for operand %s"), l);
- return 1;
+ return 0;
}
if (op->am == 2)
{
- char *__tl = "0";
+ char *__tl = (char *) "0";
op->mode = OP_EXP;
op->am = 1;
op->ol = 1;
op->vshift = 0;
- parse_exp (__tl, &(op->exp));
+ (void) parse_exp (__tl, &(op->exp));
if (op->exp.X_op != O_constant || op->exp.X_add_number != 0)
{
int insn_length = 0;
char l1[MAX_OP_LEN], l2[MAX_OP_LEN];
char *frag;
+ char *end;
int where;
struct msp430_operand_s op1, op2;
int res = 0;
bfd_boolean addr_op;
const char * error_message;
static signed int repeat_count = 0;
+ static bfd_boolean prev_insn_is_nop = FALSE;
bfd_boolean fix_emitted;
/* Opcode is the one from opcodes table
instruction that does not support it. Look for an alternative extended
instruction that has the same name without the period. Eg: "add.a"
becomes "adda". Although this not an officially supported way of
- specifing instruction aliases other MSP430 assemblers allow it. So we
+ specifying instruction aliases other MSP430 assemblers allow it. So we
support it for compatibility purposes. */
if (addr_op && opcode->fmt >= 0)
{
- char * old_name = opcode->name;
+ const char * old_name = opcode->name;
char real_name[32];
sprintf (real_name, "%sa", old_name);
&& opcode->insn_opnumb
&& (!*line || *line == '\n'))
{
- as_bad (_("instruction %s requires %d operand(s)"),
+ as_bad (ngettext ("instruction %s requires %d operand",
+ "instruction %s requires %d operands",
+ opcode->insn_opnumb),
opcode->name, opcode->insn_opnumb);
return 0;
}
switch (check_for_nop & - check_for_nop)
{
case NOP_CHECK_INTERRUPT:
- if (warn_interrupt_nops
- || silicon_errata_warn & SILICON_ERRATA_CPU42
- || silicon_errata_warn & SILICON_ERRATA_CPU42_PLUS)
+ if (warn_interrupt_nops)
{
if (gen_interrupt_nops)
as_warn (_("NOP inserted between two instructions that change interrupt state"));
as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
}
- if (gen_interrupt_nops
- || silicon_errata_fix & SILICON_ERRATA_CPU42_PLUS)
+ if (gen_interrupt_nops)
/* Emit a NOP between interrupt enable/disable.
See 1.3.4.1 of the MSP430x5xx User Guide. */
doit = TRUE;
case NOP_CHECK_CPU12:
if (silicon_errata_warn & SILICON_ERRATA_CPU12)
- as_warn (_("CPU12: CMP/BIT with PC destinstion ignores next instruction"));
+ as_warn (_("CPU12: CMP/BIT with PC destination ignores next instruction"));
if (silicon_errata_fix & SILICON_ERRATA_CPU12)
doit = TRUE;
switch (opcode->insn_opnumb)
{
case 0:
- if (is_opcode ("eint") || is_opcode ("dint"))
+ if (is_opcode ("eint"))
+ {
+ if (! prev_insn_is_nop)
+ {
+ if (gen_interrupt_nops)
+ {
+ frag = frag_more (2);
+ bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
+ dwarf2_emit_insn (2);
+
+ if (warn_interrupt_nops)
+ as_warn (_("inserting a NOP before EINT"));
+ }
+ else if (warn_interrupt_nops)
+ as_warn (_("a NOP might be needed before the EINT"));
+ }
+ }
+ else if (is_opcode ("dint"))
check_for_nop |= NOP_CHECK_INTERRUPT;
/* Set/clear bits instructions. */
|| is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
{
if (silicon_errata_fix & SILICON_ERRATA_CPU11)
- as_bad (_("CPU11: PC is destinstion of SR altering instruction"));
+ as_bad (_("CPU11: PC is destination of SR altering instruction"));
else if (silicon_errata_warn & SILICON_ERRATA_CPU11)
- as_warn (_("CPU11: PC is destinstion of SR altering instruction"));
+ as_warn (_("CPU11: PC is destination of SR altering instruction"));
}
/* If the status register is the destination... */
))
{
if (silicon_errata_fix & SILICON_ERRATA_CPU13)
- as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_bad (_("CPU13: SR is destination of SR altering instruction"));
else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
- as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_warn (_("CPU13: SR is destination of SR altering instruction"));
}
if (is_opcode ("clr") && bin == 0x4302 /* CLR R2*/)
))
{
if (silicon_errata_fix & SILICON_ERRATA_CPU13)
- as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_bad (_("CPU13: SR is destination of SR altering instruction"));
else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
- as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_warn (_("CPU13: SR is destination of SR altering instruction"));
}
if (extended_op)
as_bad (_("expected #n as first argument of %s"), opcode->name);
break;
}
- parse_exp (l1 + 1, &(op1.exp));
+ end = parse_exp (l1 + 1, &(op1.exp));
+ if (end != NULL && *end != 0)
+ {
+ as_bad (_("extra characters '%s' at end of constant expression '%s'"), end, l1);
+ break;
+ }
if (op1.exp.X_op != O_constant)
{
- as_bad (_("expected constant expression for first argument of %s"),
+ as_bad (_("expected constant expression as first argument of %s"),
opcode->name);
break;
}
as_bad (_("expected #n as first argument of %s"), opcode->name);
break;
}
- parse_exp (l1 + 1, &(op1.exp));
+ end = parse_exp (l1 + 1, &(op1.exp));
+ if (end != NULL && *end != 0)
+ {
+ as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
+ break;
+ }
if (op1.exp.X_op != O_constant)
{
- as_bad (_("expected constant expression for first argument of %s"),
+ as_bad (_("expected constant expression as first argument of %s"),
opcode->name);
break;
}
break;
}
- case 7:
- {
- int reg;
-
- /* RRUX: Synthetic unsigned right shift of a register by one bit. */
- if (extended & 0xff)
- {
- as_bad (_("repeat count cannot be used with %s"), opcode->name);
- break;
- }
-
- line = extract_operand (line, l1, sizeof (l1));
- if ((reg = check_reg (l1)) == -1)
- {
- as_bad (_("expected register as argument of %s"),
- opcode->name);
- break;
- }
-
- if (target_is_430xv2 () && reg == 0)
- {
- as_bad (_("%s: attempt to rotate the PC register"), opcode->name);
- break;
- }
-
- if (byte_op)
- {
- /* Tricky - there is no single instruction that will do this.
- Encode as: RRA.B rN { BIC.B #0x80, rN */
- op_length = 6;
- frag = frag_more (op_length);
- where = frag - frag_now->fr_literal;
- bin = 0x1140 | reg;
- bfd_putl16 ((bfd_vma) bin, frag);
- dwarf2_emit_insn (2);
- bin = 0xc070 | reg;
- bfd_putl16 ((bfd_vma) bin, frag + 2);
- bin = 0x0080;
- bfd_putl16 ((bfd_vma) bin, frag + 4);
- dwarf2_emit_insn (4);
- }
- else
- {
- /* Encode as RRUM[.A] rN. */
- bin = opcode->bin_opcode;
- if (! addr_op)
- bin |= 0x10;
- bin |= reg;
- op_length = 2;
- frag = frag_more (op_length);
- where = frag - frag_now->fr_literal;
- bfd_putl16 ((bfd_vma) bin, frag);
- dwarf2_emit_insn (op_length);
- }
- break;
- }
-
case 8:
{
bfd_boolean need_reloc = FALSE;
if (*l1 == '#')
{
- parse_exp (l1 + 1, &(op1.exp));
+ end = parse_exp (l1 + 1, &(op1.exp));
+ if (end != NULL && *end != 0)
+ {
+ as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
+ break;
+ }
if (op1.exp.X_op == O_constant)
{
/* The RPT instruction only accepted immediates and registers. */
if (*l1 == '#')
{
- parse_exp (l1 + 1, &(op1.exp));
+ end = parse_exp (l1 + 1, &(op1.exp));
+ if (end != NULL && *end != 0)
+ {
+ as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
+ break;
+ }
if (op1.exp.X_op != O_constant)
{
as_bad (_("expected constant value as argument to RPT"));
break;
default:
- as_bad (_("Illegal emulated instruction "));
+ as_bad (_("Illegal emulated instruction"));
break;
}
break;
|| is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
{
if (silicon_errata_fix & SILICON_ERRATA_CPU11)
- as_bad (_("CPU11: PC is destinstion of SR altering instruction"));
+ as_bad (_("CPU11: PC is destination of SR altering instruction"));
else if (silicon_errata_warn & SILICON_ERRATA_CPU11)
- as_warn (_("CPU11: PC is destinstion of SR altering instruction"));
+ as_warn (_("CPU11: PC is destination of SR altering instruction"));
}
/* If the status register is the destination... */
))
{
if (silicon_errata_fix & SILICON_ERRATA_CPU13)
- as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_bad (_("CPU13: SR is destination of SR altering instruction"));
else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
- as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_warn (_("CPU13: SR is destination of SR altering instruction"));
}
if ( (is_opcode ("bic") && bin == 0xc232)
&& (is_opcode ("rra") || is_opcode ("rrc") || is_opcode ("sxt")))
{
if (silicon_errata_fix & SILICON_ERRATA_CPU13)
- as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_bad (_("CPU13: SR is destination of SR altering instruction"));
else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
- as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+ as_warn (_("CPU13: SR is destination of SR altering instruction"));
}
insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2);
else if (! addr_op)
extended |= BYTE_OPERATION;
+ if (is_opcode ("rrux"))
+ extended |= IGNORE_CARRY_BIT;
+
if (op1.ol != 0 && ((extended & 0xf) != 0))
{
as_bad (_("repeat instruction used with non-register mode instruction"));
if (*m == '$')
m++;
- parse_exp (m, &exp);
+ end = parse_exp (m, &exp);
+ if (end != NULL && *end != 0)
+ {
+ as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
+ break;
+ }
/* In order to handle something like:
if (x > 512 || x < -511)
{
- as_bad (_("Wrong displacement %d"), x << 1);
+ as_bad (_("Wrong displacement %d"), x << 1);
break;
}
if (*m == '#' || *m == '$')
m++;
- parse_exp (m, & exp);
+ end = parse_exp (m, & exp);
+ if (end != NULL && *end != 0)
+ {
+ as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
+ break;
+ }
if (exp.X_op == O_symbol)
{
/* Relaxation required. */
if (*m == '#' || *m == '$')
m++;
- parse_exp (m, & exp);
+ end = parse_exp (m, & exp);
+ if (end != NULL && *end != 0)
+ {
+ as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
+ break;
+ }
if (exp.X_op == O_symbol)
{
/* Relaxation required. */
as_bad (_("Illegal instruction or not implemented opcode."));
}
+ if (is_opcode ("nop"))
+ prev_insn_is_nop = TRUE;
+ else
+ prev_insn_is_nop = FALSE;
+
input_line_pointer = line;
return 0;
}
if (!cmd[0])
{
- as_bad (_("can't find opcode "));
+ as_bad (_("can't find opcode"));
return;
}
return fixp->fx_frag->fr_address + fixp->fx_where;
}
-/* Replaces standard TC_FORCE_RELOCATION_LOCAL.
+/* Addition to the standard TC_FORCE_RELOCATION_LOCAL.
Now it handles the situation when relocations
have to be passed to linker. */
int
&& !msp430_enable_relax)
return 1;
- return (!fixp->fx_pcrel
- || generic_force_reloc (fixp));
+ return 0;
}
static arelent * relocs[MAX_RELOC_EXPANSION + 1];
arelent *reloc;
- reloc = xmalloc (sizeof (arelent));
+ reloc = XNEW (arelent);
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
because there can be multiple incarnations of the same label, with
exactly the same name, in any given section and the linker will have
no way to identify the correct one. Instead we just have to hope
- that no relaxtion will occur between the local label and the other
+ that no relaxation will occur between the local label and the other
symbol in the expression.
Similarly we have to compute differences between symbols in the .eh_frame
&& ! S_IS_GAS_LOCAL (fixp->fx_addsy)
&& ! S_IS_GAS_LOCAL (fixp->fx_subsy))
{
- arelent * reloc2 = xmalloc (sizeof * reloc);
+ arelent * reloc2 = XNEW (arelent);
relocs[0] = reloc2;
relocs[1] = reloc;
reloc2->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
else
{
- reloc2->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+ reloc2->sym_ptr_ptr = XNEW (asymbol *);
*reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy);
}
}
else
{
- reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+ reloc->sym_ptr_ptr = XNEW (asymbol *);
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
}
return & no_relocs;
}
#endif
- reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+ reloc->sym_ptr_ptr = XNEW (asymbol *);
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
reloc->addend = fixp->fx_offset;
}
else if (fragP->fr_symbol)
{
- /* Its got a segment, but its not ours. Even if fr_symbol is in
+ /* It's got a segment, but it's not ours. Even if fr_symbol is in
an absolute segment, we don't know a displacement until we link
object files. So it will always be long. This also applies to
labels in a subsegment of current. Liker may relax it to short
break;
default:
- as_fatal (_("internal inconsistency problem in %s: %lx"),
+ as_fatal (_("internal inconsistency problem in %s: %lx"),
__FUNCTION__, (long) fragP->fr_subtype);
break;
}
projects / deliverable / binutils-gdb.git / blobdiff