}
static struct nds32_pseudo_opcode *
-nds32_lookup_pseudo_opcode (char *str)
+nds32_lookup_pseudo_opcode (const char *str)
{
int i = 0;
/* Assume pseudo-opcode are less than 16-char in length. */
recognized. This will be handled by the generic code. */
int
-nds32_parse_option (int c, char *arg)
+nds32_parse_option (int c, const char *arg)
{
struct nds32_parse_option_table *coarse_tune;
struct nds32_set_option_table *fine_tune;
/* Check X_md to transform relocation. */
static fixS*
-nds32_elf_record_fixup_exp (fragS *fragP, char *str,
+nds32_elf_record_fixup_exp (fragS *fragP, const char *str,
const struct nds32_field *fld,
expressionS *pexp, char* out,
struct nds32_asm_insn *insn)
/* Check instruction if it can be used for the baseline. */
static bfd_boolean
-nds32_check_insn_available (struct nds32_asm_insn insn, char *str)
+nds32_check_insn_available (struct nds32_asm_insn insn, const char *str)
{
int attr = insn.attr & ATTR_ALL;
static int baseline_isa = 0;
md_assemble (char *str)
{
struct nds32_asm_insn insn;
+ expressionS expr;
char *out;
struct nds32_pseudo_opcode *popcode;
const struct nds32_field *fld = NULL;
}
label_exist = 0;
- insn.info = (expressionS *) alloca (sizeof (expressionS));
+ insn.info = & expr;
asm_desc.result = NASM_OK;
nds32_assemble (&asm_desc, &insn, str);