/* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
- 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+ 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support.
This file is part of GAS, the GNU Assembler.
static void ppc_function (int);
static void ppc_extern (int);
static void ppc_lglobl (int);
+static void ppc_ref (int);
static void ppc_section (int);
static void ppc_named_section (int);
static void ppc_stabx (int);
/* The type of processor we are assembling for. This is one or more
of the PPC_OPCODE flags defined in opcode/ppc.h. */
ppc_cpu_t ppc_cpu = 0;
+
+/* Flags set on encountering toc relocs. */
+enum {
+ has_large_toc_reloc = 1,
+ has_small_toc_reloc = 2
+} toc_reloc_types;
\f
/* The target specific pseudo-ops which we support. */
{ "extern", ppc_extern, 0 },
{ "function", ppc_function, 0 },
{ "lglobl", ppc_lglobl, 0 },
+ { "ref", ppc_ref, 0 },
{ "rename", ppc_rename, 0 },
{ "section", ppc_named_section, 0 },
{ "stabx", ppc_stabx, 0 },
expression. */
int
-ppc_parse_name (const char *name, expressionS *expr)
+ppc_parse_name (const char *name, expressionS *exp)
{
int val;
if (val < 0)
return 0;
- expr->X_op = O_constant;
- expr->X_add_number = val;
+ exp->X_op = O_constant;
+ exp->X_add_number = val;
return 1;
}
{
fprintf (stream, _("\
PowerPC options:\n\
--a32 generate ELF32/XCOFF32\n\
--a64 generate ELF64/XCOFF64\n\
--u ignored\n\
--mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n\
--mpwr generate code for POWER (RIOS1)\n\
--m601 generate code for PowerPC 601\n\
+-a32 generate ELF32/XCOFF32\n\
+-a64 generate ELF64/XCOFF64\n\
+-u ignored\n\
+-mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n\
+-mpwr generate code for POWER (RIOS1)\n\
+-m601 generate code for PowerPC 601\n\
-mppc, -mppc32, -m603, -m604\n\
- generate code for PowerPC 603/604\n\
--m403 generate code for PowerPC 403\n\
--m405 generate code for PowerPC 405\n\
--m440 generate code for PowerPC 440\n\
--m464 generate code for PowerPC 464\n\
+ generate code for PowerPC 603/604\n\
+-m403 generate code for PowerPC 403\n\
+-m405 generate code for PowerPC 405\n\
+-m440 generate code for PowerPC 440\n\
+-m464 generate code for PowerPC 464\n\
+-m476 generate code for PowerPC 476\n\
-m7400, -m7410, -m7450, -m7455\n\
- generate code for PowerPC 7400/7410/7450/7455\n\
--m750cl generate code for PowerPC 750cl\n"));
+ generate code for PowerPC 7400/7410/7450/7455\n\
+-m750cl generate code for PowerPC 750cl\n"));
fprintf (stream, _("\
--mppc64, -m620 generate code for PowerPC 620/625/630\n\
--mppc64bridge generate code for PowerPC 64, including bridge insns\n\
--mbooke generate code for 32-bit PowerPC BookE\n\
--mppca2 generate code for A2 architecture\n\
--mpower4 generate code for Power4 architecture\n\
--mpower5 generate code for Power5 architecture\n\
--mpower6 generate code for Power6 architecture\n\
--mpower7 generate code for Power7 architecture\n\
--mcell generate code for Cell Broadband Engine architecture\n\
--mcom generate code Power/PowerPC common instructions\n\
--many generate code for any architecture (PWR/PWRX/PPC)\n"));
+-mppc64, -m620 generate code for PowerPC 620/625/630\n\
+-mppc64bridge generate code for PowerPC 64, including bridge insns\n\
+-mbooke generate code for 32-bit PowerPC BookE\n\
+-ma2 generate code for A2 architecture\n\
+-mpower4, -mpwr4 generate code for Power4 architecture\n\
+-mpower5, -mpwr5, -mpwr5x\n\
+ generate code for Power5 architecture\n\
+-mpower6, -mpwr6 generate code for Power6 architecture\n\
+-mpower7, -mpwr7 generate code for Power7 architecture\n\
+-mcell generate code for Cell Broadband Engine architecture\n\
+-mcom generate code Power/PowerPC common instructions\n\
+-many generate code for any architecture (PWR/PWRX/PPC)\n"));
fprintf (stream, _("\
--maltivec generate code for AltiVec\n\
--mvsx generate code for Vector-Scalar (VSX) instructions\n\
--me300 generate code for PowerPC e300 family\n\
--me500, -me500x2 generate code for Motorola e500 core complex\n\
+-maltivec generate code for AltiVec\n\
+-mvsx generate code for Vector-Scalar (VSX) instructions\n\
+-me300 generate code for PowerPC e300 family\n\
+-me500, -me500x2 generate code for Motorola e500 core complex\n\
-me500mc, generate code for Freescale e500mc core complex\n\
--mspe generate code for Motorola SPE instructions\n\
--mregnames Allow symbolic names for registers\n\
--mno-regnames Do not allow symbolic names for registers\n"));
+-me500mc64, generate code for Freescale e500mc64 core complex\n\
+-mspe generate code for Motorola SPE instructions\n\
+-mtitan generate code for AppliedMicro Titan core complex\n\
+-mregnames Allow symbolic names for registers\n\
+-mno-regnames Do not allow symbolic names for registers\n"));
#ifdef OBJ_ELF
fprintf (stream, _("\
--mrelocatable support for GCC's -mrelocatble option\n\
--mrelocatable-lib support for GCC's -mrelocatble-lib option\n\
--memb set PPC_EMB bit in ELF flags\n\
+-mrelocatable support for GCC's -mrelocatble option\n\
+-mrelocatable-lib support for GCC's -mrelocatble-lib option\n\
+-memb set PPC_EMB bit in ELF flags\n\
-mlittle, -mlittle-endian, -l, -le\n\
- generate code for a little endian machine\n\
+ generate code for a little endian machine\n\
-mbig, -mbig-endian, -b, -be\n\
- generate code for a big endian machine\n\
--msolaris generate code for Solaris\n\
--mno-solaris do not generate code for Solaris\n\
--V print assembler version number\n\
--Qy, -Qn ignored\n"));
+ generate code for a big endian machine\n\
+-msolaris generate code for Solaris\n\
+-mno-solaris do not generate code for Solaris\n\
+-V print assembler version number\n\
+-Qy, -Qn ignored\n"));
#endif
}
\f
const char *default_os = TARGET_OS;
const char *default_cpu = TARGET_CPU;
- if ((ppc_cpu & ~PPC_OPCODE_ANY) == 0)
+ if ((ppc_cpu & ~(ppc_cpu_t) PPC_OPCODE_ANY) == 0)
{
if (ppc_obj64)
- ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64;
+ ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_64;
else if (strncmp (default_os, "aix", 3) == 0
&& default_os[3] >= '4' && default_os[3] <= '9')
- ppc_cpu |= PPC_OPCODE_COMMON | PPC_OPCODE_32;
+ ppc_cpu |= PPC_OPCODE_COMMON;
else if (strncmp (default_os, "aix3", 4) == 0)
- ppc_cpu |= PPC_OPCODE_POWER | PPC_OPCODE_32;
+ ppc_cpu |= PPC_OPCODE_POWER;
else if (strcmp (default_cpu, "rs6000") == 0)
- ppc_cpu |= PPC_OPCODE_POWER | PPC_OPCODE_32;
+ ppc_cpu |= PPC_OPCODE_POWER;
else if (strncmp (default_cpu, "powerpc", 7) == 0)
- ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32;
+ ppc_cpu |= PPC_OPCODE_PPC;
else
as_fatal (_("Unknown default cpu = %s, os = %s"),
default_cpu, default_os);
return bfd_mach_ppc64;
else if (ppc_arch () == bfd_arch_rs6000)
return bfd_mach_rs6k;
+ else if (ppc_cpu & PPC_OPCODE_TITAN)
+ return bfd_mach_ppc_titan;
else
return bfd_mach_ppc;
}
}
}
- if ((op->flags & ppc_cpu & ~(PPC_OPCODE_32 | PPC_OPCODE_64)) != 0
- && ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == 0
- || ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64))
- == (ppc_cpu & (PPC_OPCODE_32 | PPC_OPCODE_64)))
- || (ppc_cpu & PPC_OPCODE_64_BRIDGE) != 0)
+ if ((ppc_cpu & op->flags) != 0
&& !(ppc_cpu & op->deprecated))
{
const char *retval;
retval = hash_insert (ppc_hash, op->name, (void *) op);
if (retval != NULL)
{
- /* Ignore Power duplicates for -m601. */
- if ((ppc_cpu & PPC_OPCODE_601) != 0
- && (op->flags & PPC_OPCODE_POWER) != 0)
- continue;
-
as_bad (_("duplicate instruction %s"),
op->name);
bad_insn = TRUE;
ppc_insert_operand (unsigned long insn,
const struct powerpc_operand *operand,
offsetT val,
- ppc_cpu_t ppc_cpu,
+ ppc_cpu_t cpu,
char *file,
unsigned int line)
{
const char *errmsg;
errmsg = NULL;
- insn = (*operand->insert) (insn, (long) val, ppc_cpu, &errmsg);
+ insn = (*operand->insert) (insn, (long) val, cpu, &errmsg);
if (errmsg != (const char *) NULL)
as_bad_where (file, line, "%s", errmsg);
}
int offset;
p = frag_more (nbytes);
+ memset (p, 0, nbytes);
offset = 0;
if (target_big_endian)
offset = nbytes - size;
toc = bfd_get_section_by_name (stdoutput, ".toc");
if (toc != NULL
+ && toc_reloc_types != has_large_toc_reloc
&& bfd_section_size (stdoutput, toc) > 0x10000)
as_warn (_("TOC section size exceeds 64k"));
{
unsigned int opcount;
unsigned int num_operands_expected;
- unsigned int i;
/* There is an optional operand. Count the number of
commas in the input line. */
break;
case BFD_RELOC_PPC_TLS:
- insn = ppc_insert_operand (insn, operand, ppc_obj64 ? 13 : 2,
- ppc_cpu, (char *) NULL, 0);
+ if (!_bfd_elf_ppc_at_tls_transform (opcode->opcode, 0))
+ as_bad (_("@tls may not be used with \"%s\" operands"),
+ opcode->name);
+ else if (operand->shift != 11)
+ as_bad (_("@tls may only be used in last operand"));
+ else
+ insn = ppc_insert_operand (insn, operand,
+ ppc_obj64 ? 13 : 2,
+ ppc_cpu, (char *) NULL, 0);
break;
/* We'll only use the 32 (or 64) bit form of these relocations
}
}
+ switch (reloc)
+ {
+ case BFD_RELOC_PPC_TOC16:
+ toc_reloc_types |= has_small_toc_reloc;
+ break;
+ case BFD_RELOC_PPC64_TOC16_LO:
+ case BFD_RELOC_PPC64_TOC16_HI:
+ case BFD_RELOC_PPC64_TOC16_HA:
+ toc_reloc_types |= has_large_toc_reloc;
+ break;
+ default:
+ break;
+ }
+
if (ppc_obj64
&& (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0)
{
#ifdef OBJ_ELF
/* Do we need/want a APUinfo section? */
- if ((ppc_cpu & PPC_OPCODE_E500MC) != 0)
+ if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC)) != 0)
{
/* These are all version "1". */
if (opcode->flags & PPC_OPCODE_SPE)
}
\f
#ifdef OBJ_ELF
-/* For ELF, add support for SHF_EXCLUDE and SHT_ORDERED. */
-
-bfd_vma
-ppc_section_letter (int letter, char **ptr_msg)
-{
- if (letter == 'e')
- return SHF_EXCLUDE;
-
- *ptr_msg = _("Bad .section directive: want a,e,w,x,M,S,G,T in string");
- return -1;
-}
-
-bfd_vma
-ppc_section_word (char *str, size_t len)
-{
- if (len == 7 && strncmp (str, "exclude", 7) == 0)
- return SHF_EXCLUDE;
-
- return -1;
-}
+/* For ELF, add support for SHT_ORDERED. */
int
ppc_section_type (char *str, size_t len)
}
int
-ppc_section_flags (flagword flags, bfd_vma attr, int type)
+ppc_section_flags (flagword flags, bfd_vma attr ATTRIBUTE_UNUSED, int type)
{
if (type == SHT_ORDERED)
flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES;
- if (attr & SHF_EXCLUDE)
- flags |= SEC_EXCLUDE;
-
return flags;
}
#endif /* OBJ_ELF */
demand_empty_rest_of_line ();
}
+/* The .ref pseudo-op. It takes a list of symbol names and inserts R_REF
+ relocations at the beginning of the current csect.
+
+ (In principle, there's no reason why the relocations _have_ to be at
+ the beginning. Anywhere in the csect would do. However, inserting
+ at the beginning is what the native assmebler does, and it helps to
+ deal with cases where the .ref statements follow the section contents.)
+
+ ??? .refs don't work for empty .csects. However, the native assembler
+ doesn't report an error in this case, and neither yet do we. */
+
+static void
+ppc_ref (int ignore ATTRIBUTE_UNUSED)
+{
+ char *name;
+ char c;
+
+ if (ppc_current_csect == NULL)
+ {
+ as_bad (_(".ref outside .csect"));
+ ignore_rest_of_line ();
+ return;
+ }
+
+ do
+ {
+ name = input_line_pointer;
+ c = get_symbol_end ();
+
+ fix_at_start (symbol_get_frag (ppc_current_csect), 0,
+ symbol_find_or_make (name), 0, FALSE, BFD_RELOC_NONE);
+
+ *input_line_pointer = c;
+ SKIP_WHITESPACE ();
+ c = *input_line_pointer;
+ if (c == ',')
+ {
+ input_line_pointer++;
+ SKIP_WHITESPACE ();
+ if (is_end_of_line[(unsigned char) *input_line_pointer])
+ {
+ as_bad (_("missing symbol name"));
+ ignore_rest_of_line ();
+ return;
+ }
+ }
+ }
+ while (c == ',');
+
+ demand_empty_rest_of_line ();
+}
+
/* The .rename pseudo-op. The RS/6000 assembler can rename symbols,
although I don't know why it bothers. */
if (*input_line_pointer == ',')
{
- expressionS ignore;
+ expressionS exp;
/* Ignore the third argument. */
++input_line_pointer;
- expression (&ignore);
+ expression (& exp);
if (*input_line_pointer == ',')
{
/* Ignore the fourth argument. */
++input_line_pointer;
- expression (&ignore);
+ expression (& exp);
if (*input_line_pointer == ',')
{
/* The fifth argument is the function size. */
PPC_HA (value), 2);
break;
+#ifdef OBJ_XCOFF
+ case BFD_RELOC_NONE:
+ break;
+#endif
+
#ifdef OBJ_ELF
case BFD_RELOC_PPC64_HIGHER:
if (fixP->fx_pcrel)
projects / deliverable / binutils-gdb.git / blobdiff