* config/tc-ppc.c (mapping): Map sectoff to BFD_RELOC_16_BASEREL.

[deliverable/binutils-gdb.git] / gas / config / tc-ppc.c

diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 8bf09db71ad6cd832eab898c920a8dc61c74d4a7..567e3c6aea01770f1a60ef18fab1799422564d5e 100644 (file)
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1,5 +1,5 @@
 /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
    Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support.
 
@@ -876,18 +876,18 @@ md_parse_option (c, arg)
       /* -mpwr means to assemble for the IBM POWER (RIOS1).  */
       else if (strcmp (arg, "pwr") == 0)
        ppc_cpu = PPC_OPCODE_POWER;
-      /* -m601 means to assemble for the Motorola PowerPC 601, which includes
+      /* -m601 means to assemble for the PowerPC 601, which includes
         instructions that are holdovers from the Power.  */
       else if (strcmp (arg, "601") == 0)
        ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_601;
       /* -mppc, -mppc32, -m603, and -m604 mean to assemble for the
-        Motorola PowerPC 603/604.  */
+        PowerPC 603/604.  */
       else if (strcmp (arg, "ppc") == 0
               || strcmp (arg, "ppc32") == 0
               || strcmp (arg, "603") == 0
               || strcmp (arg, "604") == 0)
        ppc_cpu = PPC_OPCODE_PPC;
-      /* -m403 and -m405 mean to assemble for the Motorola PowerPC 403/405.  */
+      /* -m403 and -m405 mean to assemble for the PowerPC 403/405.  */
       else if (strcmp (arg, "403") == 0
                || strcmp (arg, "405") == 0)
        ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_403;
@@ -925,6 +925,11 @@ md_parse_option (c, arg)
                    PPC_OPCODE_BOOKE64 | PPC_OPCODE_64;
          ppc_size = PPC_OPCODE_64;
        }
+      else if (strcmp (arg, "power4") == 0)
+       {
+         ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4;
+         ppc_size = PPC_OPCODE_64;
+       }
       /* -mcom means assemble for the common intersection between Power
         and PowerPC.  At present, we just allow the union, rather
         than the intersection.  */
@@ -1027,18 +1032,19 @@ md_show_usage (stream)
   fprintf (stream, _("\
 PowerPC options:\n\
 -u                     ignored\n\
--mpwrx, -mpwr2         generate code for IBM POWER/2 (RIOS2)\n\
--mpwr                  generate code for IBM POWER (RIOS1)\n\
--m601                  generate code for Motorola PowerPC 601\n\
+-mpwrx, -mpwr2         generate code for POWER/2 (RIOS2)\n\
+-mpwr                  generate code for POWER (RIOS1)\n\
+-m601                  generate code for PowerPC 601\n\
 -mppc, -mppc32, -m603, -m604\n\
-                       generate code for Motorola PowerPC 603/604\n\
--m403, -m405            generate code for Motorola PowerPC 403/405\n\
+                       generate code for PowerPC 603/604\n\
+-m403, -m405            generate code for PowerPC 403/405\n\
 -m7400, -m7410, -m7450, -m7455\n\
-                       generate code For Motorola PowerPC 7400/7410/7450/7455\n\
--mppc64, -m620         generate code for Motorola PowerPC 620\n\
+                       generate code For PowerPC 7400/7410/7450/7455\n\
+-mppc64, -m620         generate code for PowerPC 620/625/630\n\
 -mppc64bridge          generate code for PowerPC 64, including bridge insns\n\
 -mbooke64              generate code for 64-bit PowerPC BookE\n\
 -mbooke, mbooke32      generate code for 32-bit PowerPC BookE\n\
+-mpower4               generate code for Power4 architecture\n\
 -maltivec              generate code for AltiVec\n\
 -mcom                  generate code Power/PowerPC common instructions\n\
 -many                  generate code for any architecture (PWR/PWRX/PPC)\n\
@@ -1131,7 +1137,11 @@ ppc_target_format ()
 #elif TE_POWERMAC
   return "xcoff-powermac";
 #else
-  return ppc_xcoff64 ? "aixcoff64-rs6000" : "aixcoff-rs6000";
+#  ifdef TE_AIX5
+    return (ppc_xcoff64 ? "aix5coff64-rs6000" : "aixcoff-rs6000");
+#  else
+    return (ppc_xcoff64 ? "aixcoff64-rs6000" : "aixcoff-rs6000");
+#  endif
 #endif
 #endif
 #ifdef OBJ_ELF
@@ -1175,7 +1185,10 @@ md_begin ()
       if ((op->flags & ppc_cpu) != 0
          && ((op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == 0
              || (op->flags & (PPC_OPCODE_32 | PPC_OPCODE_64)) == ppc_size
-             || (ppc_cpu & PPC_OPCODE_64_BRIDGE) != 0))
+             || (ppc_cpu & PPC_OPCODE_64_BRIDGE) != 0)
+         && ((op->flags & (PPC_OPCODE_POWER4 | PPC_OPCODE_NOPOWER4)) == 0
+             || ((op->flags & PPC_OPCODE_POWER4)
+                 == (ppc_cpu & PPC_OPCODE_POWER4))))
        {
          const char *retval;
 
@@ -1365,7 +1378,7 @@ ppc_elf_suffix (str_p, exp_p)
     MAP ("plt@h",      (int) BFD_RELOC_HI16_PLTOFF),
     MAP ("plt@ha",     (int) BFD_RELOC_HI16_S_PLTOFF),
     MAP ("sdarel",     (int) BFD_RELOC_GPREL16),
-    MAP ("sectoff",    (int) BFD_RELOC_32_BASEREL),
+    MAP ("sectoff",    (int) BFD_RELOC_16_BASEREL),
     MAP ("sectoff@l",  (int) BFD_RELOC_LO16_BASEREL),
     MAP ("sectoff@h",  (int) BFD_RELOC_HI16_BASEREL),
     MAP ("sectoff@ha", (int) BFD_RELOC_HI16_S_BASEREL),
@@ -1674,7 +1687,7 @@ ppc_elf_validate_fix (fixp, seg)
          && fixp->fx_r_type != BFD_RELOC_HI16_GOTOFF
          && fixp->fx_r_type != BFD_RELOC_LO16_GOTOFF
          && fixp->fx_r_type != BFD_RELOC_HI16_S_GOTOFF
-         && fixp->fx_r_type != BFD_RELOC_32_BASEREL
+         && fixp->fx_r_type != BFD_RELOC_16_BASEREL
          && fixp->fx_r_type != BFD_RELOC_LO16_BASEREL
          && fixp->fx_r_type != BFD_RELOC_HI16_BASEREL
          && fixp->fx_r_type != BFD_RELOC_HI16_S_BASEREL
@@ -2227,7 +2240,7 @@ md_assemble (str)
                case BFD_RELOC_LO16_PLTOFF:
                  reloc = BFD_RELOC_PPC64_PLT16_LO_DS;
                  break;
-               case BFD_RELOC_32_BASEREL:
+               case BFD_RELOC_16_BASEREL:
                  reloc = BFD_RELOC_PPC64_SECTOFF_DS;
                  break;
                case BFD_RELOC_LO16_BASEREL:
@@ -5165,7 +5178,7 @@ md_apply_fix3 (fixP, valP, seg)
       if ((operand->flags & PPC_OPERAND_PARENS) != 0
          && operand->bits == 16
          && operand->shift == 0
-         && operand->insert == NULL
+         && (operand->insert == NULL || ppc_xcoff64)
          && fixP->fx_addsy != NULL
          && symbol_get_tc (fixP->fx_addsy)->subseg != 0
          && symbol_get_tc (fixP->fx_addsy)->class != XMC_TC
@@ -5271,7 +5284,6 @@ md_apply_fix3 (fixP, valP, seg)
 
        case BFD_RELOC_RVA:
        case BFD_RELOC_32_PCREL:
-       case BFD_RELOC_32_BASEREL:
        case BFD_RELOC_PPC_EMB_NADDR32:
          md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
                              value, 4);
@@ -5296,6 +5308,7 @@ md_apply_fix3 (fixP, valP, seg)
        case BFD_RELOC_LO16_GOTOFF:
        case BFD_RELOC_HI16_GOTOFF:
        case BFD_RELOC_HI16_S_GOTOFF:
+       case BFD_RELOC_16_BASEREL:
        case BFD_RELOC_LO16_BASEREL:
        case BFD_RELOC_HI16_BASEREL:
        case BFD_RELOC_HI16_S_BASEREL: