RISC-V: Add compressed instruction hints, and a few misc cleanups.

[deliverable/binutils-gdb.git] / gas / config / tc-riscv.c

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 8bb400e1001bbb74ade4db73c6c2c3e552634ee5..a4e01b6c798a7195fd26704b0c11acd4088c83af 100644 (file)
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1384,6 +1384,9 @@ rvc_imm_done:
                case 'o':
                  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
                      || imm_expr->X_op != O_constant
+                     /* C.addiw, c.li, and c.andi allow zero immediate.
+                        C.addi allows zero immediate as hint.  Otherwise this
+                        is same as 'j'.  */
                      || !VALID_RVC_IMM (imm_expr->X_add_number))
                    break;
                  ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
@@ -2319,10 +2322,18 @@ bfd_boolean
 riscv_frag_align_code (int n)
 {
   bfd_vma bytes = (bfd_vma) 1 << n;
-  bfd_vma worst_case_bytes = bytes - (riscv_opts.rvc ? 2 : 4);
-  char *nops = frag_more (worst_case_bytes);
+  bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4;
+  bfd_vma worst_case_bytes = bytes - insn_alignment;
+  char *nops;
   expressionS ex;
 
+  /* If we are moving to a smaller alignment than the instruction size, then no
+     alignment is required. */
+  if (bytes <= insn_alignment)
+    return TRUE;
+
+  nops = frag_more (worst_case_bytes);
+
   /* When not relaxing, riscv_handle_align handles code alignment.  */
   if (!riscv_opts.relax)
     return FALSE;