/* tc-sh.c -- Assemble code for the Renesas / SuperH SH
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003, 2004 Free Software Foundation, Inc.
+ 2003, 2004, 2005 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
int sh_small;
+/* Flag to generate relocations against symbol values for local symbols. */
+
+static int dont_adjust_reloc_32;
+
/* preset architecture set, if given; zero otherwise. */
-static int preset_target_arch;
+static unsigned int preset_target_arch;
/* The bit mask of architectures that could
accommodate the insns seen so far. */
-static int valid_arch;
+static unsigned int valid_arch;
const char EXP_CHARS[] = "eE";
{
const sh_opcode_info *opcode;
char *prev_name = "";
- int target_arch;
+ unsigned int target_arch;
target_arch
- = preset_target_arch ? preset_target_arch : arch_sh1_up & ~arch_sh_dsp_up;
+ = preset_target_arch ? preset_target_arch : arch_sh_up & ~arch_sh_has_dsp;
valid_arch = target_arch;
#ifdef HAVE_SH64
{
if (strcmp (prev_name, opcode->name) != 0)
{
- if (! (opcode->arch & target_arch))
+ if (!SH_MERGE_ARCH_SET_VALID (opcode->arch, target_arch))
continue;
prev_name = opcode->name;
hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
return 3;
}
+ if (l0 == 't' && l1 == 'b' && TOLOWER (src[2]) == 'r'
+ && ! IDENT_CHAR ((unsigned char) src[3]))
+ {
+ *mode = A_TBR;
+ return 3;
+ }
if (l0 == 'm' && l1 == 'a' && TOLOWER (src[2]) == 'c'
&& ! IDENT_CHAR ((unsigned char) src[4]))
{
int len;
int mode;
src++;
- if (src[0] == '-')
+ if (src[0] == '@')
+ {
+ src = parse_at (src, op);
+ if (op->type == A_DISP_TBR)
+ op->type = A_DISP2_TBR;
+ else
+ as_bad (_("illegal double indirection"));
+ }
+ else if (src[0] == '-')
{
/* Must be predecrement. */
src++;
{
op->type = A_DISP_GBR;
}
+ else if (mode == A_TBR)
+ {
+ op->type = A_DISP_TBR;
+ }
else if (mode == A_PC)
{
/* We want @(expr, pc) to uniformly address . + expr,
sh_operand_info *user = operands + n;
sh_arg_type arg = this_try->arg[n];
+ if (SH_MERGE_ARCH_SET_VALID (valid_arch, arch_sh2a_nofpu_up)
+ && ( arg == A_DISP_REG_M
+ || arg == A_DISP_REG_N))
+ {
+ /* Check a few key IMM* fields for overflow. */
+ int opf;
+ long val = user->immediate.X_add_number;
+
+ for (opf = 0; opf < 4; opf ++)
+ switch (this_try->nibbles[opf])
+ {
+ case IMM0_4:
+ case IMM1_4:
+ if (val < 0 || val > 15)
+ goto fail;
+ break;
+ case IMM0_4BY2:
+ case IMM1_4BY2:
+ if (val < 0 || val > 15 * 2)
+ goto fail;
+ break;
+ case IMM0_4BY4:
+ case IMM1_4BY4:
+ if (val < 0 || val > 15 * 4)
+ goto fail;
+ break;
+ default:
+ break;
+ }
+ }
switch (arg)
{
case A_DISP_PC:
case A_BDISP12:
case A_BDISP8:
case A_DISP_GBR:
+ case A_DISP2_TBR:
case A_MACH:
case A_PR:
case A_MACL:
reg_n = user->reg;
break;
case A_GBR:
+ case A_TBR:
case A_SR:
case A_VBR:
case A_DSR:
reg_b = user->reg;
break;
+ case A_INC_R15:
+ if (user->type != A_INC_N)
+ goto fail;
+ if (user->reg != 15)
+ goto fail;
+ reg_n = user->reg;
+ break;
+
+ case A_DEC_R15:
+ if (user->type != A_DEC_N)
+ goto fail;
+ if (user->reg != 15)
+ goto fail;
+ reg_n = user->reg;
+ break;
+
case A_REG_M:
case A_INC_M:
case A_DEC_M:
goto fail;
}
}
- if ( !(valid_arch & this_try->arch))
+ if ( !SH_MERGE_ARCH_SET_VALID (valid_arch, this_try->arch))
goto fail;
- valid_arch &= this_try->arch;
+ valid_arch = SH_MERGE_ARCH_SET (valid_arch, this_try->arch);
return this_try;
fail:
;
how);
}
+static void
+insert4 (char * where, int how, int pcrel, sh_operand_info * op)
+{
+ fix_new_exp (frag_now,
+ where - frag_now->fr_literal,
+ 4,
+ & op->immediate,
+ pcrel,
+ how);
+}
static void
build_relax (sh_opcode_info *opcode, sh_operand_info *op)
{
build_Mytes (sh_opcode_info *opcode, sh_operand_info *operand)
{
int index;
- char nbuf[4];
- char *output = frag_more (2);
+ char nbuf[8];
+ char *output;
unsigned int size = 2;
int low_byte = target_big_endian ? 1 : 0;
+ int max_index = 4;
+
nbuf[0] = 0;
nbuf[1] = 0;
nbuf[2] = 0;
nbuf[3] = 0;
+ nbuf[4] = 0;
+ nbuf[5] = 0;
+ nbuf[6] = 0;
+ nbuf[7] = 0;
- for (index = 0; index < 4; index++)
+ if (SH_MERGE_ARCH_SET (opcode->arch, arch_op32))
+ {
+ output = frag_more (4);
+ size = 4;
+ max_index = 8;
+ }
+ else
+ output = frag_more (2);
+
+ for (index = 0; index < max_index; index++)
{
sh_nibble_type i = opcode->nibbles[index];
if (i < 16)
case REG_N_B01:
nbuf[index] = reg_n | 0x01;
break;
+ case IMM0_3s:
+ nbuf[index] |= 0x08;
+ case IMM0_3c:
+ insert (output + low_byte, BFD_RELOC_SH_IMM3, 0, operand);
+ break;
+ case IMM0_3Us:
+ nbuf[index] |= 0x80;
+ case IMM0_3Uc:
+ insert (output + low_byte, BFD_RELOC_SH_IMM3U, 0, operand);
+ break;
+ case DISP0_12:
+ insert (output + 2, BFD_RELOC_SH_DISP12, 0, operand);
+ break;
+ case DISP0_12BY2:
+ insert (output + 2, BFD_RELOC_SH_DISP12BY2, 0, operand);
+ break;
+ case DISP0_12BY4:
+ insert (output + 2, BFD_RELOC_SH_DISP12BY4, 0, operand);
+ break;
+ case DISP0_12BY8:
+ insert (output + 2, BFD_RELOC_SH_DISP12BY8, 0, operand);
+ break;
+ case DISP1_12:
+ insert (output + 2, BFD_RELOC_SH_DISP12, 0, operand+1);
+ break;
+ case DISP1_12BY2:
+ insert (output + 2, BFD_RELOC_SH_DISP12BY2, 0, operand+1);
+ break;
+ case DISP1_12BY4:
+ insert (output + 2, BFD_RELOC_SH_DISP12BY4, 0, operand+1);
+ break;
+ case DISP1_12BY8:
+ insert (output + 2, BFD_RELOC_SH_DISP12BY8, 0, operand+1);
+ break;
+ case IMM0_20_4:
+ break;
+ case IMM0_20:
+ insert4 (output, BFD_RELOC_SH_DISP20, 0, operand);
+ break;
+ case IMM0_20BY8:
+ insert4 (output, BFD_RELOC_SH_DISP20BY8, 0, operand);
+ break;
case IMM0_4BY4:
insert (output + low_byte, BFD_RELOC_SH_IMM4BY4, 0, operand);
break;
output[0] = (nbuf[0] << 4) | (nbuf[1]);
output[1] = (nbuf[2] << 4) | (nbuf[3]);
}
+ if (SH_MERGE_ARCH_SET (opcode->arch, arch_op32))
+ {
+ if (!target_big_endian)
+ {
+ output[3] = (nbuf[4] << 4) | (nbuf[5]);
+ output[2] = (nbuf[6] << 4) | (nbuf[7]);
+ }
+ else
+ {
+ output[2] = (nbuf[4] << 4) | (nbuf[5]);
+ output[3] = (nbuf[6] << 4) | (nbuf[7]);
+ }
+ }
return size;
}
field_b -= 0x8100;
/* pclr Dz pmuls Se,Sf,Dg */
else if ((field_b & 0xff00) == 0x8d00
- && (valid_arch & arch_sh4al_dsp_up))
+ && (SH_MERGE_ARCH_SET_VALID (valid_arch, arch_sh4al_dsp_up)))
{
- valid_arch &= arch_sh4al_dsp_up;
+ valid_arch = SH_MERGE_ARCH_SET (valid_arch, arch_sh4al_dsp_up);
field_b -= 0x8cf0;
}
else
int found = 0;
/* identify opcode in string */
- while (isspace (*name))
+ while (ISSPACE (*name))
{
name++;
}
- while (!isspace (name[name_length]))
+ while (!ISSPACE (name[name_length]))
{
name_length++;
}
/* search for opcode in full list */
for (op = sh_table; op->name; op++)
{
- if (strncasecmp (op->name, name, name_length) == 0)
+ if (strncasecmp (op->name, name, name_length) == 0
+ && op->name[name_length] == '\0')
{
found = 1;
break;
{
/* Since we skip get_specific here, we have to check & update
valid_arch now. */
- if (valid_arch & opcode->arch)
- valid_arch &= opcode->arch;
+ if (SH_MERGE_ARCH_SET_VALID (valid_arch, opcode->arch))
+ valid_arch = SH_MERGE_ARCH_SET (valid_arch, opcode->arch);
else
as_bad (_("Delayed branches not available on SH1"));
parse_exp (op_end + 1, &operand[0]);
#define OPTION_SMALL (OPTION_LITTLE + 1)
#define OPTION_DSP (OPTION_SMALL + 1)
#define OPTION_ISA (OPTION_DSP + 1)
+#define OPTION_RENESAS (OPTION_ISA + 1)
{"relax", no_argument, NULL, OPTION_RELAX},
{"big", no_argument, NULL, OPTION_BIG},
{"small", no_argument, NULL, OPTION_SMALL},
{"dsp", no_argument, NULL, OPTION_DSP},
{"isa", required_argument, NULL, OPTION_ISA},
+ {"renesas", no_argument, NULL, OPTION_RENESAS},
+
#ifdef HAVE_SH64
-#define OPTION_ABI (OPTION_ISA + 1)
+#define OPTION_ABI (OPTION_RENESAS + 1)
#define OPTION_NO_MIX (OPTION_ABI + 1)
#define OPTION_SHCOMPACT_CONST_CRANGE (OPTION_NO_MIX + 1)
#define OPTION_NO_EXPAND (OPTION_SHCOMPACT_CONST_CRANGE + 1)
break;
case OPTION_DSP:
- preset_target_arch = arch_sh1_up & ~arch_sh2e_up;
+ preset_target_arch = arch_sh_up & ~(arch_sh_sp_fpu|arch_sh_dp_fpu);
+ break;
+
+ case OPTION_RENESAS:
+ dont_adjust_reloc_32 = 1;
break;
case OPTION_ISA:
- if (strcasecmp (arg, "sh4") == 0)
- preset_target_arch = arch_sh4;
- else if (strcasecmp (arg, "sh4-nofpu") == 0)
- preset_target_arch = arch_sh4_nofpu;
- else if (strcasecmp (arg, "sh4-nommu-nofpu") == 0)
- preset_target_arch = arch_sh4_nommu_nofpu;
- else if (strcasecmp (arg, "sh4a") == 0)
- preset_target_arch = arch_sh4a;
- else if (strcasecmp (arg, "dsp") == 0)
- preset_target_arch = arch_sh1_up & ~arch_sh2e_up;
+ if (strcasecmp (arg, "dsp") == 0)
+ preset_target_arch = arch_sh_up & ~(arch_sh_sp_fpu|arch_sh_dp_fpu);
else if (strcasecmp (arg, "fp") == 0)
- preset_target_arch = arch_sh2e_up;
+ preset_target_arch = arch_sh_up & ~arch_sh_has_dsp;
else if (strcasecmp (arg, "any") == 0)
- preset_target_arch = arch_sh1_up;
+ preset_target_arch = arch_sh_up;
#ifdef HAVE_SH64
else if (strcasecmp (arg, "shmedia") == 0)
{
}
#endif /* HAVE_SH64 */
else
- as_bad ("Invalid argument to --isa option: %s", arg);
+ {
+ extern const bfd_arch_info_type bfd_sh_arch;
+ bfd_arch_info_type const *bfd_arch = &bfd_sh_arch;
+ preset_target_arch = 0;
+ for (; bfd_arch; bfd_arch=bfd_arch->next)
+ {
+ int len = strlen(bfd_arch->printable_name);
+
+ if (bfd_arch->mach == bfd_mach_sh5)
+ continue;
+
+ if (strncasecmp (bfd_arch->printable_name, arg, len) != 0)
+ continue;
+
+ if (arg[len] == '\0')
+ preset_target_arch =
+ sh_get_arch_from_bfd_mach (bfd_arch->mach);
+ else if (strcasecmp(&arg[len], "-up") == 0)
+ preset_target_arch =
+ sh_get_arch_up_from_bfd_mach (bfd_arch->mach);
+ else
+ continue;
+ break;
+ }
+
+ if (!preset_target_arch)
+ as_bad ("Invalid argument to --isa option: %s", arg);
+ }
break;
#ifdef HAVE_SH64
-little generate little endian code\n\
-big generate big endian code\n\
-relax alter jump instructions for long displacements\n\
+-renesas disable optimization with section symbol for\n\
+ compatibility with Renesas assembler.\n\
-small align sections to 4 byte boundaries, not 16\n\
-dsp enable sh-dsp insns, and disable floating-point ISAs.\n\
--isa=[sh4\n\
- | sh4-nofpu sh4 with fpu disabled\n\
- | sh4-nommu-nofpu sh4 with no MMU or FPU\n\
- | sh4a\n\
+-isa=[any use most appropriate isa\n\
| dsp same as '-dsp'\n\
- | fp\n\
- | any] use most appropriate isa\n"));
+ | fp"));
+ {
+ extern const bfd_arch_info_type bfd_sh_arch;
+ bfd_arch_info_type const *bfd_arch = &bfd_sh_arch;
+ for (; bfd_arch; bfd_arch=bfd_arch->next)
+ if (bfd_arch->mach != bfd_mach_sh5)
+ {
+ fprintf (stream, "\n | %s", bfd_arch->printable_name);
+ fprintf (stream, "\n | %s-up", bfd_arch->printable_name);
+ }
+ }
+ fprintf (stream, "]\n");
#ifdef HAVE_SH64
fprintf (stream, _("\
-isa=[shmedia set as the default instruction set for SH64\n\
if (fixP->fx_r_type == BFD_RELOC_32_PLT_PCREL
|| fixP->fx_r_type == BFD_RELOC_32_GOT_PCREL
|| fixP->fx_r_type == BFD_RELOC_SH_GOTPC
+ || ((fixP->fx_r_type == BFD_RELOC_32) && dont_adjust_reloc_32)
|| fixP->fx_r_type == BFD_RELOC_RVA)
return 0;
if (sh64_isa_mode != sh64_isa_unspecified)
val = EF_SH5;
else
+#elif defined TARGET_SYMBIAN
+ if (1)
+ val = sh_symbian_find_elf_flags (valid_arch);
+ else
#endif /* HAVE_SH64 */
- if (valid_arch & arch_sh1)
- val = EF_SH1;
- else if (valid_arch & arch_sh2)
- val = EF_SH2;
- else if (valid_arch & arch_sh2e)
- val = EF_SH2E;
- else if (valid_arch & arch_sh_dsp)
- val = EF_SH_DSP;
- else if (valid_arch & arch_sh3)
- val = EF_SH3;
- else if (valid_arch & arch_sh3_dsp)
- val = EF_SH3_DSP;
- else if (valid_arch & arch_sh3e)
- val = EF_SH3E;
- else if (valid_arch & arch_sh4_nommu_nofpu)
- val = EF_SH4_NOMMU_NOFPU;
- else if (valid_arch & arch_sh4_nofpu)
- val = EF_SH4_NOFPU;
- else if (valid_arch & arch_sh4)
- val = EF_SH4;
- else if (valid_arch & arch_sh4a_nofpu)
- val = EF_SH4A_NOFPU;
- else if (valid_arch & arch_sh4a)
- val = EF_SH4A;
- else if (valid_arch & arch_sh4al_dsp)
- val = EF_SH4AL_DSP;
- else
- abort ();
+ val = sh_find_elf_flags (valid_arch);
elf_elfheader (stdoutput)->e_flags &= ~EF_SH_MACH_MASK;
elf_elfheader (stdoutput)->e_flags |= val;
shift = 0;
switch (fixP->fx_r_type)
{
+ case BFD_RELOC_SH_IMM3:
+ max = 0x7;
+ * buf = (* buf & 0xf8) | (val & 0x7);
+ break;
+ case BFD_RELOC_SH_IMM3U:
+ max = 0x7;
+ * buf = (* buf & 0x8f) | ((val & 0x7) << 4);
+ break;
+ case BFD_RELOC_SH_DISP12:
+ max = 0xfff;
+ buf[lowbyte] = val & 0xff;
+ buf[highbyte] |= (val >> 8) & 0x0f;
+ break;
+ case BFD_RELOC_SH_DISP12BY2:
+ max = 0xfff;
+ shift = 1;
+ buf[lowbyte] = (val >> 1) & 0xff;
+ buf[highbyte] |= (val >> 9) & 0x0f;
+ break;
+ case BFD_RELOC_SH_DISP12BY4:
+ max = 0xfff;
+ shift = 2;
+ buf[lowbyte] = (val >> 2) & 0xff;
+ buf[highbyte] |= (val >> 10) & 0x0f;
+ break;
+ case BFD_RELOC_SH_DISP12BY8:
+ max = 0xfff;
+ shift = 3;
+ buf[lowbyte] = (val >> 3) & 0xff;
+ buf[highbyte] |= (val >> 11) & 0x0f;
+ break;
+ case BFD_RELOC_SH_DISP20:
+ if (! target_big_endian)
+ abort();
+ max = 0x7ffff;
+ min = -0x80000;
+ buf[1] = (buf[1] & 0x0f) | ((val >> 12) & 0xf0);
+ buf[2] = (val >> 8) & 0xff;
+ buf[3] = val & 0xff;
+ break;
+ case BFD_RELOC_SH_DISP20BY8:
+ if (!target_big_endian)
+ abort();
+ max = 0x7ffff;
+ min = -0x80000;
+ shift = 8;
+ buf[1] = (buf[1] & 0x0f) | ((val >> 20) & 0xf0);
+ buf[2] = (val >> 16) & 0xff;
+ buf[3] = (val >> 8) & 0xff;
+ break;
+
case BFD_RELOC_SH_IMM4:
max = 0xf;
*buf = (*buf & 0xf0) | (val & 0xf);
return 1;
}
-#endif
void
sh_cfi_frame_initial_instructions (void)
}
return regnum;
}
+#endif /* OBJ_ELF */
#endif /* BFD_ASSEMBLER */
projects / deliverable / binutils-gdb.git / blobdiff