/* tc-sparc.c -- Assemble for the SPARC
- Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
+ Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
+ 1999, 2000, 2001
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
You should have received a copy of the GNU General Public
License along with GAS; see the file COPYING. If not, write
to the Free Software Foundation, 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
+ Boston, MA 02111-1307, USA. */
#include <stdio.h>
#include <ctype.h>
#ifdef OBJ_ELF
#include "elf/sparc.h"
+#include "dwarf2dbg.h"
#endif
static struct sparc_arch *lookup_arch PARAMS ((char *));
{"uaword", s_uacons, 4},
{"uaxword", s_uacons, 8},
#ifdef OBJ_ELF
+ {"file", dwarf2_directive_file, 0},
+ {"loc", dwarf2_directive_loc, 0},
/* These are specific to sparc/svr4. */
{"2byte", s_uacons, 2},
{"4byte", s_uacons, 4},
changed in read.c. Ideally it shouldn't have to know about it at all,
but nothing is ideal around here. */
-#define isoctal(c) ((unsigned)((c) - '0') < '8')
+#define isoctal(c) ((unsigned) ((c) - '0') < '8')
struct sparc_it
{
and file formats. */
enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
- v8plusa, v9, v9a, v9_64};
+ v8plusa, v9, v9a, v9b, v9_64};
static struct sparc_arch {
char *name;
{ "sparc86x", "sparclite", sparc86x, 32, 1 },
{ "v8plus", "v9", v9, 0, 1 },
{ "v8plusa", "v9a", v9, 0, 1 },
+ { "v8plusb", "v9b", v9, 0, 1 },
{ "v9", "v9", v9, 0, 1 },
{ "v9a", "v9a", v9, 0, 1 },
+ { "v9b", "v9b", v9, 0, 1 },
/* This exists to allow configure.in/Makefile.in to pass one
value to specify both the default machine and default word size. */
{ "v9-64", "v9", v9, 64, 0 },
return "a.out-sunos-big";
else if (default_arch_type == sparc86x && target_little_endian_data)
return "a.out-sunos-big";
- else return "a.out-sparc-little";
+ else
+ return "a.out-sparc-little";
#else
return "a.out-sunos-big";
#endif
*
* -Av6, -Av7, -Av8, -Asparclite, -Asparclet
* Standard 32 bit architectures.
- * -Av8plus, -Av8plusa
- * Sparc64 in a 32 bit world.
- * -Av9, -Av9a
+ * -Av9, -Av9a, -Av9b
* Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
* This used to only mean 64 bits, but properly specifying it
* complicated gcc's ASM_SPECs, so now opcode selection is
* specified orthogonally to word size (except when specifying
* the default, but that is an internal implementation detail).
- * -xarch=v8plus, -xarch=v8plusa
- * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
+ * -Av8plus, -Av8plusa, -Av8plusb
+ * Same as -Av9{,a,b}.
+ * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
+ * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
+ * assembler.
+ * -xarch=v9, -xarch=v9a, -xarch=v9b
+ * Same as -Av9{,a,b} -64, for compatibility with Sun's
+ * assembler.
*
* Select the architecture and possibly the file format.
* Instructions or features not supported by the selected
* The default is to start at v6, and bump the architecture up
* whenever an instruction is seen at a higher level. In 32 bit
* environments, v9 is not bumped up to, the user must pass
- * -Av8plus{,a}.
+ * -Av8plus{,a,b}.
*
* If -bump is specified, a warning is printing when bumping to
* higher levels.
break;
case OPTION_XARCH:
- /* This is for compatibility with Sun's assembler. */
- if (strcmp (arg, "v8plus") != 0
- && strcmp (arg, "v8plusa") != 0)
- {
- as_bad (_("invalid architecture -xarch=%s"), arg);
- return 0;
- }
+#ifdef OBJ_ELF
+ if (strncmp (arg, "v9", 2) != 0)
+ md_parse_option (OPTION_32, NULL);
+ else
+ md_parse_option (OPTION_64, NULL);
+#endif
/* Fall through. */
case 'A':
if (sa == NULL
|| ! sa->user_option_p)
{
- as_bad (_("invalid architecture -A%s"), arg);
+ if (c == OPTION_XARCH)
+ as_bad (_("invalid architecture -xarch=%s"), arg);
+ else
+ as_bad (_("invalid architecture -A%s"), arg);
return 0;
}
FILE *stream;
{
const struct sparc_arch *arch;
+ int column;
/* We don't get a chance to initialize anything before we're called,
so handle that now. */
init_default_arch ();
fprintf (stream, _("SPARC options:\n"));
+ column = 0;
for (arch = &sparc_arch_table[0]; arch->name; arch++)
{
+ if (!arch->user_option_p)
+ continue;
if (arch != &sparc_arch_table[0])
fprintf (stream, " | ");
- if (arch->user_option_p)
- fprintf (stream, "-A%s", arch->name);
+ if (column + strlen (arch->name) > 70)
+ {
+ column = 0;
+ fputc ('\n', stream);
+ }
+ column += 5 + 2 + strlen (arch->name);
+ fprintf (stream, "-A%s", arch->name);
}
- fprintf (stream, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
- fprintf (stream, _("\
+ for (arch = &sparc_arch_table[0]; arch->name; arch++)
+ {
+ if (!arch->user_option_p)
+ continue;
+ fprintf (stream, " | ");
+ if (column + strlen (arch->name) > 65)
+ {
+ column = 0;
+ fputc ('\n', stream);
+ }
+ column += 5 + 7 + strlen (arch->name);
+ fprintf (stream, "-xarch=%s", arch->name);
+ }
+ fprintf (stream, _("\n\
specify variant of SPARC architecture\n\
-bump warn when assembler switches architectures\n\
-sparc ignored\n\
/* sparc64 priviledged registers. */
struct priv_reg_entry
- {
- char *name;
- int regnum;
- };
+{
+ char *name;
+ int regnum;
+};
struct priv_reg_entry priv_reg_table[] =
{
struct priv_reg_entry v9a_asr_table[] =
{
{"tick_cmpr", 23},
+ {"sys_tick_cmpr", 25},
+ {"sys_tick", 24},
{"softint", 22},
{"set_softint", 20},
{"pic", 17},
for (i = 0; native_op_table[i].name; i++)
{
const struct sparc_opcode *insn;
- char *name = sparc_arch_size == 32 ? native_op_table[i].name32 :
- native_op_table[i].name64;
+ char *name = ((sparc_arch_size == 32)
+ ? native_op_table[i].name32
+ : native_op_table[i].name64);
insn = (struct sparc_opcode *) hash_find (op_hash, name);
if (insn == NULL)
{
void
sparc_md_end ()
{
+ unsigned long mach = bfd_mach_sparc;
+
if (sparc_arch_size == 64)
- {
- if (current_architecture == SPARC_OPCODE_ARCH_V9A)
- bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
- else
- bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
- }
+ switch (current_architecture)
+ {
+ case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
+ case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
+ default: mach = bfd_mach_sparc_v9; break;
+ }
else
- {
- if (current_architecture == SPARC_OPCODE_ARCH_V9)
- bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
- else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
- bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
- else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
- bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
- else if (default_arch_type == sparc86x && target_little_endian_data)
- bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclite_le);
- else
- {
- /* The sparclite is treated like a normal sparc. Perhaps it
- shouldn't be but for now it is (since that's the way it's
- always been treated). */
- bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
- }
- }
+ switch (current_architecture)
+ {
+ case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
+ case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
+ case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
+ case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
+ /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
+ be but for now it is (since that's the way it's always been
+ treated). */
+ default: break;
+ }
+ bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
}
\f
/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
{
the_insn.opcode = (SETHI_INSN | RD (rd)
| ((the_insn.exp.X_add_number >> 10)
- & (the_insn.exp.X_op == O_constant ? 0x3fffff : 0)));
+ & (the_insn.exp.X_op == O_constant
+ ? 0x3fffff : 0)));
the_insn.reloc = (the_insn.exp.X_op != O_constant
- ? BFD_RELOC_HI22
- : BFD_RELOC_NONE);
+ ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
output_insn (insn, &the_insn);
need_hi22_p = 1;
}
the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
| RD (rd) | IMMED
| (the_insn.exp.X_add_number
- & (the_insn.exp.X_op != O_constant ? 0 :
- need_hi22_p ? 0x3ff : 0x1fff)));
+ & (the_insn.exp.X_op != O_constant
+ ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
the_insn.reloc = (the_insn.exp.X_op != O_constant
- ? BFD_RELOC_LO10
- : BFD_RELOC_NONE);
+ ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
output_insn (insn, &the_insn);
}
}
return;
}
need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
- lower32 = 0; upper32 = 0;
+ lower32 = 0;
+ upper32 = 0;
}
else
{
{
the_insn.opcode = (SETHI_INSN | RD (dstreg)
| (((need_xor10_p ? ~lower32 : lower32)
- >> 10) & 0x3fffff));
+ >> 10) & 0x3fffff));
the_insn.reloc = (the_insn.exp.X_op != O_constant
? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
output_insn (insn, &the_insn);
goto error;
}
kmask |= mask;
- while (*s == ' ') { ++s; continue; }
+ while (*s == ' ')
+ ++s;
if (*s == '|' || *s == '+')
++s;
- while (*s == ' ') { ++s; continue; }
+ while (*s == ' ')
+ ++s;
}
}
else
continue;
}
+ case '3':
+ {
+ int smask = 0;
+
+ if (! parse_const_expr_arg (&s, &smask))
+ {
+ error_message = _(": invalid siam mode expression");
+ goto error;
+ }
+ if (smask < 0 || smask > 7)
+ {
+ error_message = _(": invalid siam mode number");
+ goto error;
+ }
+ opcode |= smask;
+ continue;
+ }
+
case '*':
{
int fcn = 0;
case '_':
case '/':
- /* Parse a v9a ancillary state register. */
+ /* Parse a v9a/v9b ancillary state register. */
if (*s == '%')
{
struct priv_reg_entry *p = v9a_asr_table;
}
if (p->name[0] != s[0])
{
- error_message = _(": unrecognizable v9a ancillary state register");
+ error_message = _(": unrecognizable v9a or v9b ancillary state register");
goto error;
}
if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
error_message = _(": rd on write only ancillary state register");
goto error;
}
+ if (p->regnum >= 24
+ && (insn->architecture
+ & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
+ {
+ /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
+ error_message = _(": unrecognizable v9a ancillary state register");
+ goto error;
+ }
if (*args == '/')
opcode |= (p->regnum << 14);
else
}
else
{
- error_message = _(": unrecognizable v9a ancillary state register");
+ error_message = _(": unrecognizable v9a or v9b ancillary state register");
goto error;
}
else
{
break;
- } /* if not an 'f' register. */
+ } /* if not an 'f' register. */
switch (*args)
{
case 'J':
opcode |= RD (mask);
continue;
- } /* pack it in. */
+ } /* Pack it in. */
know (0);
break;
- } /* float arg */
+ } /* float arg */
case 'F':
if (strncmp (s, "%fsr", 4) == 0)
}
break;
- case '0': /* 64 bit immediate (set, setsw, setx insn) */
- the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
+ case '0': /* 64 bit immediate (set, setsw, setx insn) */
+ the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
goto immediate;
- case 'l': /* 22 bit PC relative immediate */
+ case 'l': /* 22 bit PC relative immediate */
the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
the_insn.pcrel = 1;
goto immediate;
- case 'L': /* 30 bit immediate */
+ case 'L': /* 30 bit immediate */
the_insn.reloc = BFD_RELOC_32_PCREL_S2;
the_insn.pcrel = 1;
goto immediate;
case 'h':
- case 'n': /* 22 bit immediate */
+ case 'n': /* 22 bit immediate */
the_insn.reloc = BFD_RELOC_SPARC22;
goto immediate;
- case 'i': /* 13 bit immediate */
+ case 'i': /* 13 bit immediate */
the_insn.reloc = BFD_RELOC_SPARC13;
/* fallthrough */
{ "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
{ "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
{ "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
- { NULL }
+ { NULL, 0, 0, 0, 0 }
};
const struct ops *o;
break;
case BFD_RELOC_SPARC_HIX22:
- val = ~ val;
+ val = ~val;
val = (val >> 10) & 0x3fffff;
break;
if (v9_arg_p)
{
- needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9)
- | (1 << SPARC_OPCODE_ARCH_V9A));
- needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
+ needed_arch_mask &=
+ ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
+ if (! needed_arch_mask)
+ needed_arch_mask =
+ SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
}
if (needed_arch_mask
last_insn = insn;
last_opcode = the_insn->opcode;
+
+#ifdef OBJ_ELF
+ dwarf2_emit_insn (4);
+#endif
}
\f
/* This is identical to the md_atof in m68k.c. I think this is right,
{
for (i = 0; i < prec; i++)
{
- md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
+ md_number_to_chars (litP, (valueT) words[i],
+ sizeof (LITTLENUM_TYPE));
litP += sizeof (LITTLENUM_TYPE);
}
}
{
for (i = prec - 1; i >= 0; i--)
{
- md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
+ md_number_to_chars (litP, (valueT) words[i],
+ sizeof (LITTLENUM_TYPE));
litP += sizeof (LITTLENUM_TYPE);
}
}
}
\f
/* Apply a fixS to the frags, now that we know the value it ought to
- hold. */
+ hold. */
int
md_apply_fix3 (fixP, value, segment)
/* If this is a data relocation, just output VAL. */
- if (fixP->fx_r_type == BFD_RELOC_16)
+ if (fixP->fx_r_type == BFD_RELOC_16
+ || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
{
md_number_to_chars (buf, val, 2);
}
else if (fixP->fx_r_type == BFD_RELOC_32
+ || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
|| fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
{
md_number_to_chars (buf, val, 4);
}
- else if (fixP->fx_r_type == BFD_RELOC_64)
+ else if (fixP->fx_r_type == BFD_RELOC_64
+ || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
{
md_number_to_chars (buf, val, 8);
}
else
setter = bfd_getl32 ((unsigned char *) buf - 4);
if ((setter & (0xffffffff ^ RD (~0)))
- != (INSN_OR | RS1 (O7) | RS2 (G0)))
+ != (INSN_OR | RS1 (O7) | RS2 (G0)))
break;
/* The sequence was
or %o7, %g0, %rN
case BFD_RELOC_SPARC_HIX22:
if (!fixP->fx_addsy)
{
- val ^= ~ (offsetT) 0;
+ val ^= ~(offsetT) 0;
insn |= (val >> 10) & 0x3fffff;
}
break;
case BFD_RELOC_SPARC_LOX10:
case BFD_RELOC_SPARC_REV32:
case BFD_RELOC_SPARC_OLO10:
+ case BFD_RELOC_SPARC_UA16:
+ case BFD_RELOC_SPARC_UA32:
+ case BFD_RELOC_SPARC_UA64:
case BFD_RELOC_VTABLE_ENTRY:
case BFD_RELOC_VTABLE_INHERIT:
code = fixp->fx_r_type;
relocs[2] = NULL;
reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
- *reloc->sym_ptr_ptr = symbol_get_bfdsym (section_symbol (absolute_section));
+ *reloc->sym_ptr_ptr
+ = symbol_get_bfdsym (section_symbol (absolute_section));
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
reloc->addend = fixp->tc_fix_data;
symbolS *
md_undefined_symbol (name)
- char *name;
+ char *name ATTRIBUTE_UNUSED;
{
return 0;
}
valueT
md_section_align (segment, size)
- segT segment;
+ segT segment ATTRIBUTE_UNUSED;
valueT size;
{
#ifndef OBJ_ELF
static void
s_reserve (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
char *name;
char *p;
frag_align (align, 0, 0);
/* Detach from old frag. */
- if (S_GET_SEGMENT(symbolP) == bss_section)
+ if (S_GET_SEGMENT (symbolP) == bss_section)
symbol_get_frag (symbolP)->fr_symbol = NULL;
symbol_set_frag (symbolP, frag_now);
}
else
{
- as_warn("Ignoring attempt to re-define symbol %s",
- S_GET_NAME (symbolP));
+ as_warn ("Ignoring attempt to re-define symbol %s",
+ S_GET_NAME (symbolP));
} /* if not redefining. */
demand_empty_rest_of_line ();
static void
s_common (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
char *name;
char c;
static void
s_empty (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
/* The easy way to implement is to just forget about the last
instruction. */
static void
s_seg (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
static void
s_proc (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
while (!is_end_of_line[(unsigned char) *input_line_pointer])
{
/* Tell sparc_cons_align not to align this value. */
sparc_no_align_cons = 1;
cons (bytes);
+ sparc_no_align_cons = 0;
}
/* This handles the native word allocation pseudo-op .nword.
static void
s_ncons (bytes)
- int bytes;
+ int bytes ATTRIBUTE_UNUSED;
{
cons (sparc_arch_size == 32 ? 4 : 8);
}
static void
s_register (ignore)
- int ignore;
+ int ignore ATTRIBUTE_UNUSED;
{
char c;
int reg;
c = get_symbol_end ();
if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
- if (regname [0] == 'i')
+ if (regname[0] == 'i')
regname = NULL;
else
regname = "";
if (! enforce_aligned_data)
return;
+ /* Don't align if this is an unaligned pseudo-op. */
if (sparc_no_align_cons)
- {
- /* This is an unaligned pseudo-op. */
- sparc_no_align_cons = 0;
- return;
- }
+ return;
nalign = log2 (nbytes);
if (nalign == 0)
return;
}
- p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
+ p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
(symbolS *) NULL, (offsetT) nalign, (char *) NULL);
record_alignment (now_seg, nalign);
}
-/* This is where we do the unexpected alignment check.
- This is called from HANDLE_ALIGN in tc-sparc.h. */
+/* This is called from HANDLE_ALIGN in tc-sparc.h. */
void
sparc_handle_align (fragp)
fragS *fragp;
{
- if (fragp->fr_type == rs_align_code && !fragp->fr_subtype
- && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
- as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
- if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
+ int count, fix;
+ char *p;
+
+ count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
+
+ switch (fragp->fr_type)
{
- int count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
+ case rs_align_test:
+ if (count != 0)
+ as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
+ break;
- if (count >= 4
- && !(count & 3)
- && count <= 1024
- && !((long) (fragp->fr_literal + fragp->fr_fix) & 3))
- {
- unsigned *p = (unsigned *) (fragp->fr_literal + fragp->fr_fix);
- int i;
+ case rs_align_code:
+ p = fragp->fr_literal + fragp->fr_fix;
+ fix = 0;
- for (i = 0; i < count; i += 4, p++)
- if (INSN_BIG_ENDIAN)
- /* Emit nops. */
- number_to_chars_bigendian ((char *) p, 0x01000000, 4);
- else
- number_to_chars_littleendian ((char *) p, 0x10000000, 4);
+ if (count & 3)
+ {
+ fix = count & 3;
+ memset (p, 0, fix);
+ p += fix;
+ count -= fix;
+ }
- if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
- {
- char *waddr = &fragp->fr_literal[fragp->fr_fix];
- unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
- if (INSN_BIG_ENDIAN)
- number_to_chars_bigendian (waddr, wval, 4);
- else
- number_to_chars_littleendian (waddr, wval, 4);
- }
- fragp->fr_var = count;
+ if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
+ {
+ unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
+ if (INSN_BIG_ENDIAN)
+ number_to_chars_bigendian (p, wval, 4);
+ else
+ number_to_chars_littleendian (p, wval, 4);
+ p += 4;
+ count -= 4;
+ fix += 4;
}
+
+ if (INSN_BIG_ENDIAN)
+ number_to_chars_bigendian (p, 0x01000000, 4);
+ else
+ number_to_chars_littleendian (p, 0x01000000, 4);
+
+ fragp->fr_fix += fix;
+ fragp->fr_var = 4;
+ break;
+
+ default:
+ break;
}
}
elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
if (current_architecture == SPARC_OPCODE_ARCH_V9A)
elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
+ else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
+ elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
}
#endif
(nbytes == 2 ? BFD_RELOC_16 :
(nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
- if (target_little_endian_data && nbytes == 4
+ if (target_little_endian_data
+ && nbytes == 4
&& now_seg->flags & SEC_ALLOC)
r = BFD_RELOC_SPARC_REV32;
+
+ if (sparc_no_align_cons)
+ {
+ switch (nbytes)
+ {
+ case 2: r = BFD_RELOC_SPARC_UA16; break;
+ case 4: r = BFD_RELOC_SPARC_UA32; break;
+ case 8: r = BFD_RELOC_SPARC_UA64; break;
+ default: abort ();
+ }
+ }
+
fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
}
projects / deliverable / binutils-gdb.git / blobdiff