/* tc-sparc.c -- Assemble for the SPARC
- Copyright (C) 1989, 1990, 1991, 1992 Free Software Foundation, Inc.
+ Copyright (C) 1989, 90-95, 1996 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with GAS; see the file COPYING. If not, write to
- the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
+ You should have received a copy of the GNU General Public
+ License along with GAS; see the file COPYING. If not, write
+ to the Free Software Foundation, 59 Temple Place - Suite 330,
+ Boston, MA 02111-1307, USA. */
#include <stdio.h>
#include <ctype.h>
/* careful, this file includes data *declarations* */
#include "opcode/sparc.h"
-static void sparc_ip PARAMS ((char *));
+static void sparc_ip PARAMS ((char *, const struct sparc_opcode **));
-#ifdef sparcv9
-static enum sparc_architecture current_architecture = v9;
+/* Current architecture. We don't bump up unless necessary. */
+static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
+
+/* The maximum architecture level we can bump up to.
+ In a 32 bit environment, don't allow bumping up to v9 by default.
+ The native assembler works this way. The user is required to pass
+ an explicit argument before we'll create v9 object files. However, if
+ we don't see any v9 insns, a v9 object file is not created. */
+#ifdef SPARC_ARCH64
+static enum sparc_opcode_arch_val max_architecture = SPARC_OPCODE_ARCH_V9;
#else
-static enum sparc_architecture current_architecture = v6;
+/* ??? This should be V8, but sparclite support was added by making it the
+ default. GCC now passes -Asparclite, so maybe sometime in the future
+ we can set this to V8. */
+static enum sparc_opcode_arch_val max_architecture = SPARC_OPCODE_ARCH_SPARCLITE;
#endif
+
static int architecture_requested;
static int warn_on_bump;
+/* If warn_on_bump and the needed architecture is higher than this
+ architecture, issue a warning. */
+static enum sparc_opcode_arch_val warn_after_architecture;
+
+/* Non-zero if we are generating PIC code. */
+int sparc_pic_code;
+
+/* Non-zero if we should give an error when misaligned data is seen. */
+static int enforce_aligned_data;
+
extern int target_big_endian;
+/* V9 has big and little endian data, but instructions are always big endian.
+ The sparclet has bi-endian support but both data and insns have the same
+ endianness. Global `target_big_endian' is used for data. The following
+ macro is used for instructions. */
+#define INSN_BIG_ENDIAN (target_big_endian \
+ || SPARC_OPCODE_ARCH_V9_P (max_architecture))
+
/* handle of the OPCODE hash table */
static struct hash_control *op_hash;
static void s_proc PARAMS ((int));
static void s_reserve PARAMS ((int));
static void s_common PARAMS ((int));
+static void s_empty PARAMS ((int));
+static void s_uacons PARAMS ((int));
const pseudo_typeS md_pseudo_table[] =
{
{"align", s_align_bytes, 0}, /* Defaulting is invalid (0) */
{"common", s_common, 0},
+ {"empty", s_empty, 0},
{"global", s_globl, 0},
{"half", cons, 2},
{"optim", s_ignore, 0},
{"seg", s_seg, 0},
{"skip", s_space, 0},
{"word", cons, 4},
-#ifndef NO_V9
{"xword", cons, 8},
-#ifdef OBJ_ELF
- {"uaxword", cons, 8},
-#endif
-#endif
+ {"uahalf", s_uacons, 2},
+ {"uaword", s_uacons, 4},
+ {"uaxword", s_uacons, 8},
#ifdef OBJ_ELF
/* these are specific to sparc/svr4 */
{"pushsection", obj_elf_section, 0},
{"popsection", obj_elf_previous, 0},
- {"uaword", cons, 4},
- {"uahalf", cons, 2},
+ {"2byte", s_uacons, 2},
+ {"4byte", s_uacons, 4},
+ {"8byte", s_uacons, 8},
#endif
{NULL, 0, 0},
};
struct sparc_it the_insn, set_insn;
+/* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
+
static INLINE int
in_signed_range (val, max)
bfd_signed_vma val, max;
return 1;
}
+/* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
+ (e.g. -15 to +31). */
+
+static INLINE int
+in_bitfield_range (val, max)
+ bfd_signed_vma val, max;
+{
+ if (max <= 0)
+ abort ();
+ if (val > max)
+ return 0;
+ if (val < ~(max >> 1))
+ return 0;
+ return 1;
+}
+
+static int
+sparc_ffs (mask)
+ unsigned int mask;
+{
+ int i;
+
+ if (mask == 0)
+ return -1;
+
+ for (i = 0; (mask & 1) == 0; ++i)
+ mask >>= 1;
+ return i;
+}
+
+/* Implement big shift right. */
+static bfd_vma
+BSR (val, amount)
+ bfd_vma val;
+ int amount;
+{
+ if (sizeof (bfd_vma) <= 4 && amount >= 32)
+ as_fatal ("Support for 64-bit arithmetic not compiled in.");
+ return val >> amount;
+}
+
#if 0
static void print_insn PARAMS ((struct sparc_it *insn));
#endif
* 4 bytes.
*/
#define SPECIAL_CASE_SET 1
-#define SPECIAL_CASE_FDIV 2
+#define SPECIAL_CASE_SETSW 2
+#define SPECIAL_CASE_SETX 3
+/* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
+#define SPECIAL_CASE_FDIV 4
+
+/* Bit masks of various insns. */
+#define NOP_INSN 0x01000000
+#define OR_INSN 0x80100000
+#define FMOVS_INSN 0x81A00020
+#define SETHI_INSN 0x01000000
+#define SLLX_INSN 0x81281000
+#define SRA_INSN 0x81380000
+
+/* The last instruction to be assembled. */
+static const struct sparc_opcode *last_insn;
/*
* sort of like s_lcomm
else
align = 0;
- if ((S_GET_SEGMENT (symbolP) == bss_section
- || !S_IS_DEFINED (symbolP))
+ if (!S_IS_DEFINED (symbolP)
#ifdef OBJ_AOUT
&& S_GET_OTHER (symbolP) == 0
&& S_GET_DESC (symbolP) == 0
}
else
{
- as_warn("Ignoring attempt to re-define symbol %s.", name);
+ as_warn("Ignoring attempt to re-define symbol %s",
+ S_GET_NAME (symbolP));
} /* if not redefining */
demand_empty_rest_of_line ();
char *p;
int align;
- allocate_bss:
old_sec = now_seg;
old_subsec = now_subseg;
align = temp;
}
}
+/* Handle the .empty pseudo-op. This supresses the warnings about
+ invalid delay slot usage. */
+
+static void
+s_empty (ignore)
+ int ignore;
+{
+ /* The easy way to implement is to just forget about the last
+ instruction. */
+ last_insn = NULL;
+}
+
static void
s_seg (ignore)
int ignore;
++input_line_pointer;
}
-#ifndef NO_V9
+/* This static variable is set by s_uacons to tell sparc_cons_align
+ that the expession does not need to be aligned. */
+
+static int sparc_no_align_cons = 0;
+
+/* This handles the unaligned space allocation pseudo-ops, such as
+ .uaword. .uaword is just like .word, but the value does not need
+ to be aligned. */
+
+static void
+s_uacons (bytes)
+ int bytes;
+{
+ /* Tell sparc_cons_align not to align this value. */
+ sparc_no_align_cons = 1;
+ cons (bytes);
+}
+
+/* If the --enforce-aligned-data option is used, we require .word,
+ et. al., to be aligned correctly. We do it by setting up an
+ rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
+ no unexpected alignment was introduced.
+
+ The SunOS and Solaris native assemblers enforce aligned data by
+ default. We don't want to do that, because gcc can deliberately
+ generate misaligned data if the packed attribute is used. Instead,
+ we permit misaligned data by default, and permit the user to set an
+ option to check for it. */
+
+void
+sparc_cons_align (nbytes)
+ int nbytes;
+{
+ int nalign;
+ char *p;
+
+ /* Only do this if we are enforcing aligned data. */
+ if (! enforce_aligned_data)
+ return;
+
+ if (sparc_no_align_cons)
+ {
+ /* This is an unaligned pseudo-op. */
+ sparc_no_align_cons = 0;
+ return;
+ }
+
+ nalign = 0;
+ while ((nbytes & 1) == 0)
+ {
+ ++nalign;
+ nbytes >>= 1;
+ }
+
+ if (nalign == 0)
+ return;
+
+ if (now_seg == absolute_section)
+ {
+ if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
+ as_bad ("misaligned data");
+ return;
+ }
+
+ p = frag_var (rs_align_code, 1, 1, (relax_substateT) 0,
+ (symbolS *) NULL, (long) nalign, (char *) NULL);
+
+ record_alignment (now_seg, nalign);
+}
+
+/* This is where we do the unexpected alignment check. */
+
+void
+sparc_handle_align (fragp)
+ fragS *fragp;
+{
+ if (fragp->fr_type == rs_align_code
+ && fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix != 0)
+ as_bad_where (fragp->fr_file, fragp->fr_line, "misaligned data");
+}
+
+/* sparc64 priviledged registers */
struct priv_reg_entry
{
{"", -1}, /* end marker */
};
-struct membar_masks
-{
- char *name;
- unsigned int len;
- unsigned int mask;
-};
-
-#define MEMBAR_MASKS_SIZE 7
-
-static const struct membar_masks membar_masks[MEMBAR_MASKS_SIZE] =
-{
- {"Sync", 4, 0x40},
- {"MemIssue", 8, 0x20},
- {"Lookaside", 9, 0x10},
- {"StoreStore", 10, 0x08},
- {"LoadStore", 9, 0x04},
- {"StoreLoad", 9, 0x02},
- {"LoadLoad", 8, 0x01},
-};
-
static int
cmp_reg_entry (p, q)
struct priv_reg_entry *p, *q;
return strcmp (q->name, p->name);
}
-#endif
-
/* This function is called once, at assembler startup time. It should
set up all the tables, etc. that the MD part of the assembler will need. */
+
void
md_begin ()
{
op_hash = hash_new ();
- while (i < NUMOPCODES)
+ while (i < sparc_num_opcodes)
{
const char *name = sparc_opcodes[i].name;
retval = hash_insert (op_hash, name, &sparc_opcodes[i]);
}
++i;
}
- while (i < NUMOPCODES
+ while (i < sparc_num_opcodes
&& !strcmp (sparc_opcodes[i].name, name));
}
for (i = 'A'; i <= 'F'; ++i)
toHex[i] = i + 10 - 'A';
-#ifndef NO_V9
qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
sizeof (priv_reg_table[0]), cmp_reg_entry);
-#endif
- target_big_endian = 1;
+ /* If -bump, record the architecture level at which we start issuing
+ warnings. The behaviour is different depending upon whether an
+ architecture was explicitly specified. If it wasn't, we issue warnings
+ for all upwards bumps. If it was, we don't start issuing warnings until
+ we need to bump beyond the requested architecture or when we bump between
+ conflicting architectures. */
+
+ if (warn_on_bump
+ && architecture_requested)
+ {
+ /* `max_architecture' records the requested architecture.
+ Issue warnings if we go above it. */
+ warn_after_architecture = max_architecture;
+
+ /* Find the highest architecture level that doesn't conflict with
+ the requested one. */
+ for (max_architecture = SPARC_OPCODE_ARCH_MAX;
+ max_architecture > warn_after_architecture;
+ --max_architecture)
+ if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
+ warn_after_architecture))
+ break;
+ }
}
+/* Called after all assembly has been done. */
+
void
-md_assemble (str)
- char *str;
+sparc_md_end ()
{
- char *toP;
- int rsd;
-
- know (str);
- sparc_ip (str);
-
- /* See if "set" operand is absolute and small; skip sethi if so. */
- if (special_case == SPECIAL_CASE_SET
- && the_insn.exp.X_op == O_constant)
+#ifdef SPARC_ARCH64
+ if (current_architecture == SPARC_OPCODE_ARCH_V9A)
+ bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9a);
+ else
+ bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v9);
+#else
+ if (current_architecture == SPARC_OPCODE_ARCH_V9)
+ bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plus);
+ else if (current_architecture == SPARC_OPCODE_ARCH_V9A)
+ bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_v8plusa);
+ else if (current_architecture == SPARC_OPCODE_ARCH_SPARCLET)
+ bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc_sparclet);
+ else
{
- if (the_insn.exp.X_add_number >= -(1 << 12)
- && the_insn.exp.X_add_number < (1 << 12))
- {
- the_insn.opcode = 0x80102000 /* or %g0,imm,... */
- | (the_insn.opcode & 0x3E000000) /* dest reg */
- | (the_insn.exp.X_add_number & 0x1FFF); /* imm */
- special_case = 0; /* No longer special */
- the_insn.reloc = BFD_RELOC_NONE; /* No longer relocated */
- }
+ /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
+ be but for now it is (since that's the way it's always been
+ treated). */
+ bfd_set_arch_mach (stdoutput, bfd_arch_sparc, bfd_mach_sparc);
}
+#endif
+}
+
+/* Utility to output one insn. */
+
+static void
+output_insn (insn, the_insn)
+ const struct sparc_opcode *insn;
+ struct sparc_it *the_insn;
+{
+ char *toP = frag_more (4);
- toP = frag_more (4);
/* put out the opcode */
- md_number_to_chars (toP, (valueT) the_insn.opcode, 4);
+ if (INSN_BIG_ENDIAN)
+ number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
+ else
+ number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
/* put out the symbol-dependent stuff */
- if (the_insn.reloc != BFD_RELOC_NONE)
+ if (the_insn->reloc != BFD_RELOC_NONE)
{
fix_new_exp (frag_now, /* which frag */
(toP - frag_now->fr_literal), /* where */
4, /* size */
- &the_insn.exp,
- the_insn.pcrel,
- the_insn.reloc);
+ &the_insn->exp,
+ the_insn->pcrel,
+ the_insn->reloc);
+ }
+
+ last_insn = insn;
+}
+
+void
+md_assemble (str)
+ char *str;
+{
+ const struct sparc_opcode *insn;
+
+ know (str);
+ special_case = 0;
+ sparc_ip (str, &insn);
+
+ /* We warn about attempts to put a floating point branch in a delay slot. */
+ if (insn != NULL
+ && last_insn != NULL
+ && (insn->flags & F_FBR) != 0
+ && (last_insn->flags & F_DELAYED) != 0)
+ as_warn ("FP branch in delay slot");
+
+ /* SPARC before v9 requires a nop instruction between a floating
+ point instruction and a floating point branch. We insert one
+ automatically, with a warning. */
+ if (max_architecture < SPARC_OPCODE_ARCH_V9
+ && insn != NULL
+ && last_insn != NULL
+ && (insn->flags & F_FBR) != 0
+ && (last_insn->flags & F_FLOAT) != 0)
+ {
+ struct sparc_it nop_insn;
+
+ nop_insn.opcode = NOP_INSN;
+ nop_insn.reloc = BFD_RELOC_NONE;
+ output_insn (insn, &nop_insn);
+ as_warn ("FP branch preceded by FP instruction; NOP inserted");
}
switch (special_case)
{
+ case 0:
+ /* normal insn */
+ output_insn (insn, &the_insn);
+ break;
+
case SPECIAL_CASE_SET:
- special_case = 0;
- assert (the_insn.reloc == BFD_RELOC_HI22);
- /* See if "set" operand has no low-order bits; skip OR if so. */
- if (the_insn.exp.X_op == O_constant
- && ((the_insn.exp.X_add_number & 0x3FF) == 0))
- return;
- toP = frag_more (4);
- rsd = (the_insn.opcode >> 25) & 0x1f;
- the_insn.opcode = 0x80102000 | (rsd << 25) | (rsd << 14);
- md_number_to_chars (toP, (valueT) the_insn.opcode, 4);
- fix_new_exp (frag_now, /* which frag */
- (toP - frag_now->fr_literal), /* where */
- 4, /* size */
- &the_insn.exp,
- the_insn.pcrel,
- BFD_RELOC_LO10);
- return;
+ {
+ int need_hi22_p = 0;
- case SPECIAL_CASE_FDIV:
- /* According to information leaked from Sun, the "fdiv" instructions
- on early SPARC machines would produce incorrect results sometimes.
- The workaround is to add an fmovs of the destination register to
- itself just after the instruction. This was true on machines
- with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
- special_case = 0;
- assert (the_insn.reloc == BFD_RELOC_NONE);
- toP = frag_more (4);
- rsd = (the_insn.opcode >> 25) & 0x1f;
- the_insn.opcode = 0x81A00020 | (rsd << 25) | rsd; /* fmovs dest,dest */
- md_number_to_chars (toP, (valueT) the_insn.opcode, 4);
- return;
+ /* "set" is not defined for negative numbers in v9: it doesn't yield
+ what you expect it to. */
+ if (SPARC_OPCODE_ARCH_V9_P (max_architecture)
+ && the_insn.exp.X_op == O_constant)
+ {
+ if (the_insn.exp.X_add_number < 0)
+ as_warn ("set: used with negative number");
+ else if (the_insn.exp.X_add_number > 0xffffffff)
+ as_warn ("set: number larger than 4294967295");
+ }
- case 0:
- return;
+ /* See if operand is absolute and small; skip sethi if so. */
+ if (the_insn.exp.X_op != O_constant
+ || the_insn.exp.X_add_number >= (1 << 12)
+ || the_insn.exp.X_add_number < -(1 << 12))
+ {
+ output_insn (insn, &the_insn);
+ need_hi22_p = 1;
+ }
+ /* See if operand has no low-order bits; skip OR if so. */
+ if (the_insn.exp.X_op != O_constant
+ || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
+ || ! need_hi22_p)
+ {
+ int rd = (the_insn.opcode & RD (~0)) >> 25;
+ the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
+ | RD (rd)
+ | IMMED
+ | (the_insn.exp.X_add_number
+ & (need_hi22_p ? 0x3ff : 0x1fff)));
+ the_insn.reloc = (the_insn.exp.X_op != O_constant
+ ? BFD_RELOC_LO10
+ : BFD_RELOC_NONE);
+ output_insn (insn, &the_insn);
+ }
+ break;
+ }
+
+ case SPECIAL_CASE_SETSW:
+ {
+ /* FIXME: Not finished. */
+ break;
+ }
+
+ case SPECIAL_CASE_SETX:
+ {
+#define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
+ int upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
+ int lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
+#undef SIGNEXT32
+ int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
+ int dstreg = (the_insn.opcode & RD (~0)) >> 25;
+ /* Output directly to dst reg if lower 32 bits are all zero. */
+ int upper_dstreg = (the_insn.exp.X_op == O_constant
+ && lower32 == 0) ? dstreg : tmpreg;
+ int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
+
+ /* The tmp reg should not be the dst reg. */
+ if (tmpreg == dstreg)
+ as_warn ("setx: temporary register same as destination register");
+
+ /* Reset X_add_number, we've extracted it as upper32/lower32.
+ Otherwise fixup_segment will complain about not being able to
+ write an 8 byte number in a 4 byte field. */
+ the_insn.exp.X_add_number = 0;
+
+ /* ??? Obviously there are other optimizations we can do
+ (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
+ doing some of these. Later. If you do change things, try to
+ change all of this to be table driven as well. */
+
+ /* What to output depends on the number if it's constant.
+ Compute that first, then output what we've decided upon. */
+ if (the_insn.exp.X_op != O_constant)
+ need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
+ else
+ {
+ /* Only need hh22 if `or' insn can't handle constant. */
+ if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
+ need_hh22_p = 1;
+
+ /* Does bottom part (after sethi) have bits? */
+ if ((need_hh22_p && (upper32 & 0x3ff) != 0)
+ /* No hh22, but does upper32 still have bits we can't set
+ from lower32? */
+ || (! need_hh22_p
+ && upper32 != 0
+ && (upper32 != -1 || lower32 >= 0)))
+ need_hm10_p = 1;
+
+ /* If the lower half is all zero, we build the upper half directly
+ into the dst reg. */
+ if (lower32 != 0
+ /* Need lower half if number is zero. */
+ || (! need_hh22_p && ! need_hm10_p))
+ {
+ /* No need for sethi if `or' insn can handle constant. */
+ if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
+ /* Note that we can't use a negative constant in the `or'
+ insn unless the upper 32 bits are all ones. */
+ || (lower32 < 0 && upper32 != -1))
+ need_hi22_p = 1;
+
+ /* Does bottom part (after sethi) have bits? */
+ if ((need_hi22_p && (lower32 & 0x3ff) != 0)
+ /* No sethi. */
+ || (! need_hi22_p && (lower32 & 0x1fff) != 0)
+ /* Need `or' if we didn't set anything else. */
+ || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
+ need_lo10_p = 1;
+ }
+ }
+
+ if (need_hh22_p)
+ {
+ the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
+ | ((upper32 >> 10) & 0x3fffff));
+ the_insn.reloc = (the_insn.exp.X_op != O_constant
+ ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
+ output_insn (insn, &the_insn);
+ }
+
+ if (need_hm10_p)
+ {
+ the_insn.opcode = (OR_INSN
+ | (need_hh22_p ? RS1 (upper_dstreg) : 0)
+ | RD (upper_dstreg)
+ | IMMED
+ | (upper32
+ & (need_hh22_p ? 0x3ff : 0x1fff)));
+ the_insn.reloc = (the_insn.exp.X_op != O_constant
+ ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
+ output_insn (insn, &the_insn);
+ }
+
+ if (need_hi22_p)
+ {
+ the_insn.opcode = (SETHI_INSN | RD (dstreg)
+ | ((lower32 >> 10) & 0x3fffff));
+ the_insn.reloc = BFD_RELOC_HI22;
+ output_insn (insn, &the_insn);
+ }
+
+ if (need_lo10_p)
+ {
+ /* FIXME: One nice optimization to do here is to OR the low part
+ with the highpart if hi22 isn't needed and the low part is
+ positive. */
+ the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
+ | RD (dstreg)
+ | IMMED
+ | (lower32
+ & (need_hi22_p ? 0x3ff : 0x1fff)));
+ the_insn.reloc = BFD_RELOC_LO10;
+ output_insn (insn, &the_insn);
+ }
+
+ /* If we needed to build the upper part, shift it into place. */
+ if (need_hh22_p || need_hm10_p)
+ {
+ the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
+ | IMMED | 32);
+ the_insn.reloc = BFD_RELOC_NONE;
+ output_insn (insn, &the_insn);
+ }
+
+ /* If we needed to build both upper and lower parts, OR them together. */
+ if ((need_hh22_p || need_hm10_p)
+ && (need_hi22_p || need_lo10_p))
+ {
+ the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
+ | RD (dstreg));
+ the_insn.reloc = BFD_RELOC_NONE;
+ output_insn (insn, &the_insn);
+ }
+ /* We didn't need both regs, but we may have to sign extend lower32. */
+ else if (need_hi22_p && upper32 == -1)
+ {
+ the_insn.opcode = (SRA_INSN | RS1 (dstreg) | RD (dstreg)
+ | IMMED | 0);
+ the_insn.reloc = BFD_RELOC_NONE;
+ output_insn (insn, &the_insn);
+ }
+ break;
+ }
+
+ case SPECIAL_CASE_FDIV:
+ {
+ int rd = (the_insn.opcode >> 25) & 0x1f;
+
+ output_insn (insn, &the_insn);
+
+ /* According to information leaked from Sun, the "fdiv" instructions
+ on early SPARC machines would produce incorrect results sometimes.
+ The workaround is to add an fmovs of the destination register to
+ itself just after the instruction. This was true on machines
+ with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
+ assert (the_insn.reloc == BFD_RELOC_NONE);
+ the_insn.opcode = FMOVS_INSN | rd | RD (rd);
+ output_insn (insn, &the_insn);
+ break;
+ }
default:
- as_fatal ("failed sanity check.");
+ as_fatal ("failed special case insn sanity check");
}
}
-/* Implement big shift right. */
-static bfd_vma
-BSR (val, amount)
- bfd_vma val;
- int amount;
+/* Parse an argument that can be expressed as a keyword.
+ (eg: #StoreStore or %ccfr).
+ The result is a boolean indicating success.
+ If successful, INPUT_POINTER is updated. */
+
+static int
+parse_keyword_arg (lookup_fn, input_pointerP, valueP)
+ int (*lookup_fn) ();
+ char **input_pointerP;
+ int *valueP;
{
- if (sizeof (bfd_vma) <= 4 && amount >= 32)
- as_fatal ("Support for 64-bit arithmetic not compiled in.");
- return val >> amount;
+ int value;
+ char c, *p, *q;
+
+ p = *input_pointerP;
+ for (q = p + (*p == '#' || *p == '%'); isalpha (*q) || *q == '_'; ++q)
+ continue;
+ c = *q;
+ *q = 0;
+ value = (*lookup_fn) (p);
+ *q = c;
+ if (value == -1)
+ return 0;
+ *valueP = value;
+ *input_pointerP = q;
+ return 1;
+}
+
+/* Parse an argument that is a constant expression.
+ The result is a boolean indicating success. */
+
+static int
+parse_const_expr_arg (input_pointerP, valueP)
+ char **input_pointerP;
+ int *valueP;
+{
+ char *save = input_line_pointer;
+ expressionS exp;
+
+ input_line_pointer = *input_pointerP;
+ /* The next expression may be something other than a constant
+ (say if we're not processing the right variant of the insn).
+ Don't call expression unless we're sure it will succeed as it will
+ signal an error (which we want to defer until later). */
+ /* FIXME: It might be better to define md_operand and have it recognize
+ things like %asi, etc. but continuing that route through to the end
+ is a lot of work. */
+ if (*input_line_pointer == '%')
+ {
+ input_line_pointer = save;
+ return 0;
+ }
+ expression (&exp);
+ *input_pointerP = input_line_pointer;
+ input_line_pointer = save;
+ if (exp.X_op != O_constant)
+ return 0;
+ *valueP = exp.X_add_number;
+ return 1;
}
static void
-sparc_ip (str)
+sparc_ip (str, pinsn)
char *str;
+ const struct sparc_opcode **pinsn;
{
char *error_message = "";
char *s;
int match = 0;
int comma = 0;
long immediate_max = 0;
+ int v9_arg_p;
for (s = str; islower (*s) || (*s >= '0' && *s <= '3'); ++s)
;
+
switch (*s)
{
-
case '\0':
break;
as_fatal ("Unknown opcode: `%s'", str);
}
insn = (struct sparc_opcode *) hash_find (op_hash, str);
+ *pinsn = insn;
if (insn == NULL)
{
as_bad ("Unknown opcode: `%s'", str);
{
*--s = ',';
}
+
argsStart = s;
for (;;)
{
opcode = insn->match;
memset (&the_insn, '\0', sizeof (the_insn));
the_insn.reloc = BFD_RELOC_NONE;
+ v9_arg_p = 0;
/*
* Build the opcode, checking as we go to make
{
switch (*args)
{
-#ifndef NO_V9
case 'K':
{
int kmask = 0;
- int i;
/* Parse a series of masks. */
if (*s == '#')
{
while (*s == '#')
{
- ++s;
- for (i = 0; i < MEMBAR_MASKS_SIZE; i++)
- if (!strncmp (s, membar_masks[i].name,
- membar_masks[i].len))
- break;
- if (i < MEMBAR_MASKS_SIZE)
- {
- kmask |= membar_masks[i].mask;
- s += membar_masks[i].len;
- }
- else
+ int mask;
+
+ if (! parse_keyword_arg (sparc_encode_membar, &s,
+ &mask))
{
error_message = ": invalid membar mask name";
goto error;
}
- if (*s == '|')
+ kmask |= mask;
+ while (*s == ' ') { ++s; continue; }
+ if (*s == '|' || *s == '+')
++s;
+ while (*s == ' ') { ++s; continue; }
}
}
else
{
- expressionS exp;
- char *hold;
- char *send;
-
- hold = input_line_pointer;
- input_line_pointer = s;
- expression (&exp);
- send = input_line_pointer;
- input_line_pointer = hold;
-
- kmask = exp.X_add_number;
- if (exp.X_op != O_constant
- || kmask < 0
- || kmask > 127)
+ if (! parse_const_expr_arg (&s, &kmask))
+ {
+ error_message = ": invalid membar mask expression";
+ goto error;
+ }
+ if (kmask < 0 || kmask > 127)
{
error_message = ": invalid membar mask number";
goto error;
}
-
- s = send;
}
- opcode |= SIMM13 (kmask);
+ opcode |= MEMBAR (kmask);
continue;
}
case '*':
{
- int prefetch_fcn = 0;
+ int fcn = 0;
/* Parse a prefetch function. */
if (*s == '#')
{
- s += 1;
- if (!strncmp (s, "n_reads", 7))
- prefetch_fcn = 0, s += 7;
- else if (!strncmp (s, "one_read", 8))
- prefetch_fcn = 1, s += 8;
- else if (!strncmp (s, "n_writes", 8))
- prefetch_fcn = 2, s += 8;
- else if (!strncmp (s, "one_write", 9))
- prefetch_fcn = 3, s += 9;
- else if (!strncmp (s, "page", 4))
- prefetch_fcn = 4, s += 4;
- else
+ if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
{
error_message = ": invalid prefetch function name";
goto error;
}
}
- else if (isdigit (*s))
+ else
{
- while (isdigit (*s))
+ if (! parse_const_expr_arg (&s, &fcn))
{
- prefetch_fcn = prefetch_fcn * 10 + *s - '0';
- ++s;
+ error_message = ": invalid prefetch function expression";
+ goto error;
}
-
- if (prefetch_fcn < 0 || prefetch_fcn > 31)
+ if (fcn < 0 || fcn > 31)
{
error_message = ": invalid prefetch function number";
goto error;
}
}
- else
- {
- error_message = ": unrecognizable prefetch function";
- goto error;
- }
- opcode |= RD (prefetch_fcn);
+ opcode |= RD (fcn);
continue;
}
case '!':
case '?':
- /* Parse a privileged register. */
+ /* Parse a sparc64 privileged register. */
if (*s == '%')
{
struct priv_reg_entry *p = priv_reg_table;
error_message = ": unrecognizable privileged register";
goto error;
}
-#endif
case 'M':
case 'm':
++s;
}
- if (num < 16 || 31 < num)
+ if (current_architecture >= SPARC_OPCODE_ARCH_V9)
{
- error_message = ": asr number must be between 15 and 31";
- goto error;
- } /* out of range */
+ if (num < 16 || 31 < num)
+ {
+ error_message = ": asr number must be between 16 and 31";
+ goto error;
+ }
+ }
+ else
+ {
+ if (num < 0 || 31 < num)
+ {
+ error_message = ": asr number must be between 0 and 31";
+ goto error;
+ }
+ }
opcode |= (*args == 'M' ? RS1 (num) : RD (num));
continue;
{
error_message = ": expecting %asrN";
goto error;
- } /* if %asr followed by a number. */
-
- } /* if %asr */
+ }
+ } /* if %asr */
break;
-#ifndef NO_V9
case 'I':
the_insn.reloc = BFD_RELOC_SPARC_11;
immediate_max = 0x03FF;
immediate_max = 0x01FF;
goto immediate;
+ case 'X':
+ /* V8 systems don't understand BFD_RELOC_SPARC_5. */
+ if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
+ the_insn.reloc = BFD_RELOC_SPARC_5;
+ else
+ the_insn.reloc = BFD_RELOC_SPARC13;
+ /* These fields are unsigned, but for upward compatibility,
+ allow negative values as well. */
+ immediate_max = 0x1f;
+ goto immediate;
+
+ case 'Y':
+ /* V8 systems don't understand BFD_RELOC_SPARC_6. */
+ if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
+ the_insn.reloc = BFD_RELOC_SPARC_6;
+ else
+ the_insn.reloc = BFD_RELOC_SPARC13;
+ /* These fields are unsigned, but for upward compatibility,
+ allow negative values as well. */
+ immediate_max = 0x3f;
+ goto immediate;
+
case 'k':
the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
the_insn.pcrel = 1;
continue;
}
break;
-#endif /* NO_V9 */
case '\0': /* end of args */
if (*s == '\0')
break;
case 'r': /* next operand must be a register */
+ case 'O':
case '1':
case '2':
case 'd':
default:
goto error;
}
- /*
- * Got the register, now figure out where
- * it goes in the opcode.
- */
+
+ /* Got the register, now figure out where
+ it goes in the opcode. */
switch (*args)
{
-
case '1':
opcode |= mask << 14;
continue;
case 'r':
opcode |= (mask << 25) | (mask << 14);
continue;
+
+ case 'O':
+ opcode |= (mask << 25) | (mask << 0);
+ continue;
}
}
break;
break;
} /* register must be multiple of 4 */
-#ifndef NO_V9
if (mask >= 64)
{
- error_message = ": There are only 64 f registers; [0-63]";
+ if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
+ error_message = ": There are only 64 f registers; [0-63]";
+ else
+ error_message = ": There are only 32 f registers; [0-31]";
goto error;
} /* on error */
- if (mask >= 32)
+ else if (mask >= 32)
{
- mask -= 31;
- } /* wrap high bit */
-#else
- if (mask >= 32)
- {
- error_message = ": There are only 32 f registers; [0-31]";
- goto error;
- } /* on error */
-#endif
+ if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
+ {
+ v9_arg_p = 1;
+ mask -= 31; /* wrap high bit */
+ }
+ else
+ {
+ error_message = ": There are only 32 f registers; [0-31]";
+ goto error;
+ }
+ }
}
else
{
switch (*args)
{
-
case 'v':
case 'V':
case 'e':
}
break;
+ case '0': /* 64 bit immediate (setx insn) */
+ the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
+ goto immediate;
+
case 'h': /* high 22 bits */
the_insn.reloc = BFD_RELOC_HI22;
goto immediate;
the_insn.reloc = BFD_RELOC_LO10;
s += 3;
}
-#ifndef NO_V9
else if (c == 'u'
&& s[2] == 'h'
&& s[3] == 'i')
{
the_insn.reloc = BFD_RELOC_SPARC_HH22;
s += 4;
+ v9_arg_p = 1;
}
else if (c == 'u'
&& s[2] == 'l'
{
the_insn.reloc = BFD_RELOC_SPARC_HM10;
s += 4;
+ v9_arg_p = 1;
}
-#endif /* NO_V9 */
else
break;
}
char *s1;
- for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++);;
+ for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) ;
if (s1 != s && isdigit (s1[-1]))
{
&& the_insn.exp.X_add_symbol == 0
&& the_insn.exp.X_op_symbol == 0)
{
-#ifndef NO_V9
/* Handle %uhi/%ulo by moving the upper word to the lower
one and pretending it's %hi/%lo. We also need to watch
for %hi/%lo: the top word needs to be zeroed otherwise
the_insn.reloc = BFD_RELOC_LO10;
the_insn.exp.X_add_number = BSR (the_insn.exp.X_add_number, 32);
break;
- default:
- break;
case BFD_RELOC_HI22:
case BFD_RELOC_LO10:
the_insn.exp.X_add_number &= 0xffffffff;
break;
+ default:
+ break;
}
-#endif
+
/* For pc-relative call instructions, we reject
constants to get better code. */
if (the_insn.pcrel
/* Parse an asi. */
if (*s == '#')
{
- s += 1;
- if (!strncmp (s, "ASI_AIUP", 8))
- asi = 0x10, s += 8;
- else if (!strncmp (s, "ASI_AIUS", 8))
- asi = 0x11, s += 8;
- else if (!strncmp (s, "ASI_PNF", 7))
- asi = 0x82, s += 7;
- else if (!strncmp (s, "ASI_SNF", 7))
- asi = 0x83, s += 7;
- else if (!strncmp (s, "ASI_P", 5))
- asi = 0x80, s += 5;
- else if (!strncmp (s, "ASI_S", 5))
- asi = 0x81, s += 5;
- else
+ if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
{
- error_message = ": invalid asi name";
+ error_message = ": invalid ASI name";
goto error;
}
}
else
{
- char *push = input_line_pointer;
- expressionS e;
- input_line_pointer = s;
-
- expression (&e);
- if (e.X_op != O_constant)
+ if (! parse_const_expr_arg (&s, &asi))
{
- error_message = ": constant required for ASI";
+ error_message = ": invalid ASI expression";
goto error;
}
- asi = e.X_add_number;
- s = input_line_pointer;
- input_line_pointer = push;
-
if (asi < 0 || asi > 255)
{
- error_message = ": invalid asi number";
+ error_message = ": invalid ASI number";
goto error;
}
}
break;
case 'S':
- if (strcmp (str, "set") == 0)
+ if (strcmp (str, "set") == 0
+ || strcmp (str, "setuw") == 0)
{
special_case = SPECIAL_CASE_SET;
continue;
}
+ else if (strcmp (str, "setsw") == 0)
+ {
+ special_case = SPECIAL_CASE_SETSW;
+ continue;
+ }
+ else if (strcmp (str, "setx") == 0)
+ {
+ special_case = SPECIAL_CASE_SETX;
+ continue;
+ }
else if (strncmp (str, "fdiv", 4) == 0)
{
special_case = SPECIAL_CASE_FDIV;
}
break;
-#ifndef NO_V9
case 'o':
if (strncmp (s, "%asi", 4) != 0)
break;
break;
s += 4;
continue;
-#endif /* NO_V9 */
case 't':
if (strncmp (s, "%tbr", 4) != 0)
s += 4;
continue;
-#ifndef NO_V9
case 'x':
{
char *push = input_line_pointer;
input_line_pointer = push;
continue;
}
-#endif
case 'y':
if (strncmp (s, "%y", 2) != 0)
s += 2;
continue;
+ case 'u':
+ case 'U':
+ {
+ /* Parse a sparclet cpreg. */
+ int cpreg;
+ if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
+ {
+ error_message = ": invalid cpreg name";
+ goto error;
+ }
+ opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
+ continue;
+ }
+
default:
as_fatal ("failed sanity check.");
} /* switch on arg code */
+
+ /* Break out of for() loop. */
break;
} /* for each arg that we expect */
+
error:
if (match == 0)
{
/* Args don't match. */
- if (((unsigned) (&insn[1] - sparc_opcodes)) < NUMOPCODES
+ if (((unsigned) (&insn[1] - sparc_opcodes)) < sparc_num_opcodes
&& (insn->name == insn[1].name
|| !strcmp (insn->name, insn[1].name)))
{
}
else
{
- if (insn->architecture > current_architecture
- || (insn->architecture != current_architecture
- && current_architecture > v8))
+ /* We have a match. Now see if the architecture is ok. */
+ int needed_arch_mask = insn->architecture;
+
+ if (v9_arg_p)
{
- if ((!architecture_requested || warn_on_bump)
- && !ARCHITECTURES_CONFLICT_P (current_architecture,
- insn->architecture)
- && !ARCHITECTURES_CONFLICT_P (insn->architecture,
- current_architecture))
- {
- if (warn_on_bump)
- {
- as_warn ("architecture bumped from \"%s\" to \"%s\" on \"%s\"",
- architecture_pname[current_architecture],
- architecture_pname[insn->architecture],
- str);
- } /* if warning */
+ needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9)
+ | (1 << SPARC_OPCODE_ARCH_V9A));
+ needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
+ }
+
+ if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (current_architecture))
+ ; /* ok */
+ /* Can we bump up the architecture? */
+ else if (needed_arch_mask & SPARC_OPCODE_SUPPORTED (max_architecture))
+ {
+ enum sparc_opcode_arch_val needed_architecture =
+ sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
+ & needed_arch_mask);
- current_architecture = insn->architecture;
+ assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
+ if (warn_on_bump
+ && needed_architecture > warn_after_architecture)
+ {
+ as_warn ("architecture bumped from \"%s\" to \"%s\" on \"%s\"",
+ sparc_opcode_archs[current_architecture].name,
+ sparc_opcode_archs[needed_architecture].name,
+ str);
+ warn_after_architecture = needed_architecture;
}
- else
+ current_architecture = needed_architecture;
+ }
+ /* Conflict. */
+ /* ??? This seems to be a bit fragile. What if the next entry in
+ the opcode table is the one we want and it is supported?
+ It is possible to arrange the table today so that this can't
+ happen but what about tomorrow? */
+ else
+ {
+ int arch,printed_one_p = 0;
+ char *p;
+ char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
+
+ /* Create a list of the architectures that support the insn. */
+ needed_arch_mask &= ~ SPARC_OPCODE_SUPPORTED (max_architecture);
+ p = required_archs;
+ arch = sparc_ffs (needed_arch_mask);
+ while ((1 << arch) <= needed_arch_mask)
{
- as_bad ("Architecture mismatch on \"%s\".", str);
- as_tsktsk (" (Requires %s; current architecture is %s.)",
- architecture_pname[insn->architecture],
- architecture_pname[current_architecture]);
- return;
- } /* if bump ok else error */
- } /* if architecture higher */
- } /* if no match */
+ if ((1 << arch) & needed_arch_mask)
+ {
+ if (printed_one_p)
+ *p++ = '|';
+ strcpy (p, sparc_opcode_archs[arch].name);
+ p += strlen (p);
+ printed_one_p = 1;
+ }
+ ++arch;
+ }
+
+ as_bad ("Architecture mismatch on \"%s\".", str);
+ as_tsktsk (" (Requires %s; requested architecture is %s.)",
+ required_archs,
+ sparc_opcode_archs[max_architecture].name);
+ return;
+ }
+ } /* if no match */
break;
- } /* forever looking for a match */
+ } /* forever looking for a match */
the_insn.opcode = opcode;
}
char *litP;
int *sizeP;
{
- int prec;
+ int i,prec;
LITTLENUM_TYPE words[MAX_LITTLENUMS];
- LITTLENUM_TYPE *wordP;
char *t;
char *atof_ieee ();
switch (type)
{
-
case 'f':
case 'F':
case 's':
*sizeP = 0;
return "Bad call to MD_ATOF()";
}
+
t = atof_ieee (input_line_pointer, type, words);
if (t)
input_line_pointer = t;
*sizeP = prec * sizeof (LITTLENUM_TYPE);
- for (wordP = words; prec--;)
+
+ if (target_big_endian)
+ {
+ for (i = 0; i < prec; i++)
+ {
+ md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
+ litP += sizeof (LITTLENUM_TYPE);
+ }
+ }
+ else
{
- md_number_to_chars (litP, (valueT) (*wordP++), sizeof (LITTLENUM_TYPE));
- litP += sizeof (LITTLENUM_TYPE);
+ for (i = prec - 1; i >= 0; i--)
+ {
+ md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
+ litP += sizeof (LITTLENUM_TYPE);
+ }
}
+
return 0;
}
-/*
- * Write out big-endian.
- */
+/* Write a value out to the object file, using the appropriate
+ endianness. */
+
void
md_number_to_chars (buf, val, n)
char *buf;
valueT val;
int n;
{
- number_to_chars_bigendian (buf, val, n);
+ if (target_big_endian)
+ number_to_chars_bigendian (buf, val, n);
+ else
+ number_to_chars_littleendian (buf, val, n);
}
/* Apply a fixS to the frags, now that we know the value it ought to
hold. */
int
-md_apply_fix (fixP, value)
+md_apply_fix3 (fixP, value, segment)
fixS *fixP;
valueT *value;
+ segT segment;
{
char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
offsetT val;
+ long insn;
val = *value;
don't want to include the value of an externally visible symbol. */
if (fixP->fx_addsy != NULL)
{
- if (S_IS_EXTERN (fixP->fx_addsy)
+ if (fixP->fx_addsy->sy_used_in_reloc
+ && (S_IS_EXTERNAL (fixP->fx_addsy)
+ || S_IS_WEAK (fixP->fx_addsy)
+ || (sparc_pic_code && ! fixP->fx_pcrel)
+ || (S_GET_SEGMENT (fixP->fx_addsy) != segment
+ && ((bfd_get_section_flags (stdoutput,
+ S_GET_SEGMENT (fixP->fx_addsy))
+ & SEC_LINK_ONCE) != 0
+ || strncmp (segment_name (S_GET_SEGMENT (fixP->fx_addsy)),
+ ".gnu.linkonce",
+ sizeof ".gnu.linkonce" - 1) == 0)))
&& S_GET_SEGMENT (fixP->fx_addsy) != absolute_section
&& S_GET_SEGMENT (fixP->fx_addsy) != undefined_section
&& ! bfd_is_com_section (S_GET_SEGMENT (fixP->fx_addsy)))
if (fixP->fx_addsy != NULL
&& fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
val = 0;
-#endif
-
- switch (fixP->fx_r_type)
- {
- case BFD_RELOC_16:
- buf[0] = val >> 8;
- buf[1] = val;
- break;
- case BFD_RELOC_32:
- buf[0] = val >> 24;
- buf[1] = val >> 16;
- buf[2] = val >> 8;
- buf[3] = val;
- break;
+ /* When generating PIC code, we do not want an addend for a reloc
+ against a local symbol. We adjust fx_addnumber to cancel out the
+ value already included in val, and to also cancel out the
+ adjustment which bfd_install_relocation will create. */
+ if (sparc_pic_code
+ && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
+ && fixP->fx_addsy != NULL
+ && ! S_IS_COMMON (fixP->fx_addsy)
+ && (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) == 0)
+ fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
+#endif
- case BFD_RELOC_32_PCREL_S2:
- val = (val >>= 2) + 1;
- buf[0] |= (val >> 24) & 0x3f;
- buf[1] = (val >> 16);
- buf[2] = val >> 8;
- buf[3] = val;
- break;
+ /* If this is a data relocation, just output VAL. */
-#ifndef NO_V9
- case BFD_RELOC_64:
- {
- bfd_vma valh = BSR (val, 32);
- buf[0] = valh >> 24;
- buf[1] = valh >> 16;
- buf[2] = valh >> 8;
- buf[3] = valh;
- buf[4] = val >> 24;
- buf[5] = val >> 16;
- buf[6] = val >> 8;
- buf[7] = val;
- }
- break;
+ if (fixP->fx_r_type == BFD_RELOC_16)
+ {
+ md_number_to_chars (buf, val, 2);
+ }
+ else if (fixP->fx_r_type == BFD_RELOC_32)
+ {
+ md_number_to_chars (buf, val, 4);
+ }
+ else if (fixP->fx_r_type == BFD_RELOC_64)
+ {
+ md_number_to_chars (buf, val, 8);
+ }
+ else
+ {
+ /* It's a relocation against an instruction. */
- case BFD_RELOC_SPARC_11:
- if (((val > 0) && (val & ~0x7ff))
- || ((val < 0) && (~(val - 1) & ~0x7ff)))
+ if (INSN_BIG_ENDIAN)
+ insn = bfd_getb32 ((unsigned char *) buf);
+ else
+ insn = bfd_getl32 ((unsigned char *) buf);
+
+ switch (fixP->fx_r_type)
{
- as_bad ("relocation overflow.");
- } /* on overflow */
-
- buf[2] |= (val >> 8) & 0x7;
- buf[3] = val & 0xff;
- break;
+ case BFD_RELOC_32_PCREL_S2:
+ val = val >> 2;
+ /* FIXME: This increment-by-one deserves a comment of why it's
+ being done! */
+ if (! sparc_pic_code
+ || fixP->fx_addsy == NULL
+ || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
+ ++val;
+ insn |= val & 0x3fffffff;
+ break;
- case BFD_RELOC_SPARC_10:
- if (((val > 0) && (val & ~0x3ff))
- || ((val < 0) && (~(val - 1) & ~0x3ff)))
- {
- as_bad ("relocation overflow.");
- } /* on overflow */
+ case BFD_RELOC_SPARC_11:
+ if (! in_signed_range (val, 0x7ff))
+ as_bad ("relocation overflow.");
+ insn |= val & 0x7ff;
+ break;
- buf[2] |= (val >> 8) & 0x3;
- buf[3] = val & 0xff;
- break;
+ case BFD_RELOC_SPARC_10:
+ if (! in_signed_range (val, 0x3ff))
+ as_bad ("relocation overflow.");
+ insn |= val & 0x3ff;
+ break;
- case BFD_RELOC_SPARC_WDISP16:
- if (((val > 0) && (val & ~0x3fffc))
- || ((val < 0) && (~(val - 1) & ~0x3fffc)))
- {
- as_bad ("relocation overflow.");
- } /* on overflow */
+ case BFD_RELOC_SPARC_6:
+ if (! in_bitfield_range (val, 0x3f))
+ as_bad ("relocation overflow.");
+ insn |= val & 0x3f;
+ break;
- val = (val >>= 2) + 1;
- buf[1] |= ((val >> 14) & 0x3) << 4;
- buf[2] |= (val >> 8) & 0x3f;
- buf[3] = val & 0xff;
- break;
+ case BFD_RELOC_SPARC_5:
+ if (! in_bitfield_range (val, 0x1f))
+ as_bad ("relocation overflow.");
+ insn |= val & 0x1f;
+ break;
- case BFD_RELOC_SPARC_WDISP19:
- if (((val > 0) && (val & ~0x1ffffc))
- || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
- {
- as_bad ("relocation overflow.");
- } /* on overflow */
+ case BFD_RELOC_SPARC_WDISP16:
+ /* FIXME: simplify */
+ if (((val > 0) && (val & ~0x3fffc))
+ || ((val < 0) && (~(val - 1) & ~0x3fffc)))
+ as_bad ("relocation overflow.");
+ /* FIXME: The +1 deserves a comment. */
+ val = (val >> 2) + 1;
+ insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
+ break;
- val = (val >>= 2) + 1;
- buf[1] |= (val >> 16) & 0x7;
- buf[2] = (val >> 8) & 0xff;
- buf[3] = val & 0xff;
- break;
+ case BFD_RELOC_SPARC_WDISP19:
+ /* FIXME: simplify */
+ if (((val > 0) && (val & ~0x1ffffc))
+ || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
+ as_bad ("relocation overflow.");
+ /* FIXME: The +1 deserves a comment. */
+ val = (val >> 2) + 1;
+ insn |= val & 0x7ffff;
+ break;
- case BFD_RELOC_SPARC_HH22:
- val = BSR (val, 32);
- /* intentional fallthrough */
-#endif /* NO_V9 */
+ case BFD_RELOC_SPARC_HH22:
+ val = BSR (val, 32);
+ /* intentional fallthrough */
-#ifndef NO_V9
- case BFD_RELOC_SPARC_LM22:
-#endif
- case BFD_RELOC_HI22:
- if (!fixP->fx_addsy)
- {
- buf[1] |= (val >> 26) & 0x3f;
- buf[2] = val >> 18;
- buf[3] = val >> 10;
- }
- else
- {
- buf[2] = 0;
- buf[3] = 0;
- }
- break;
+ case BFD_RELOC_SPARC_LM22:
+ case BFD_RELOC_HI22:
+ if (!fixP->fx_addsy)
+ {
+ insn |= (val >> 10) & 0x3fffff;
+ }
+ else
+ {
+ /* FIXME: Need comment explaining why we do this. */
+ insn &= ~0xffff;
+ }
+ break;
- case BFD_RELOC_SPARC22:
- if (val & ~0x003fffff)
- {
- as_bad ("relocation overflow");
- } /* on overflow */
- buf[1] |= (val >> 16) & 0x3f;
- buf[2] = val >> 8;
- buf[3] = val & 0xff;
- break;
+ case BFD_RELOC_SPARC22:
+ if (val & ~0x003fffff)
+ as_bad ("relocation overflow");
+ insn |= (val & 0x3fffff);
+ break;
-#ifndef NO_V9
- case BFD_RELOC_SPARC_HM10:
- val = BSR (val, 32);
- /* intentional fallthrough */
-#endif /* NO_V9 */
+ case BFD_RELOC_SPARC_HM10:
+ val = BSR (val, 32);
+ /* intentional fallthrough */
- case BFD_RELOC_LO10:
- if (!fixP->fx_addsy)
- {
- buf[2] |= (val >> 8) & 0x03;
- buf[3] = val;
- }
- else
- buf[3] = 0;
- break;
+ case BFD_RELOC_LO10:
+ if (!fixP->fx_addsy)
+ {
+ insn |= val & 0x3ff;
+ }
+ else
+ {
+ /* FIXME: Need comment explaining why we do this. */
+ insn &= ~0xff;
+ }
+ break;
- case BFD_RELOC_SPARC13:
- if (! in_signed_range (val, 0x1fff))
- as_bad ("relocation overflow");
+ case BFD_RELOC_SPARC13:
+ if (! in_signed_range (val, 0x1fff))
+ as_bad ("relocation overflow");
+ insn |= val & 0x1fff;
+ break;
- buf[2] |= (val >> 8) & 0x1f;
- buf[3] = val;
- break;
+ case BFD_RELOC_SPARC_WDISP22:
+ val = (val >> 2) + 1;
+ /* FALLTHROUGH */
+ case BFD_RELOC_SPARC_BASE22:
+ insn |= val & 0x3fffff;
+ break;
- case BFD_RELOC_SPARC_WDISP22:
- val = (val >> 2) + 1;
- /* FALLTHROUGH */
- case BFD_RELOC_SPARC_BASE22:
- buf[1] |= (val >> 16) & 0x3f;
- buf[2] = val >> 8;
- buf[3] = val;
- break;
+ case BFD_RELOC_NONE:
+ default:
+ as_bad ("bad or unhandled relocation type: 0x%02x", fixP->fx_r_type);
+ break;
+ }
- case BFD_RELOC_NONE:
- default:
- as_bad ("bad or unhandled relocation type: 0x%02x", fixP->fx_r_type);
- break;
+ if (INSN_BIG_ENDIAN)
+ bfd_putb32 (insn, (unsigned char *) buf);
+ else
+ bfd_putl32 (insn, (unsigned char *) buf);
}
/* Are we finished with this relocation now? */
case BFD_RELOC_SPARC_WDISP19:
case BFD_RELOC_SPARC_WDISP22:
case BFD_RELOC_64:
+ case BFD_RELOC_SPARC_5:
+ case BFD_RELOC_SPARC_6:
case BFD_RELOC_SPARC_10:
case BFD_RELOC_SPARC_11:
case BFD_RELOC_SPARC_HH22:
default:
abort ();
}
+
+#if defined (OBJ_ELF) || defined (OBJ_AOUT)
+ /* If we are generating PIC code, we need to generate a different
+ set of relocs. */
+
+#ifdef OBJ_ELF
+#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
+#else
+#define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
+#endif
+
+ if (sparc_pic_code)
+ {
+ switch (code)
+ {
+ case BFD_RELOC_32_PCREL_S2:
+ if (! S_IS_DEFINED (fixp->fx_addsy)
+ || S_IS_EXTERNAL (fixp->fx_addsy)
+ || S_IS_WEAK (fixp->fx_addsy))
+ code = BFD_RELOC_SPARC_WPLT30;
+ break;
+ case BFD_RELOC_HI22:
+ if (fixp->fx_addsy != NULL
+ && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
+ code = BFD_RELOC_SPARC_PC22;
+ else
+ code = BFD_RELOC_SPARC_GOT22;
+ break;
+ case BFD_RELOC_LO10:
+ if (fixp->fx_addsy != NULL
+ && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
+ code = BFD_RELOC_SPARC_PC10;
+ else
+ code = BFD_RELOC_SPARC_GOT10;
+ break;
+ case BFD_RELOC_SPARC13:
+ code = BFD_RELOC_SPARC_GOT13;
+ break;
+ default:
+ break;
+ }
+ }
+#endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
+
reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
if (reloc->howto == 0)
{
fixp->fx_r_type, bfd_get_reloc_code_name (code));
return 0;
}
- assert (!fixp->fx_pcrel == !reloc->howto->pc_relative);
/* @@ Why fx_addnumber sometimes and fx_offset other times? */
#ifdef OBJ_AOUT
- if (reloc->howto->pc_relative == 0)
+ if (reloc->howto->pc_relative == 0
+ || code == BFD_RELOC_SPARC_PC10
+ || code == BFD_RELOC_SPARC_PC22)
reloc->addend = fixp->fx_addnumber;
else
reloc->addend = fixp->fx_offset - reloc->address;
#else /* elf or coff */
- if (reloc->howto->pc_relative == 0)
+ if (reloc->howto->pc_relative == 0
+ || code == BFD_RELOC_SPARC_PC10
+ || code == BFD_RELOC_SPARC_PC22)
reloc->addend = fixp->fx_addnumber;
else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
reloc->addend = (section->vma
+ md_pcrel_from (fixp));
else
reloc->addend = fixp->fx_offset;
-
#endif
return reloc;
* -bump
* Warn on architecture bumps. See also -A.
*
- * -Av6, -Av7, -Av8, -Av9, -Asparclite
+ * -Av6, -Av7, -Av8, -Av9, -Av9a, -Asparclite
+ * -xarch=v8plus, -xarch=v8plusa
* Select the architecture. Instructions or features not
* supported by the selected architecture cause fatal errors.
*
* The default is to start at v6, and bump the architecture up
- * whenever an instruction is seen at a higher level.
+ * whenever an instruction is seen at a higher level. If 32 bit
+ * environments, v9 is not bumped up to, the user must pass -Av9.
+ *
+ * -xarch=v8plus{,a} is for compatibility with the Sun assembler.
*
* If -bump is specified, a warning is printing when bumping to
* higher levels.
*
* If an architecture is specified, all instructions must match
* that architecture. Any higher level instructions are flagged
- * as errors.
+ * as errors. Note that in the 32 bit environment specifying
+ * -Av9 does not automatically create a v9 object file, a v9
+ * insn must be seen.
*
- * if both an architecture and -bump are specified, the
+ * If both an architecture and -bump are specified, the
* architecture starts at the specified level, but bumps are
- * warnings.
+ * warnings. Note that we can't set `current_architecture' to
+ * the requested level in this case: in the 32 bit environment,
+ * we still must avoid creating v9 object files unless v9 insns
+ * are seen.
*
* Note:
* Bumping between incompatible architectures is always an
#ifdef OBJ_ELF
CONST char *md_shortopts = "A:K:VQ:sq";
#else
+#ifdef OBJ_AOUT
+CONST char *md_shortopts = "A:k";
+#else
CONST char *md_shortopts = "A:";
#endif
+#endif
struct option md_longopts[] = {
#define OPTION_BUMP (OPTION_MD_BASE)
{"bump", no_argument, NULL, OPTION_BUMP},
#define OPTION_SPARC (OPTION_MD_BASE + 1)
{"sparc", no_argument, NULL, OPTION_SPARC},
+#define OPTION_XARCH (OPTION_MD_BASE + 2)
+ {"xarch", required_argument, NULL, OPTION_XARCH},
+#ifdef SPARC_BIENDIAN
+#define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 3)
+ {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
+#define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 4)
+ {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
+#endif
+ #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 5)
+ {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
{NULL, no_argument, NULL, 0}
};
size_t md_longopts_size = sizeof(md_longopts);
{
case OPTION_BUMP:
warn_on_bump = 1;
+ warn_after_architecture = SPARC_OPCODE_ARCH_V6;
break;
+ case OPTION_XARCH:
+ /* ??? We could add v8plus and v8plusa to sparc_opcode_archs.
+ But we might want v8plus to mean something different than v9
+ someday, and we'd recognize more -xarch options than Sun's
+ assembler does (which may lead to a conflict someday). */
+ if (strcmp (arg, "v8plus") == 0)
+ arg = "v9";
+ else if (strcmp (arg, "v8plusa") == 0)
+ arg = "v9a";
+ else
+ {
+ as_bad ("invalid architecture -xarch=%s", arg);
+ return 0;
+ }
+
+ /* fall through */
+
case 'A':
{
- char *p = arg;
- const char **arch;
-
- for (arch = architecture_pname; *arch != NULL; ++arch)
- {
- if (strcmp (p, *arch) == 0)
- break;
- }
+ enum sparc_opcode_arch_val new_arch = sparc_opcode_lookup_arch (arg);
- if (*arch == NULL)
+ if (new_arch == SPARC_OPCODE_ARCH_BAD)
{
- as_bad ("invalid architecture -A%s", p);
+ as_bad ("invalid architecture -A%s", arg);
return 0;
}
else
{
- enum sparc_architecture new_arch = arch - architecture_pname;
-#ifdef NO_V9
- if (new_arch == v9)
- {
- as_error ("v9 support not compiled in");
- return 0;
- }
-#endif
- current_architecture = new_arch;
+ max_architecture = new_arch;
architecture_requested = 1;
}
}
/* Ignore -sparc, used by SunOS make default .s.o rule. */
break;
+ case OPTION_ENFORCE_ALIGNED_DATA:
+ enforce_aligned_data = 1;
+ break;
+
+#ifdef SPARC_BIENDIAN
+ case OPTION_LITTLE_ENDIAN:
+ target_big_endian = 0;
+ break;
+ case OPTION_BIG_ENDIAN:
+ target_big_endian = 1;
+ break;
+#endif
+
+#ifdef OBJ_AOUT
+ case 'k':
+ sparc_pic_code = 1;
+ break;
+#endif
+
#ifdef OBJ_ELF
case 'V':
print_version_id ();
if (strcmp (arg, "PIC") != 0)
as_warn ("Unrecognized option following -K");
else
- {
- as_warn ("gas does not currently support PIC code for the SPARC");
- as_fatal ("use /usr/ccs/bin/as instead");
- }
+ sparc_pic_code = 1;
+ break;
#endif
default:
return 0;
}
- return 1;
+ return 1;
}
void
md_show_usage (stream)
FILE *stream;
{
- const char **arch;
+ const struct sparc_opcode_arch *arch;
+
fprintf(stream, "SPARC options:\n");
- for (arch = architecture_pname; *arch; arch++)
+ for (arch = &sparc_opcode_archs[0]; arch->name; arch++)
{
- if (arch != architecture_pname)
+ if (arch != &sparc_opcode_archs[0])
fprintf (stream, " | ");
- fprintf (stream, "-A%s", *arch);
+ fprintf (stream, "-A%s", arch->name);
}
- fprintf (stream, "\n\
+ fprintf (stream, "\n-xarch=v8plus | -xarch=v8plusa\n");
+ fprintf (stream, "\
specify variant of SPARC architecture\n\
-bump warn when assembler switches architectures\n\
--sparc ignored\n");
+-sparc ignored\n
+--enforce-aligned-data force .long, etc., to be aligned correctly\n");
+#ifdef OBJ_AOUT
+ fprintf (stream, "\
+-k generate PIC\n");
+#endif
#ifdef OBJ_ELF
- fprintf(stream, "\
+ fprintf (stream, "\
+-KPIC generate PIC\n\
-V print assembler version number\n\
-q ignored\n\
-Qy, -Qn ignored\n\
-s ignored\n");
#endif
+#ifdef SPARC_BIENDIAN
+ fprintf (stream, "\
+-EL generate code for a little endian machine\n\
+-EB generate code for a big endian machine\n");
+#endif
}
\f
/* We have no need to default values of symbols. */
md_pcrel_from (fixP)
fixS *fixP;
{
- return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
+ long ret;
+
+ ret = fixP->fx_where + fixP->fx_frag->fr_address;
+ if (! sparc_pic_code
+ || fixP->fx_addsy == NULL
+ || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
+ ret += fixP->fx_size;
+ return ret;
}
/* end of tc-sparc.c */
projects / deliverable / binutils-gdb.git / blobdiff