x86: replace Reg8, Reg16, Reg32, and Reg64

[deliverable/binutils-gdb.git] / gas / doc / as.texinfo

diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index b82204dfdf773de3a3f6f293e350f4e31c72cf0e..4251808775c025cb94a202b130b8247e0a0d36ac 100644 (file)
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -487,7 +487,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
     @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-me6500}|@b{-mppc64bridge}|
     @b{-mbooke}|@b{-mpower4}|@b{-mpwr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}|
     @b{-mpower7}|@b{-mpwr7}|@b{-mpower8}|@b{-mpwr8}|@b{-mpower9}|@b{-mpwr9}@b{-ma2}|
-    @b{-mcell}|@b{-mspe}|@b{-mtitan}|@b{-me300}|@b{-mcom}]
+    @b{-mcell}|@b{-mspe}|@b{-mspe2}|@b{-mtitan}|@b{-me300}|@b{-mcom}]
    [@b{-many}] [@b{-maltivec}|@b{-mvsx}|@b{-mhtm}|@b{-mvle}]
    [@b{-mregnames}|@b{-mno-regnames}]
    [@b{-mrelocatable}|@b{-mrelocatable-lib}|@b{-K PIC}] [@b{-memb}]
@@ -502,6 +502,13 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-mnolink-relax}]
    [@b{-mno-warn-regname-label}]
 @end ifset
+@ifset RISCV
+
+@emph{Target RISC-V options:}
+   [@b{-fpic}|@b{-fPIC}|@b{-fno-pic}]
+   [@b{-march}=@var{ISA}]
+   [@b{-mabi}=@var{ABI}]
+@end ifset
 @ifset RL78
 
 @emph{Target RL78 options:}
@@ -520,12 +527,6 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-mint-register=@var{number}}]
    [@b{-mgcc-abi}|@b{-mrx-abi}]
 @end ifset
-@ifset RISCV
-
-@emph{Target RISC-V options:}
-   [@b{-march}=@var{ISA}]
-   [@b{-mabi}=@var{ABI}]
-@end ifset
 @ifset S390
 
 @emph{Target s390 options:}
@@ -1702,14 +1703,14 @@ PowerPC processor.
 @ifset RISCV
 
 @ifclear man
-@xref{RISC-V-Opts}, for the options available when @value{AS} is configured
+@xref{RISC-V-Options}, for the options available when @value{AS} is configured
 for a RISC-V processor.
 @end ifclear
 
 @ifset man
 @c man begin OPTIONS
 The following options are available when @value{AS} is configured for a
-RISC-V  processor.
+RISC-V processor.
 @c man end
 @c man begin INCLUDE
 @include c-riscv.texi
@@ -4606,7 +4607,7 @@ required, as described below.
 
 The second expression (also absolute) gives the fill value to be stored in the
 padding bytes.  It (and the comma) may be omitted.  If it is omitted, the
-padding bytes are normally zero.  However, on some systems, if the section is
+padding bytes are normally zero.  However, on most systems, if the section is
 marked as containing code and the fill value is omitted, the space is filled
 with no-op instructions.
 
@@ -4706,7 +4707,7 @@ is already a multiple of 8, no change is needed.
 
 The second expression (also absolute) gives the fill value to be stored in the
 padding bytes.  It (and the comma) may be omitted.  If it is omitted, the
-padding bytes are normally zero.  However, on some systems, if the section is
+padding bytes are normally zero.  However, on most systems, if the section is
 marked as containing code and the fill value is omitted, the space is filled
 with no-op instructions.
 
@@ -5833,6 +5834,19 @@ state machine to @var{value}, which must be an unsigned integer.
 This directive will set the @code{discriminator} register in the @code{.debug_line}
 state machine to @var{value}, which must be an unsigned integer.
 
+@item view @var{value}
+This option causes a row to be added to @code{.debug_line} in reference to the
+current address (which might not be the same as that of the following assembly
+instruction), and to associate @var{value} with the @code{view} register in the
+@code{.debug_line} state machine.  If @var{value} is a label, both the
+@code{view} register and the label are set to the number of prior @code{.loc}
+directives at the same program location.  If @var{value} is the literal
+@code{0}, the @code{view} register is set to zero, and the assembler asserts
+that there aren't any prior @code{.loc} directives at the same program
+location.  If @var{value} is the literal @code{-0}, the assembler arrange for
+the @code{view} register to be reset in this row, even if there are prior
+@code{.loc} directives at the same program location.
+
 @end table
 
 @node Loc_mark_labels
@@ -6159,7 +6173,7 @@ multiple of 8, no change is needed.
 
 The second expression (also absolute) gives the fill value to be stored in the
 padding bytes.  It (and the comma) may be omitted.  If it is omitted, the
-padding bytes are normally zero.  However, on some systems, if the section is
+padding bytes are normally zero.  However, on most systems, if the section is
 marked as containing code and the fill value is omitted, the space is filled
 with no-op instructions.
 
@@ -6379,6 +6393,9 @@ is equivalent to assembling
         .long   0
 @end example
 
+A count of zero is allowed, but nothing is generated.  Negative counts are not
+allowed and if encountered will be treated as if they were zero.
+
 @node Sbttl
 @section @code{.sbttl "@var{subheading}"}
 
@@ -7384,7 +7401,7 @@ long values into the output.
 @cindex eight-byte integer
 @cindex integer, 8-byte
 
-Like the @option{.8byte} directive, except that it inserts unaligned, eight
+Like the @option{.2byte} directive, except that it inserts unaligned, eight
 byte long bignum values into the output.
 
 @end ifset
@@ -7694,12 +7711,12 @@ subject, see the hardware manufacturer's manual.
 @ifset PRU
 * PRU-Dependent::               PRU Dependent Features
 @end ifset
-@ifset RL78
-* RL78-Dependent::              RL78 Dependent Features
-@end ifset
 @ifset RISCV
 * RISC-V-Dependent::            RISC-V Dependent Features
 @end ifset
+@ifset RL78
+* RL78-Dependent::              RL78 Dependent Features
+@end ifset
 @ifset RX
 * RX-Dependent::                RX Dependent Features
 @end ifset
@@ -7930,14 +7947,14 @@ family.
 @include c-pru.texi
 @end ifset
 
-@ifset RL78
-@include c-rl78.texi
-@end ifset
-
 @ifset RISCV
 @include c-riscv.texi
 @end ifset
 
+@ifset RL78
+@include c-rl78.texi
+@end ifset
+
 @ifset RX
 @include c-rx.texi
 @end ifset