x86: replace Reg8, Reg16, Reg32, and Reg64

[deliverable/binutils-gdb.git] / gas / doc / c-aarch64.texi

diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 677420594e1deaa2ef963bd62272195c6c3e652e..538b103e2034f805e5fd768e93d39ff326298dae 100644 (file)
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -65,6 +65,7 @@ on the target processor.  The following processor names are recognized:
 @code{exynos-m1},
 @code{falkor},
 @code{qdf24xx},
+@code{saphira},
 @code{thunderx},
 @code{vulcan},
 @code{xgene1}
@@ -89,7 +90,7 @@ This option specifies the target architecture.  The assembler will
 issue an error message if an attempt is made to assemble an
 instruction which will not execute on the target architecture.  The
 following architecture names are recognized: @code{armv8-a},
-@code{armv8.1-a}, @code{armv8.2-a} and @code{armv8.3-a}.
+@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a} and @code{armv8.4-a}.
 
 If both @option{-mcpu} and @option{-march} are specified, the
 assembler will use the setting for @option{-mcpu}.  If neither are
@@ -139,7 +140,15 @@ automatically cause those extensions to be disabled.
 @item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
  @tab Enable CRC instructions.
 @item @code{crypto} @tab ARMv8-A @tab No
- @tab Enable cryptographic extensions.  This implies @code{fp} and @code{simd}.
+ @tab Enable cryptographic extensions.  This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
+@item @code{aes} @tab ARMv8-A @tab No
+ @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
+@item @code{sha2} @tab ARMv8-A @tab No
+ @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
+@item @code{sha3} @tab ARMv8.2-A @tab No
+ @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
+@item @code{sm4} @tab ARMv8.2-A @tab No
+ @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
  @tab Enable floating-point extensions.
 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
@@ -165,8 +174,11 @@ automatically cause those extensions to be disabled.
 @item @code{sve} @tab ARMv8.2-A @tab No
  @tab Enable the Scalable Vector Extensions.  This implies @code{fp16},
  @code{simd} and @code{compnum}.
-@item @code{dotprod} @tab ARMv8.2-A @tab No
+@item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
  @tab Enable the Dot Product extension.  This implies @code{simd}.
+@item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
+ @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
+ This implies @code{fp16}.
 @end multitable
 
 @node AArch64 Syntax
@@ -363,6 +375,9 @@ example:
         foo .req w0
 @end smallexample
 
+ip0, ip1, lr and fp are automatically defined to
+alias to X16, X17, X30 and X29 respectively.
+
 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
 
 @c TTTTTTTTTTTTTTTTTTTTTTTTTT