rx: make field type enum

[deliverable/binutils-gdb.git] / gas / doc / c-aarch64.texi

diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 2717af2ece805678ace056dcb8e10f44fc5d76fd..a193908f3d572ecdad5a9a293d7279d63a92254a 100644 (file)
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -1,4 +1,4 @@
-@c Copyright (C) 2009-2015 Free Software Foundation, Inc.
+@c Copyright (C) 2009-2016 Free Software Foundation, Inc.
 @c Contributed by ARM Ltd.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
@@ -128,23 +128,30 @@ automatically cause those extensions to be disabled.
 @multitable @columnfractions .12 .17 .17 .54
 @headitem Extension @tab Minimum Architecture @tab Enabled by default
  @tab Description
-@item @code{crc} @tab ARMv8-A @tab No
+@item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
  @tab Enable CRC instructions.
 @item @code{crypto} @tab ARMv8-A @tab No
  @tab Enable cryptographic extensions.  This implies @code{fp} and @code{simd}.
 @item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
  @tab Enable floating-point extensions.
-@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
- @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
-@item @code{pan} @tab ARMv8-A @tab ARMv8-A or later
- @tab Enable Privileged Access Never support.
-@item @code{lor} @tab ARMv8-A @tab ARMv8-A or later
- @tab Enable Limited Ordering Regions extensions.
-@item @code{rdma} @tab ARMv8-A @tab ARMv8-A or later
- @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 @item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
  @tab Enable ARMv8.2 16-bit floating-point support.  This implies
  @code{fp}.
+@item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable Limited Ordering Regions extensions.
+@item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable Large System extensions.
+@item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable Privileged Access Never support.
+@item @code{profile} @tab ARMv8.2-A @tab No
+ @tab Enable statistical profiling extensions.
+@item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
+ @tab Enable the Reliability, Availability and Serviceability
+ extension.
+@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
+@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
+ @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 @end multitable
 
 @node AArch64 Syntax
@@ -271,12 +278,35 @@ incrementally to the architecture being compiled for.
 This directive switches to the @code{.bss} section.
 
 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
+
+@cindex @code{.cpu} directive, AArch64
+@item .cpu @var{name}
+Set the target processor.  Valid values for @var{name} are the same as
+those accepted by the @option{-mcpu=} command line option.
+
 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
+
+@cindex @code{.dword} directive, AArch64
+@item .dword @var{expressions}
+The @code{.dword} directive produces 64 bit values.
+
 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
+
+@cindex @code{.even} directive, AArch64
+@item .even
+The @code{.even} directive aligns the output on the next even byte
+boundary.
+
 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
 @c IIIIIIIIIIIIIIIIIIIIIIIIII
+
+@cindex @code{.inst} directive, AArch64
+@item .inst @var{expressions}
+Inserts the expressions into the output as if they were instructions,
+rather than data.
+
 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
@@ -322,6 +352,18 @@ example:
 
 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
 
+@cindex @code{.tlsdescadd} directive, AArch64
+@item   @code{.tlsdescadd}
+Emits a TLSDESC_ADD reloc on the next instruction.
+
+@cindex @code{.tlsdesccall} directive, AArch64
+@item   @code{.tlsdesccall}
+Emits a TLSDESC_CALL reloc on the next instruction.
+
+@cindex @code{.tlsdescldr} directive, AArch64
+@item   @code{.tlsdescldr}
+Emits a TLSDESC_LDR reloc on the next instruction.
+
 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
 
 @cindex @code{.unreq} directive, AArch64
@@ -342,12 +384,14 @@ should only be done if it is really necessary.
 
 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
-@c YYYYYYYYYYYYYYYYYYYYYYYYYY
-@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 
 @cindex @code{.xword} directive, AArch64
-@item .xword
-The @code{.xword} directive produces 64 bit values.
+@item .xword @var{expressions}
+The @code{.xword} directive produces 64 bit values.  This is the same
+as the @code{.dword} directive.
+
+@c YYYYYYYYYYYYYYYYYYYYYYYYYY
+@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 
 @end table