-@c Copyright (C) 2009-2014 Free Software Foundation, Inc.
+@c Copyright (C) 2009-2016 Free Software Foundation, Inc.
@c Contributed by ARM Ltd.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
This option specifies the target processor. The assembler will issue an error
message if an attempt is made to assemble an instruction which will not execute
on the target processor. The following processor names are recognized:
+@code{cortex-a35},
@code{cortex-a53},
@code{cortex-a57},
+@code{cortex-a72},
+@code{exynos-m1},
+@code{qdf24xx},
+@code{thunderx},
+@code{xgene1}
and
-@code{xgene-1}.
+@code{xgene2}.
The special name @code{all} may be used to allow the assembler to accept
instructions valid for any supported processor, including all optional
extensions.
This option specifies the target architecture. The assembler will
issue an error message if an attempt is made to assemble an
instruction which will not execute on the target architecture. The
-only value for @var{architecture} is @code{armv8-a}.
+following architecture names are recognized: @code{armv8-a},
+@code{armv8.1-a} and @code{armv8.2-a}.
If both @option{-mcpu} and @option{-march} are specified, the
assembler will use the setting for @option{-mcpu}. If neither are
@option{-mcpu}, extensions are not always enabled by default,
@xref{AArch64 Extensions}.
+@cindex @code{-mverbose-error} command line option, AArch64
+@item -mverbose-error
+This option enables verbose error messages for AArch64 gas. This option
+is enabled by default.
+
+@cindex @code{-mno-verbose-error} command line option, AArch64
+@item -mno-verbose-error
+This option disables verbose error messages in AArch64 gas.
+
@end table
@c man end
@multitable @columnfractions .12 .17 .17 .54
@headitem Extension @tab Minimum Architecture @tab Enabled by default
@tab Description
-@item @code{crc} @tab ARMv8-A @tab No
+@item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
@tab Enable CRC instructions.
@item @code{crypto} @tab ARMv8-A @tab No
@tab Enable cryptographic extensions. This implies @code{fp} and @code{simd}.
@item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
@tab Enable floating-point extensions.
+@item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
+ @tab Enable ARMv8.2 16-bit floating-point support. This implies
+ @code{fp}.
+@item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable Limited Ordering Regions extensions.
+@item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable Large System extensions.
+@item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable Privileged Access Never support.
+@item @code{profile} @tab ARMv8.2-A @tab No
+ @tab Enable statistical profiling extensions.
+@item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
+ @tab Enable the Reliability, Availability and Serviceability
+ extension.
+@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
@tab Enable Advanced SIMD extensions. This implies @code{fp}.
@end multitable
@cindex ADRP, ADD, LDR/STR group relocations, AArch64
Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
instructions can be generated by prefixing the label with
-@samp{#:pg_hi21:} and @samp{#:lo12:} respectively.
+@samp{:pg_hi21:} and @samp{#:lo12:} respectively.
For example to use 33-bit (+/-4GB) pc-relative addressing to
load the address of @var{foo} into x0:
@smallexample
- adrp x0, #:pg_hi21:foo
+ adrp x0, :pg_hi21:foo
add x0, x0, #:lo12:foo
@end smallexample
Or to load the value of @var{foo} into x0:
@smallexample
- adrp x0, #:pg_hi21:foo
+ adrp x0, :pg_hi21:foo
ldr x0, [x0, #:lo12:foo]
@end smallexample
-Note that @samp{#:pg_hi21:} is optional.
+Note that @samp{:pg_hi21:} is optional.
@smallexample
adrp x0, foo
is equivalent to
@smallexample
- adrp x0, #:pg_hi21:foo
+ adrp x0, :pg_hi21:foo
@end smallexample
@node AArch64 Floating Point
@table @code
@c AAAAAAAAAAAAAAAAAAAAAAAAA
+
+@cindex @code{.arch} directive, AArch64
+@item .arch @var{name}
+Select the target architecture. Valid values for @var{name} are the same as
+for the @option{-march} commandline option.
+
+Specifying @code{.arch} clears any previously selected architecture
+extensions.
+
+@cindex @code{.arch_extension} directive, AArch64
+@item .arch_extension @var{name}
+Add or remove an architecture extension to the target architecture. Valid
+values for @var{name} are the same as those accepted as architectural
+extensions by the @option{-mcpu} commandline option.
+
+@code{.arch_extension} may be used multiple times to add or remove extensions
+incrementally to the architecture being compiled for.
+
@c BBBBBBBBBBBBBBBBBBBBBBBBBB
@cindex @code{.bss} directive, AArch64
This directive switches to the @code{.bss} section.
@c CCCCCCCCCCCCCCCCCCCCCCCCCC
+
+@cindex @code{.cpu} directive, AArch64
+@item .cpu @var{name}
+Set the target processor. Valid values for @var{name} are the same as
+those accepted by the @option{-mcpu=} command line option.
+
@c DDDDDDDDDDDDDDDDDDDDDDDDDD
+
+@cindex @code{.dword} directive, AArch64
+@item .dword @var{expressions}
+The @code{.dword} directive produces 64 bit values.
+
@c EEEEEEEEEEEEEEEEEEEEEEEEEE
+
+@cindex @code{.even} directive, AArch64
+@item .even
+The @code{.even} directive aligns the output on the next even byte
+boundary.
+
@c FFFFFFFFFFFFFFFFFFFFFFFFFF
@c GGGGGGGGGGGGGGGGGGGGGGGGGG
@c HHHHHHHHHHHHHHHHHHHHHHHHHH
@c IIIIIIIIIIIIIIIIIIIIIIIIII
+
+@cindex @code{.inst} directive, AArch64
+@item .inst @var{expressions}
+Inserts the expressions into the output as if they were instructions,
+rather than data.
+
@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
@c KKKKKKKKKKKKKKKKKKKKKKKKKK
@c LLLLLLLLLLLLLLLLLLLLLLLLLL
@c TTTTTTTTTTTTTTTTTTTTTTTTTT
+@cindex @code{.tlsdescadd} directive, AArch64
+@item @code{.tlsdescadd}
+Emits a TLSDESC_ADD reloc on the next instruction.
+
+@cindex @code{.tlsdesccall} directive, AArch64
+@item @code{.tlsdesccall}
+Emits a TLSDESC_CALL reloc on the next instruction.
+
+@cindex @code{.tlsdescldr} directive, AArch64
+@item @code{.tlsdescldr}
+Emits a TLSDESC_LDR reloc on the next instruction.
+
@c UUUUUUUUUUUUUUUUUUUUUUUUUU
@cindex @code{.unreq} directive, AArch64
@c WWWWWWWWWWWWWWWWWWWWWWWWWW
@c XXXXXXXXXXXXXXXXXXXXXXXXXX
+
+@cindex @code{.xword} directive, AArch64
+@item .xword @var{expressions}
+The @code{.xword} directive produces 64 bit values. This is the same
+as the @code{.dword} directive.
+
@c YYYYYYYYYYYYYYYYYYYYYYYYYY
@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
projects / deliverable / binutils-gdb.git / blobdiff