-@c Copyright (C) 1996-2015 Free Software Foundation, Inc.
+@c Copyright (C) 1996-2017 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@code{cortex-a8},
@code{cortex-a9},
@code{cortex-a15},
+@code{cortex-a17},
+@code{cortex-a32},
+@code{cortex-a35},
@code{cortex-a53},
@code{cortex-a57},
@code{cortex-a72},
+@code{cortex-a73},
@code{cortex-r4},
@code{cortex-r4f},
@code{cortex-r5},
@code{cortex-r7},
+@code{cortex-r8},
+@code{cortex-m33},
+@code{cortex-m23},
@code{cortex-m7},
@code{cortex-m4},
@code{cortex-m3},
@code{exynos-m1},
@code{marvell-pj4},
@code{marvell-whitney},
+@code{falkor},
+@code{qdf24xx},
@code{xgene1},
@code{xgene2},
@code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
@code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
@code{virt} (Virtualization Extensions for v7-A architecture, implies
@code{idiv}),
-@code{pan} (Priviliged Access Never Extensions for v8-A architecture)
+@code{pan} (Privileged Access Never Extensions for v8-A architecture),
+@code{ras} (Reliability, Availability and Serviceability extensions
+for v8-A architecture),
+@code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
+@code{simd})
and
@code{xscale}.
@code{armv6j},
@code{armv6k},
@code{armv6z},
-@code{armv6zk},
+@code{armv6kz},
@code{armv6-m},
@code{armv6s-m},
@code{armv7},
@code{armv7-m},
@code{armv7e-m},
@code{armv8-a},
+@code{armv8.1-a},
+@code{armv8.2-a},
+@code{armv8.3-a},
@code{iwmmxt}
@code{iwmmxt2}
and
@code{arm1136jf-s},
@code{maverick},
@code{neon},
+@code{neon-vfpv3},
+@code{neon-fp16},
@code{neon-vfpv4},
@code{neon-fp-armv8},
+@code{crypto-neon-fp-armv8},
+@code{neon-fp-armv8.1}
and
-@code{crypto-neon-fp-armv8}.
+@code{crypto-neon-fp-armv8.1}.
In addition to determining which instructions are assembled, this option
also affects the way in which the @code{.double} assembler directive behaves
when assembling little-endian code.
The default is dependent on the processor selected. For Architecture 5 or
-later, the default is to assembler for VFP instructions; for earlier
+later, the default is to assemble for VFP instructions; for earlier
architectures the default is to assemble for FPA instructions.
@cindex @code{-mthumb} command line option, ARM
MOVT r0, #:upper16:foo
@end smallexample
+Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
+@samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
+generated by prefixing the value with @samp{#:lower0_7:#},
+@samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
+respectively. For example to load the 32-bit address of foo into r0:
+
+@smallexample
+ MOVS r0, #:upper8_15:#foo
+ LSLS r0, r0, #8
+ ADDS r0, #:upper0_7:#foo
+ LSLS r0, r0, #8
+ ADDS r0, #:lower8_15:#foo
+ LSLS r0, r0, #8
+ ADDS r0, #:lower0_7:#foo
+@end smallexample
+
@node ARM-Neon-Alignment
@subsection NEON Alignment Specifiers
@c AAAAAAAAAAAAAAAAAAAAAAAAA
+@ifclear ELF
@cindex @code{.2byte} directive, ARM
@cindex @code{.4byte} directive, ARM
@cindex @code{.8byte} directive, ARM
@itemx .4byte @var{expression} [, @var{expression}]*
@itemx .8byte @var{expression} [, @var{expression}]*
These directives write 2, 4 or 8 byte values to the output section.
+@end ifclear
@cindex @code{.align} directive, ARM
@item .align @var{expression} [, @var{expression}]
interworking is not going to be performed. The presence of this
directive also implies @code{.thumb}
-This directive is not neccessary when generating EABI objects. On these
+This directive is not necessary when generating EABI objects. On these
targets the encoding is implicit when generating Thumb code.
@cindex @code{.thumb_set} directive, ARM
@cindex @code{.unwind_raw} directive, ARM
@item .unwind_raw @var{offset}, @var{byte1}, @dots{}
-Insert one of more arbitary unwind opcode bytes, which are known to adjust
+Insert one of more arbitrary unwind opcode bytes, which are known to adjust
the stack pointer by @var{offset} bytes.
For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
know more about the object-file format used to represent unwind
information, you may consult the @cite{Exception Handling ABI for the
ARM Architecture} available from @uref{http://infocenter.arm.com}.
+