@code{cortex-a5},
@code{cortex-a8},
@code{cortex-a9},
+@code{cortex-a15},
@code{cortex-r4},
@code{cortex-r4f},
+@code{cortex-m4},
@code{cortex-m3},
@code{cortex-m1},
@code{cortex-m0},
In addition to the basic instruction set, the assembler can be told to
accept various extension mnemonics that extend the processor using the
co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
-is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
-are currently supported:
-@code{+maverick}
-@code{+iwmmxt}
+is equivalent to specifying @code{-mcpu=ep9312}.
+
+Multiple extensions may be specified, separated by a @code{+}. The
+extensions should be specified in ascending alphabetical order.
+
+Extension mnemonics may also be removed from those the assembler accepts.
+This is done be prepending @code{no} to the option that adds the extension.
+Extensions that are removed should be listed after all extensions which have
+been added, again in ascending alphabetical order. For example,
+@code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
+
+
+The following extensions are currently supported:
+@code{iwmmxt},
+@code{iwmmxt2},
+@code{maverick},
and
-@code{+xscale}.
+@code{xscale}.
@cindex @code{-march=} command line option, ARM
@item -march=@var{architecture}[+@var{extension}@dots{}]
@code{vfpv3xd-d16},
@code{vfpv4},
@code{vfpv4-d16},
+@code{fpv4-sp-d16},
@code{arm1020t},
@code{arm1020e},
@code{arm1136jf-s},
Select the target architecture. Valid values for @var{name} are the same as
for the @option{-march} commandline option.
+Specifying @code{.arch} clears any previously selected architecture
+extensions.
+
+@cindex @code{.arch_extension} directive, ARM
+@item .arch_extension @var{name}
+Add or remove an architecture extension to the target architecture. Valid
+values for @var{name} are the same as those accepted as architectural
+extensions by the @option{-mcpu} commandline option.
+
+@code{.arch_extension} may be used multiple times to add or remove extensions
+incrementally to the architecture being compiled for.
+
@cindex @code{.arm} directive, ARM
@item .arm
This performs the same action as @var{.code 32}.
Select the target processor. Valid values for @var{name} are the same as
for the @option{-mcpu} commandline option.
+Specifying @code{.cpu} clears any previously selected architecture
+extensions.
+
@c DDDDDDDDDDDDDDDDDDDDDDDDDD
@cindex @code{.dn} and @code{.qn} directives, ARM
@item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
-@item @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
+@itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
The @code{dn} and @code{qn} directives are used to create typed
and/or indexed register aliases for use in Advanced SIMD Extension
The @var{tag} is either an attribute number, or one of the following:
@code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
@code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
-@code{Tag_THUMB_ISA_use}, @code{Tag_VFP_arch}, @code{Tag_WMMX_arch},
+@code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
@code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
@code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
@code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
@code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
@code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
@code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
-@code{Tag_ABI_align8_needed}, @code{Tag_ABI_align8_preserved},
+@code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
@code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
@code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
@code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
@code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
-@code{Tag_VFP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
+@code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
@code{Tag_MPextension_use}, @code{Tag_DIV_use},
@code{Tag_nodefaults}, @code{Tag_also_compatible_with},
@code{Tag_conformance}, @code{Tag_T2EE_use},
The @var{value} is either a @code{number}, @code{"string"}, or
@code{number, "string"} depending on the tag.
+Note - the following legacy values are also accepted by @var{tag}:
+@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
+@code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
+
@cindex @code{.even} directive, ARM
@item .even
This directive aligns to an even-numbered address.
@cindex @code{.inst} directive, ARM
@item .inst @var{opcode} [ , @dots{} ]
-@item .inst.n @var{opcode} [ , @dots{} ]
-@item .inst.w @var{opcode} [ , @dots{} ]
+@itemx .inst.n @var{opcode} [ , @dots{} ]
+@itemx .inst.w @var{opcode} [ , @dots{} ]
Generates the instruction corresponding to the numerical value @var{opcode}.
@code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
specified explicitly, overriding the normal encoding rules.
Make all unwinder annotations relative to a frame pointer. Without this
the unwinder will use offsets from the stack pointer.
-The syntax of this directive is the same as the @code{sub} or @code{mov}
+The syntax of this directive is the same as the @code{add} or @code{mov}
instruction used to set the frame pointer. @var{spreg} must be either
@code{sp} or mentioned in a previous @code{.movsp} directive.
mov ip, sp
@dots{}
.setfp fp, ip, #4
-sub fp, ip, #4
+add fp, ip, #4
@end smallexample
@cindex @code{.secrel32} directive, ARM
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