-@c Copyright 1996-2013 Free Software Foundation, Inc.
+@c Copyright (C) 1996-2016 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@code{cortex-a8},
@code{cortex-a9},
@code{cortex-a15},
+@code{cortex-a17},
+@code{cortex-a32},
+@code{cortex-a35},
+@code{cortex-a53},
+@code{cortex-a57},
+@code{cortex-a72},
@code{cortex-r4},
@code{cortex-r4f},
@code{cortex-r5},
@code{cortex-r7},
+@code{cortex-r8},
+@code{cortex-m7},
@code{cortex-m4},
@code{cortex-m3},
@code{cortex-m1},
@code{cortex-m0},
@code{cortex-m0plus},
+@code{exynos-m1},
+@code{marvell-pj4},
+@code{marvell-whitney},
+@code{qdf24xx},
+@code{xgene1},
+@code{xgene2},
@code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
@code{i80200} (Intel XScale processor)
@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
The following extensions are currently supported:
+@code{crc}
@code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
@code{fp} (Floating Point Extensions for v8-A architecture),
@code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
@code{iwmmxt},
@code{iwmmxt2},
+@code{xscale},
@code{maverick},
-@code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
+@code{mp} (Multiprocessing Extensions for v7-A and v7-R
+architectures),
@code{os} (Operating System for v6M architecture),
@code{sec} (Security Extensions for v6K and v7-A architectures),
@code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
@code{virt} (Virtualization Extensions for v7-A architecture, implies
@code{idiv}),
+@code{pan} (Priviliged Access Never Extensions for v8-A architecture),
+@code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
+@code{simd})
and
@code{xscale}.
@code{armv6j},
@code{armv6k},
@code{armv6z},
-@code{armv6zk},
+@code{armv6kz},
@code{armv6-m},
@code{armv6s-m},
@code{armv7},
@code{armv7-a},
+@code{armv7ve},
@code{armv7-r},
@code{armv7-m},
@code{armv7e-m},
@code{armv8-a},
+@code{armv8.1-a},
+@code{armv8.2-a},
@code{iwmmxt}
+@code{iwmmxt2}
and
@code{xscale}.
If both @code{-mcpu} and
@code{vfpv4},
@code{vfpv4-d16},
@code{fpv4-sp-d16},
+@code{fpv5-sp-d16},
+@code{fpv5-d16},
@code{fp-armv8},
@code{arm1020t},
@code{arm1020e},
@code{neon},
@code{neon-vfpv4},
@code{neon-fp-armv8},
+@code{crypto-neon-fp-armv8},
+@code{neon-fp-armv8.1}
and
-@code{crypto-neon-fp-armv8}.
+@code{crypto-neon-fp-armv8.1}.
In addition to determining which instructions are assembled, this option
also affects the way in which the @code{.double} assembler directive behaves
This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.
+Note: If a program is being built for a system with big-endian data
+and little-endian instructions then it should be assembled with the
+@option{-EB} option, (all of it, code and data) and then linked with
+the @option{--be8} option. This will reverse the endianness of the
+instructions back to little-endian, but leave the data as big-endian.
+
@cindex @code{-EL} command line option, ARM
@item -EL
This option specifies that the output generated by the assembler should
Enable or disable warnings about using deprecated options or
features. The default is to warn.
+@cindex @code{-mccs} command line option, ARM
+@item -mccs
+Turns on CodeComposer Studio assembly syntax compatibility mode.
+
+@cindex @code{-mwarn-syms} command line option, ARM
+@item -mwarn-syms
+@itemx -mno-warn-syms
+Enable or disable warnings about symbols that match the names of ARM
+instructions. The default is to warn.
+
@end table
MOVT r0, #:upper16:foo
@end smallexample
+Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
+@samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
+generated by prefixing the value with @samp{#:lower0_7:#},
+@samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
+respectively. For example to load the 32-bit address of foo into r0:
+
+@smallexample
+ MOVS r0, #:upper8_15:#foo
+ LSLS r0, r0, #8
+ ADDS r0, #:upper0_7:#foo
+ LSLS r0, r0, #8
+ ADDS r0, #:lower8_15:#foo
+ LSLS r0, r0, #8
+ ADDS r0, #:lower0_7:#foo
+@end smallexample
+
@node ARM-Neon-Alignment
@subsection NEON Alignment Specifiers
@item .arm
This performs the same action as @var{.code 32}.
-@anchor{arm_pad}
-@cindex @code{.pad} directive, ARM
-@item .pad #@var{count}
-Generate unwinder annotations for a stack adjustment of @var{count} bytes.
-A positive value indicates the function prologue allocated stack space by
-decrementing the stack pointer.
-
@c BBBBBBBBBBBBBBBBBBBBBBBBBB
@cindex @code{.bss} directive, ARM
output section. These are not compatible with current ARM processors
or ABIs.
+@anchor{arm_pad}
@cindex @code{.pad} directive, ARM
@item .pad #@var{count}
Generate unwinder annotations for a stack adjustment of @var{count} bytes.
know more about the object-file format used to represent unwind
information, you may consult the @cite{Exception Handling ABI for the
ARM Architecture} available from @uref{http://infocenter.arm.com}.
+
projects / deliverable / binutils-gdb.git / blobdiff