Add MIPS32 DSPr3 support.

[deliverable/binutils-gdb.git] / gas / doc / c-arm.texi

diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index f07aa62bd41064ccb1e121680d9a86962d6fc0b2..7e4863ea992387ace7a785f759e93379430cd336 100644 (file)
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -1,4 +1,4 @@
-@c Copyright (C) 1996-2015 Free Software Foundation, Inc.
+@c Copyright (C) 1996-2016 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 
@@ -119,6 +119,9 @@ recognized:
 @code{cortex-a8},
 @code{cortex-a9},
 @code{cortex-a15},
+@code{cortex-a17},
+@code{cortex-a32},
+@code{cortex-a35},
 @code{cortex-a53},
 @code{cortex-a57},
 @code{cortex-a72},
@@ -126,6 +129,7 @@ recognized:
 @code{cortex-r4f},
 @code{cortex-r5},
 @code{cortex-r7},
+@code{cortex-r8},
 @code{cortex-m7},
 @code{cortex-m4},
 @code{cortex-m3},
@@ -135,6 +139,7 @@ recognized:
 @code{exynos-m1},
 @code{marvell-pj4},
 @code{marvell-whitney},
+@code{qdf24xx},
 @code{xgene1},
 @code{xgene2},
 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
@@ -179,6 +184,9 @@ architectures),
 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
 @code{virt} (Virtualization Extensions for v7-A architecture, implies
 @code{idiv}),
+@code{pan} (Priviliged Access Never Extensions for v8-A architecture),
+@code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
+@code{simd})
 and
 @code{xscale}.
 
@@ -207,7 +215,7 @@ names are recognized:
 @code{armv6j},
 @code{armv6k},
 @code{armv6z},
-@code{armv6zk},
+@code{armv6kz},
 @code{armv6-m},
 @code{armv6s-m},
 @code{armv7},
@@ -217,6 +225,8 @@ names are recognized:
 @code{armv7-m},
 @code{armv7e-m},
 @code{armv8-a},
+@code{armv8.1-a},
+@code{armv8.2-a},
 @code{iwmmxt}
 @code{iwmmxt2}
 and
@@ -270,8 +280,10 @@ The following format options are recognized:
 @code{neon},
 @code{neon-vfpv4},
 @code{neon-fp-armv8},
+@code{crypto-neon-fp-armv8},
+@code{neon-fp-armv8.1}
 and
-@code{crypto-neon-fp-armv8}.
+@code{crypto-neon-fp-armv8.1}.
 
 In addition to determining which instructions are assembled, this option
 also affects the way in which the @code{.double} assembler directive behaves
@@ -394,6 +406,12 @@ features.  The default is to warn.
 @item -mccs
 Turns on CodeComposer Studio assembly syntax compatibility mode.
 
+@cindex @code{-mwarn-syms} command line option, ARM
+@item -mwarn-syms
+@itemx -mno-warn-syms
+Enable or disable warnings about symbols that match the names of ARM
+instructions.  The default is to warn.
+
 @end table
 
 
@@ -522,6 +540,22 @@ respectively.  For example to load the 32-bit address of foo into r0:
         MOVT r0, #:upper16:foo
 @end smallexample
 
+Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
+@samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
+generated by prefixing the value with @samp{#:lower0_7:#},
+@samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
+respectively.  For example to load the 32-bit address of foo into r0:
+
+@smallexample
+        MOVS r0, #:upper8_15:#foo
+        LSLS r0, r0, #8
+        ADDS r0, #:upper0_7:#foo
+        LSLS r0, r0, #8
+        ADDS r0, #:lower8_15:#foo
+        LSLS r0, r0, #8
+        ADDS r0, #:lower0_7:#foo
+@end smallexample
+
 @node ARM-Neon-Alignment
 @subsection NEON Alignment Specifiers
 
@@ -1206,3 +1240,4 @@ code that calls functions which may throw exceptions.  If you need to
 know more about the object-file format used to represent unwind
 information, you may consult the @cite{Exception Handling ABI for the
 ARM Architecture} available from @uref{http://infocenter.arm.com}.
+