gdb: check for partial symtab presence in dwarf2_initialize_objfile

[deliverable/binutils-gdb.git] / gas / doc / c-arm.texi

diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index fa642177b2c3b7605feecce37d8b4d21fb1a1e0a..91803605775418bcc795e163f42b0beaec880967 100644 (file)
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -1,4 +1,4 @@
-@c Copyright (C) 1996-2019 Free Software Foundation, Inc.
+@c Copyright (C) 1996-2020 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 
@@ -129,6 +129,8 @@ recognized:
 @code{cortex-a73},
 @code{cortex-a75},
 @code{cortex-a76},
+@code{cortex-a76ae},
+@code{cortex-a77},
 @code{ares},
 @code{cortex-r4},
 @code{cortex-r4f},
@@ -136,6 +138,7 @@ recognized:
 @code{cortex-r7},
 @code{cortex-r8},
 @code{cortex-r52},
+@code{cortex-m35p},
 @code{cortex-m33},
 @code{cortex-m23},
 @code{cortex-m7},
@@ -177,6 +180,8 @@ been added, again in ascending alphabetical order.  For example,
 
 
 The following extensions are currently supported:
+@code{bf16} (BFloat16 extensions for v8.6-A architecture),
+@code{i8mm} (Int8 Matrix Multiply extensions for v8.6-A architecture),
 @code{crc}
 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
 @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
@@ -251,6 +256,7 @@ names are recognized:
 @code{armv8-m.base},
 @code{armv8-m.main},
 @code{armv8.1-m.main},
+@code{armv8.6-a},
 @code{iwmmxt},
 @code{iwmmxt2}
 and
@@ -353,6 +359,14 @@ For @code{armv8-m.main}:
 @code{+fp}: Enables single-precision only VFPv5 instructions with 16
 double-word registers.
 @code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers.
+@code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0),
+@code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1),
+@code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2),
+@code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3),
+@code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4),
+@code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5),
+@code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6),
+@code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7),
 @code{+nofp}: Disables all FPU instructions.
 @code{+nodsp}: Disables DSP Extension.
 
@@ -493,6 +507,22 @@ The default is dependent on the processor selected.  For Architecture 5 or
 later, the default is to assemble for VFP instructions; for earlier
 architectures the default is to assemble for FPA instructions.
 
+@cindex @code{-mfp16-format=} command-line option
+@item -mfp16-format=@var{format}
+This option specifies the half-precision floating point format to use
+when assembling floating point numbers emitted by the @code{.float16}
+directive.
+The following format options are recognized:
+@code{ieee},
+@code{alternative}.
+If @code{ieee} is specified then the IEEE 754-2008 half-precision floating
+point format is used, if @code{alternative} is specified then the Arm
+alternative half-precision format is used. If this option is set on the
+command line then the format is fixed and cannot be changed with
+the @code{float16_format} directive. If this value is not set then
+the IEEE 754-2008 format is used until the format is explicitly set with
+the @code{float16_format} directive.
+
 @cindex @code{-mthumb} command-line option, ARM
 @item -mthumb
 This option specifies that the assembler should start assembling Thumb
@@ -934,6 +964,23 @@ or ABIs.
 
 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
 
+@cindex @code{.float16} directive, ARM
+@item .float16 @var{value [,...,value_n]}
+Place the half precision floating point representation of one or more
+floating-point values into the current section. The exact format of the
+encoding is specified by @code{.float16_format}. If the format has not
+been explicitly set yet (either via the @code{.float16_format} directive or
+the command line option) then the IEEE 754-2008 format is used.
+
+@cindex @code{.float16_format} directive, ARM
+@item .float16_format @var{format}
+Set the format to use when encoding float16 values emitted by
+the @code{.float16} directive.
+Once the format has been set it cannot be changed.
+@code{format} should be one of the following: @code{ieee} (encode in
+the IEEE 754-2008 half precision format) or @code{alternative} (encode in
+the Arm alternative half precision format).
+
 @anchor{arm_fnend}
 @cindex @code{.fnend} directive, ARM
 @item .fnend