[ARM] Support for ARMv8.1 Adv.SIMD extension

[deliverable/binutils-gdb.git] / gas / doc / c-arm.texi

diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index b4b2d953e68893a3736d87aabfa843d2ba72f237..afbd9f96c43e07d246e7cca75057fa4e763bb0b4 100644 (file)
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -1,4 +1,4 @@
-@c Copyright 1996-2013 Free Software Foundation, Inc.
+@c Copyright (C) 1996-2015 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 
@@ -119,15 +119,24 @@ recognized:
 @code{cortex-a8},
 @code{cortex-a9},
 @code{cortex-a15},
+@code{cortex-a53},
+@code{cortex-a57},
+@code{cortex-a72},
 @code{cortex-r4},
 @code{cortex-r4f},
 @code{cortex-r5},
 @code{cortex-r7},
+@code{cortex-m7},
 @code{cortex-m4},
 @code{cortex-m3},
 @code{cortex-m1},
 @code{cortex-m0},
 @code{cortex-m0plus},
+@code{exynos-m1},
+@code{marvell-pj4},
+@code{marvell-whitney},
+@code{xgene1},
+@code{xgene2},
 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
 @code{i80200} (Intel XScale processor)
 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
@@ -155,18 +164,24 @@ been added, again in ascending alphabetical order.  For example,
 
 
 The following extensions are currently supported:
+@code{crc}
 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
 @code{fp} (Floating Point Extensions for v8-A architecture),
 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
 @code{iwmmxt},
 @code{iwmmxt2},
+@code{xscale},
 @code{maverick},
-@code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
+@code{mp} (Multiprocessing Extensions for v7-A and v7-R
+architectures),
 @code{os} (Operating System for v6M architecture),
 @code{sec} (Security Extensions for v6K and v7-A architectures),
 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
 @code{virt} (Virtualization Extensions for v7-A architecture, implies
 @code{idiv}),
+@code{pan} (Priviliged Access Never Extensions for v8-A architecture),
+@code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
+@code{simd})
 and
 @code{xscale}.
 
@@ -206,6 +221,7 @@ names are recognized:
 @code{armv7e-m},
 @code{armv8-a},
 @code{iwmmxt}
+@code{iwmmxt2}
 and
 @code{xscale}.
 If both @code{-mcpu} and
@@ -247,6 +263,8 @@ The following format options are recognized:
 @code{vfpv4},
 @code{vfpv4-d16},
 @code{fpv4-sp-d16},
+@code{fpv5-sp-d16},
+@code{fpv5-d16},
 @code{fp-armv8},
 @code{arm1020t},
 @code{arm1020e},
@@ -255,8 +273,9 @@ The following format options are recognized:
 @code{neon},
 @code{neon-vfpv4},
 @code{neon-fp-armv8},
-and
 @code{crypto-neon-fp-armv8}.
+and
+@code{neon-fp-armv8-1},
 
 In addition to determining which instructions are assembled, this option
 also affects the way in which the @code{.double} assembler directive behaves
@@ -347,6 +366,12 @@ and
 This option specifies that the output generated by the assembler should
 be marked as being encoded for a big-endian processor.
 
+Note: If a program is being built for a system with big-endian data
+and little-endian instructions then it should be assembled with the
+@option{-EB} option, (all of it, code and data) and then linked with
+the @option{--be8} option.  This will reverse the endianness of the
+instructions back to little-endian, but leave the data as big-endian.
+
 @cindex @code{-EL} command line option, ARM
 @item -EL
 This option specifies that the output generated by the assembler should
@@ -369,6 +394,16 @@ the linker option of the same name.
 Enable or disable warnings about using deprecated options or
 features.  The default is to warn.
 
+@cindex @code{-mccs} command line option, ARM
+@item -mccs
+Turns on CodeComposer Studio assembly syntax compatibility mode.
+
+@cindex @code{-mwarn-syms} command line option, ARM
+@item -mwarn-syms
+@itemx -mno-warn-syms
+Enable or disable warnings about symbols that match the names of ARM
+instructions.  The default is to warn.
+
 @end table
 
 
@@ -564,13 +599,6 @@ incrementally to the architecture being compiled for.
 @item .arm
 This performs the same action as @var{.code 32}.
 
-@anchor{arm_pad}
-@cindex @code{.pad} directive, ARM
-@item .pad #@var{count}
-Generate unwinder annotations for a stack adjustment of @var{count} bytes.
-A positive value indicates the function prologue allocated stack space by
-decrementing the stack pointer.
-
 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 
 @cindex @code{.bss} directive, ARM
@@ -770,6 +798,7 @@ This directive writes 12-byte packed floating-point values to the
 output section.  These are not compatible with current ARM processors
 or ABIs.
 
+@anchor{arm_pad}
 @cindex @code{.pad} directive, ARM
 @item .pad #@var{count}
 Generate unwinder annotations for a stack adjustment of @var{count} bytes.