-@c Copyright 1996, 1997, 1998, 1999, 2000, 2001
+@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
* ARM Floating Point:: Floating Point
* ARM Directives:: ARM Machine Directives
* ARM Opcodes:: Opcodes
+* ARM Mapping Symbols:: Mapping Symbols
@end menu
@node ARM Options
@table @code
@cindex @code{-mcpu=} command line option, ARM
-@item -mcpu=@var{processor}[+@var{extension}@dots]
+@item -mcpu=@var{processor}[+@var{extension}@dots{}]
This option specifies the target processor. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
@code{arm940t},
@code{arm9tdmi},
@code{arm9e},
+@code{arm926e},
+@code{arm926ejs},
@code{arm946e-r0},
@code{arm946e},
@code{arm966e-r0},
@code{arm10e},
@code{arm1020},
@code{arm1020t},
-@code{arm1020e},
+@code{arm1020e},
+@code{arm1026ejs},
+@code{arm1136js},
+@code{arm1136jfs},
@code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
@code{i80200} (Intel XScale processor)
+@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
and
@code{xscale}.
The special name @code{all} may be used to allow the
is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
are currently supported:
@code{+maverick}
+@code{+iwmmxt}
and
@code{+xscale}.
@cindex @code{-march=} command line option, ARM
-@item -march=@var{architecture}[+@var{extension}@dots]
+@item -march=@var{architecture}[+@var{extension}@dots{}]
This option specifies the target architecture. The assembler will issue
an error message if an attempt is made to assemble an instruction which
will not execute on the target architecture. The following architecture
@code{armv5t},
@code{armv5txm},
@code{armv5te},
-@code{armv5texp}
+@code{armv5texp},
+@code{armv6},
+@code{armv6j},
+@code{iwmmxt}
and
@code{xscale}.
If both @code{-mcpu} and
The following format options are recognized:
@code{softfpa},
@code{fpe},
+@code{fpe2},
+@code{fpe3},
@code{fpa},
@code{fpa10},
@code{fpa11},
@code{vfp10-r0},
@code{vfp9},
@code{vfpxd},
-@code{arm1020t}
+@code{arm1020t},
+@code{arm1020e},
+@code{arm1136jfs}
and
-@code{arm1020e}.
+@code{maverick}.
In addition to determining which instructions are assembled, this option
also affects the way in which the @code{.double} assembler directive behaves
@cindex @code{-mapcs-float} command line option, ARM
@item -mapcs-float
-This indicates the the floating point variant of the APCS should be
+This indicates the floating point variant of the APCS should be
used. In this variant floating point arguments are passed in FP
registers rather than integer registers.
This indicates that the reentrant variant of the APCS should be used.
This variant supports position independent code.
+@cindex @code{-mfloat-abi=} command line option, ARM
+@item -mfloat-abi=@var{abi}
+This option specifies that the output generated by the assembler should be
+marked as using specified floating point ABI.
+The following values are recognized:
+@code{soft},
+@code{softfp}
+and
+@code{hard}.
+
+@cindex @code{-eabi=} command line option, ARM
+@item -meabi=@var{ver}
+This option specifies which EABI version the produced object files should
+conform to.
+The following values are recognised:
+@code{gnu}
+and
+@code{3}.
+
@cindex @code{-EB} command line option, ARM
@item -EB
This option specifies that the output generated by the assembler should
This is the generic @var{.align} directive. For the ARM however if the
first argument is zero (ie no alignment is needed) the assembler will
behave as if the argument had been 2 (ie pad to the next four byte
-boundary). This is for compatability with ARM's own assembler.
+boundary). This is for compatibility with ARM's own assembler.
@cindex @code{req} directive, ARM
@item @var{name} .req @var{register name}
foo .req r0
@end smallexample
+@cindex @code{unreq} directive, ARM
+@item .unreq @var{alias-name}
+This undefines a register alias which was previously defined using the
+@code{req} directive. For example:
+
+@smallexample
+ foo .req r0
+ .unreq foo
+@end smallexample
+
+An error occurs if the name is undefined. Note - this pseudo op can
+be used to delete builtin in register name aliases (eg 'r0'). This
+should only be done if it is really necessary.
+
@cindex @code{code} directive, ARM
@item .code @code{[16|32]}
This directive selects the instruction set being generated. The value 16
This directive causes the current contents of the literal pool to be
dumped into the current section (which is assumed to be the .text
section) at the current location (aligned to a word boundary).
+@code{GAS} maintains a separate literal pool for each section and each
+sub-section. The @code{.ltorg} directive will only affect the literal
+pool of the current section and sub-section. At the end of assembly
+all remaining, un-empty literal pools will automatically be dumped.
+
+Note - older versions of @code{GAS} would dump the current literal
+pool any time a section change occurred. This is no longer done, since
+it prevents accurate control of the placement of literal pools.
@cindex @code{.pool} directive, ARM
@item .pool
Software Development Toolkit Reference Manual}, Advanced RISC Machines
Ltd.
+@node ARM Mapping Symbols
+@section Mapping Symbols
+
+The ARM ELF specification requires that special symbols be inserted
+into object files to mark certain features:
+
+@table @code
+
+@cindex @code{$a}
+@item $a
+At the start of a region of code containing ARM instructions.
+
+@cindex @code{$t}
+@item $t
+At the start of a region of code containing THUMB instructions.
+
+@cindex @code{$d}
+@item $d
+At the start of a region of data.
+
+@end table
+
+The assembler will automatically insert these symbols for you - there
+is no need to code them yourself. Support for tagging symbols ($b,
+$f, $p and $m) which is also mentioned in the current ARM ELF
+specification is not implemented. This is because they have been
+dropped from the new EABI and so tools cannot rely upon their
+presence.
+
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