Add AMD bdver3 support.

[deliverable/binutils-gdb.git] / gas / doc / c-i386.texi

diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 1bdb1fab801c6a68b22a98feeb75b84b5ea65668..4ee8d7a23124795c07f4eae4862bf4b29e489407 100644 (file)
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -111,6 +111,7 @@ processor names are recognized:
 @code{core2},
 @code{corei7},
 @code{l1om},
+@code{k1om},
 @code{k6},
 @code{k6_2},
 @code{athlon},
@@ -119,6 +120,9 @@ processor names are recognized:
 @code{amdfam10},
 @code{bdver1},
 @code{bdver2},
+@code{bdver3},
+@code{btver1},
+@code{btver2},
 @code{generic32} and
 @code{generic64}.
 
@@ -142,8 +146,12 @@ accept various extension mnemonics.  For example,
 @code{nosse},
 @code{avx},
 @code{avx2},
+@code{adx},
+@code{rdseed},
+@code{prfchw},
 @code{noavx},
 @code{vmx},
+@code{vmfunc},
 @code{smx},
 @code{xsave},
 @code{xsaveopt},
@@ -157,11 +165,14 @@ accept various extension mnemonics.  For example,
 @code{movbe},
 @code{ept},
 @code{lzcnt},
+@code{hle},
+@code{rtm},
 @code{invpcid},
 @code{clflush},
 @code{lwp},
 @code{fma4},
 @code{xop},
+@code{cx16},
 @code{syscall},
 @code{rdtscp},
 @code{3dnow},
@@ -210,7 +221,7 @@ for any SSE intruction.
 @cindex @samp{-mavxscalar=} option, x86-64
 @item -mavxscalar=@var{128}
 @itemx -mavxscalar=@var{256}
-This options control how the assembler should encode scalar AVX
+These options control how the assembler should encode scalar AVX
 instructions.  @option{-mavxscalar=@var{128}} will encode scalar
 AVX instructions with 128bit vector length, which is the default.
 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
@@ -438,8 +449,8 @@ quadruple word).
 
 Different encoding options can be specified via optional mnemonic
 suffix.  @samp{.s} suffix swaps 2 register operands in encoding when
-moving from one register to another.  @samp{.d32} suffix forces 32bit
-displacement in encoding.
+moving from one register to another.  @samp{.d8} or @samp{.d32} suffix
+prefers 8bit or 32bit displacement in encoding.
 
 @cindex conversion instructions, i386
 @cindex i386 conversion instructions
@@ -1003,9 +1014,10 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
-@item @samp{corei7} @tab @samp{l1om}
+@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
-@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2}
+@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
+@item @samp{btver1} @tab @samp{btver2}
 @item @samp{generic32} @tab @samp{generic64}
 @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
@@ -1013,10 +1025,11 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
-@item @samp{.lzcnt} @tab @samp{.invpcid}
+@item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
+@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
-@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
+@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
 @item @samp{.padlock}
 @end multitable