x86: support further AMD Zen2 instructions

[deliverable/binutils-gdb.git] / gas / doc / c-i386.texi

diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index b0ec3418de23b1e13fddbcfc7a1ecba9e87afaf0..589b4260f03f31aeb69d54e16caa4398e2465202 100644 (file)
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -217,6 +217,7 @@ accept various extension mnemonics.  For example,
 @code{noavx512_bitalg},
 @code{noavx512_vp2intersect},
 @code{noavx512_bf16},
+@code{noenqcmd},
 @code{vmx},
 @code{vmfunc},
 @code{smx},
@@ -244,6 +245,8 @@ accept various extension mnemonics.  For example,
 @code{pconfig},
 @code{waitpkg},
 @code{cldemote},
+@code{rdpru},
+@code{mcommit},
 @code{lwp},
 @code{fma4},
 @code{xop},
@@ -302,6 +305,9 @@ AVX instructions with 128bit vector length, which is the default.
 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
 with 256bit vector length.
 
+WARNING: Don't use this for production code - due to CPU errata the
+resulting code may not work on certain models.
+
 @cindex @samp{-mvexwig=} option, i386
 @cindex @samp{-mvexwig=} option, x86-64
 @item -mvexwig=@var{0}
@@ -312,6 +318,9 @@ instructions with vex.w = 0, which is the default.
 @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with
 vex.w = 1.
 
+WARNING: Don't use this for production code - due to CPU errata the
+resulting code may not work on certain models.
+
 @cindex @samp{-mevexlig=} option, i386
 @cindex @samp{-mevexlig=} option, x86-64
 @item -mevexlig=@var{128}
@@ -458,13 +467,21 @@ Optimize instruction encoding with smaller instruction size.  @samp{-O}
 and @samp{-O1} encode 64-bit register load instructions with 64-bit
 immediate as 32-bit register load instructions with 31-bit or 32-bits
 immediates, encode 64-bit register clearing instructions with 32-bit
-register clearing instructions and encode 256-bit/512-bit VEX/EVEX
-vector register clearing instructions with 128-bit VEX vector register
-clearing instructions as well as encode 128-bit/256-bit EVEX vector
+register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector
+register clearing instructions with 128-bit VEX vector register
+clearing instructions, encode 128-bit/256-bit EVEX vector
 register load/store instructions with VEX vector register load/store
-instructions.  @samp{-O2} includes @samp{-O1} optimization plus
-encodes 256-bit/512-bit EVEX vector register clearing instructions with
-128-bit EVEX vector register clearing instructions.
+instructions, and encode 128-bit/256-bit EVEX packed integer logical
+instructions with 128-bit/256-bit VEX packed integer logical.
+
+@samp{-O2} includes @samp{-O1} optimization plus encodes
+256-bit/512-bit EVEX vector register clearing instructions with 128-bit
+EVEX vector register clearing instructions.  In 64-bit mode VEX encoded
+instructions with commutative source operands will also have their
+source operands swapped if this allows using the 2-byte VEX prefix form
+instead of the 3-byte one.  Certain forms of AND as well as OR with the
+same (register) operand specified twice will also be changed to TEST.
+
 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
 and 64-bit register tests with immediate as 8-bit register test with
 immediate.  @samp{-O0} turns off this optimization.
@@ -501,6 +518,12 @@ The directive is intended to be used for data which requires a large
 amount of space, and it is only available for ELF based x86_64
 targets.
 
+@cindex @code{value} directive
+@item .value @var{expression} [, @var{expression}]
+This directive behaves in the same way as the @code{.short} directive,
+taking a series of comma separated expressions and storing them as
+two-byte wide values into the current section.
+
 @c FIXME: Document other x86 specific directives ?  Eg: .code16gcc,
 
 @end table
@@ -583,11 +606,16 @@ instruction, do @emph{not} have reversed order.  @ref{i386-Bugs}.
 In AT&T syntax the size of memory operands is determined from the last
 character of the instruction mnemonic.  Mnemonic suffixes of @samp{b},
 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
-(32-bit) and quadruple word (64-bit) memory references.  Intel syntax accomplishes
-this by prefixing memory operands (@emph{not} the instruction mnemonics) with
-@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}.  Thus,
-Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
-syntax.
+(32-bit) and quadruple word (64-bit) memory references.  Mnemonic suffixes
+of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm
+(256-bit vector) and zmm (512-bit vector) memory references, only when there's
+no other way to disambiguate an instruction.  Intel syntax accomplishes this by
+prefixing memory operands (@emph{not} the instruction mnemonics) with
+@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr},
+@samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}.  Thus, Intel
+syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
+syntax.  In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and
+@samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references.
 
 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
 instruction with the 64-bit displacement or immediate operand.
@@ -1315,7 +1343,8 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
-@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
+@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
+@item @samp{.mcommit}
 @end multitable
 
 Apart from the warning, there are only two other effects on