2000-08-11 Kazu Hirata <kazu@hxi.com>

[deliverable/binutils-gdb.git] / gas / doc / c-i386.texi

diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index e27893b892e0ff3d9170d1a548a5e8469f979367..84139db23fe3ee08eb3ea1770e1741954bf6202b 100644 (file)
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -24,6 +24,7 @@
 * i386-Float::                  Floating Point
 * i386-SIMD::                   Intel's MMX and AMD's 3DNow! SIMD Operations
 * i386-16bit::                  Writing 16-bit Code
+* i386-Arch::                   Specifying an x86 CPU architecture
 * i386-Bugs::                   AT&T Syntax bugs
 * i386-Notes::                  Notes
 @end menu
@@ -35,13 +36,23 @@
 @cindex i386 options (none)
 The 80386 has no machine dependent options.
 
+
 @node i386-Syntax
 @section AT&T Syntax versus Intel Syntax
 
+@cindex i386 intel_syntax pseudo op
+@cindex intel_syntax pseudo op, i386
+@cindex i386 att_syntax pseudo op
+@cindex att_syntax pseudo op, i386
 @cindex i386 syntax compatibility
 @cindex syntax compatibility, i386
-In order to maintain compatibility with the output of @code{@value{GCC}},
-@code{@value{AS}} supports AT&T System V/386 assembler syntax.  This is quite
+
+@code{@value{AS}} now supports assembly using Intel assembler syntax.
+@code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
+back to the usual AT&T mode for compatibility with the output of
+@code{@value{GCC}}.  Either of these directives may have an optional
+argument, @code{prefix}, or @code{noprefix} specifying whether registers
+require a @samp{%} prefix.  AT&T System V/386 assembler syntax is quite
 different from Intel syntax.  We mention these differences because
 almost all 80386 documents use Intel syntax.  Notable differences
 between the two syntaxes are:
@@ -443,14 +454,25 @@ instructions is reversed from the Intel syntax.
 @cindex i386 16-bit code
 @cindex 16-bit code, i386
 @cindex real-mode code, i386
+@cindex @code{code16gcc} directive, i386
 @cindex @code{code16} directive, i386
 @cindex @code{code32} directive, i386
 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code,
 it also supports writing code to run in real mode or in 16-bit protected
-mode code segments.  To do this, put a @samp{.code16} directive before
-the assembly language instructions to be run in 16-bit mode.  You can
-switch @code{@value{AS}} back to writing normal 32-bit code with the
-@samp{.code32} directive.
+mode code segments.  To do this, put a @samp{.code16} or
+@samp{.code16gcc} directive before the assembly language instructions to
+be run in 16-bit mode.  You can switch @code{@value{AS}} back to writing
+normal 32-bit code with the @samp{.code32} directive.
+
+@samp{.code16gcc} provides experimental support for generating 16-bit
+code from gcc, and differs from @samp{.code16} in that @samp{call},
+@samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
+@samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
+default to 32-bit size.  This is so that the stack pointer is
+manipulated in the same way over function calls, allowing access to
+function parameters at the same stack offsets as in 32-bit mode.
+@samp{.code16gcc} also automatically adds address size prefixes where
+necessary to use the 32-bit addressing modes that gcc generates.
 
 The code which @code{@value{AS}} generates in 16-bit mode will not
 necessarily run on a 16-bit pre-80386 processor.  To write code that
@@ -495,6 +517,31 @@ non-commutative arithmetic floating point operations with two register
 operands where the source register is @samp{%st} and the destination
 register is @samp{%st(i)}.
 
+@node i386-Arch
+@section Specifying CPU Architecture
+
+@cindex arch directive, i386
+@cindex i386 arch directive
+
+@code{@value{AS}} may be told to assemble for a particular CPU
+architecture with the @code{.arch @var{cpu_type}} directive.  This
+directive enables a warning when gas detects an instruction that is not
+supported on the CPU specified.  The choices for @var{cpu_type} are:
+
+@multitable @columnfractions .20 .20 .20 .20
+@item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
+@item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
+@item @samp{pentiumpro} @tab @samp{k6} @tab @samp{athlon}
+@end multitable
+
+Apart from the warning, there is only one other effect on
+@code{@value{AS}} operation;  If you specify a CPU other than
+@samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
+will automatically use a two byte opcode sequence.  The larger three
+byte opcode sequence is used on the 486 (and when no architecture is
+specified) because it executes faster on the 486.  Note that you can
+explicitly request the two byte opcode by writing @samp{sarl %eax}.
+
 @node i386-Notes
 @section Notes