-@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000,
-@c 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011
-@c Free Software Foundation, Inc.
+@c Copyright (C) 1991-2014 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@c man end
@cindex options for i386
@cindex options for x86-64
@cindex i386 options
-@cindex x86-64 options
+@cindex x86-64 options
The i386 version of @code{@value{AS}} has a few machine
dependent options:
This option specifies the target processor. The assembler will
issue an error message if an attempt is made to assemble an instruction
which will not execute on the target processor. The following
-processor names are recognized:
+processor names are recognized:
@code{i8086},
@code{i186},
@code{i286},
@code{amdfam10},
@code{bdver1},
@code{bdver2},
+@code{bdver3},
+@code{bdver4},
+@code{btver1},
+@code{btver2},
@code{generic32} and
@code{generic64}.
-In addition to the basic instruction set, the assembler can be told to
+In addition to the basic instruction set, the assembler can be told to
accept various extension mnemonics. For example,
@code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
@var{vmx}. The following extensions are currently supported:
@code{nosse},
@code{avx},
@code{avx2},
+@code{adx},
+@code{rdseed},
+@code{prfchw},
+@code{smap},
+@code{mpx},
+@code{sha},
+@code{prefetchwt1},
+@code{clflushopt},
+@code{se1},
+@code{clwb},
+@code{pcommit},
+@code{avx512f},
+@code{avx512cd},
+@code{avx512er},
+@code{avx512pf},
+@code{avx512vl},
+@code{avx512bw},
+@code{avx512dq},
+@code{avx512ifma},
+@code{avx512vbmi},
@code{noavx},
@code{vmx},
+@code{vmfunc},
@code{smx},
@code{xsave},
@code{xsaveopt},
+@code{xsavec},
+@code{xsaves},
@code{aes},
@code{pclmul},
@code{fsgsbase},
@code{movbe},
@code{ept},
@code{lzcnt},
+@code{hle},
+@code{rtm},
@code{invpcid},
@code{clflush},
@code{lwp},
@code{fma4},
@code{xop},
+@code{cx16},
@code{syscall},
@code{rdtscp},
@code{3dnow},
@item -msse-check=@var{none}
@itemx -msse-check=@var{warning}
@itemx -msse-check=@var{error}
-These options control if the assembler should check SSE intructions.
+These options control if the assembler should check SSE instructions.
@option{-msse-check=@var{none}} will make the assembler not to check SSE
instructions, which is the default. @option{-msse-check=@var{warning}}
-will make the assembler issue a warning for any SSE intruction.
+will make the assembler issue a warning for any SSE instruction.
@option{-msse-check=@var{error}} will make the assembler issue an error
-for any SSE intruction.
+for any SSE instruction.
@cindex @samp{-mavxscalar=} option, i386
@cindex @samp{-mavxscalar=} option, x86-64
@option{-mavxscalar=@var{256}} will encode scalar AVX instructions
with 256bit vector length.
+@cindex @samp{-mevexlig=} option, i386
+@cindex @samp{-mevexlig=} option, x86-64
+@item -mevexlig=@var{128}
+@itemx -mevexlig=@var{256}
+@itemx -mevexlig=@var{512}
+These options control how the assembler should encode length-ignored
+(LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
+EVEX instructions with 128bit vector length, which is the default.
+@option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
+encode LIG EVEX instructions with 256bit and 512bit vector length,
+respectively.
+
+@cindex @samp{-mevexwig=} option, i386
+@cindex @samp{-mevexwig=} option, x86-64
+@item -mevexwig=@var{0}
+@itemx -mevexwig=@var{1}
+These options control how the assembler should encode w-ignored (WIG)
+EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
+EVEX instructions with evex.w = 0, which is the default.
+@option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
+evex.w = 1.
+
@cindex @samp{-mmnemonic=} option, i386
@cindex @samp{-mmnemonic=} option, x86-64
@item -mmnemonic=@var{att}
@itemx -mmnemonic=@var{intel}
-This option specifies instruction mnemonic for matching instructions.
+This option specifies instruction mnemonic for matching instructions.
The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
take precedent.
@cindex @samp{-msyntax=} option, x86-64
@item -msyntax=@var{att}
@itemx -msyntax=@var{intel}
-This option specifies instruction syntax when processing instructions.
+This option specifies instruction syntax when processing instructions.
The @code{.att_syntax} and @code{.intel_syntax} directives will
take precedent.
This opetion specifies that registers don't require a @samp{%} prefix.
The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
+@cindex @samp{-madd-bnd-prefix} option, i386
+@cindex @samp{-madd-bnd-prefix} option, x86-64
+@item -madd-bnd-prefix
+This option forces the assembler to add BND prefix to all branches, even
+if such prefix was not explicitly specified in the source code.
+
+@cindex @samp{-mbig-obj} option, x86-64
+@item -mbig-obj
+On x86-64 PE/COFF target this option forces the use of big object file
+format, which allows more than 32768 sections.
+
+@cindex @samp{-momit-lock-prefix=} option, i386
+@cindex @samp{-momit-lock-prefix=} option, x86-64
+@item -momit-lock-prefix=@var{no}
+@itemx -momit-lock-prefix=@var{yes}
+These options control how the assembler should encode lock prefix.
+This option is intended as a workaround for processors, that fail on
+lock prefix. This option can only be safely used with single-core,
+single-thread computers
+@option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
+@option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
+which is the default.
+
+@cindex @samp{-mevexrcig=} option, i386
+@cindex @samp{-mevexrcig=} option, x86-64
+@item -mevexrcig=@var{rne}
+@itemx -mevexrcig=@var{rd}
+@itemx -mevexrcig=@var{ru}
+@itemx -mevexrcig=@var{rz}
+These options control how the assembler should encode SAE-only
+EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
+of EVEX instruction with 00, which is the default.
+@option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
+and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
+with 01, 10 and 11 RC bits, respectively.
+
@end table
@c man end
Different encoding options can be specified via optional mnemonic
suffix. @samp{.s} suffix swaps 2 register operands in encoding when
-moving from one register to another. @samp{.d32} suffix forces 32bit
-displacement in encoding.
+moving from one register to another. @samp{.d8} or @samp{.d32} suffix
+prefers 8bit or 32bit displacement in encoding.
@cindex conversion instructions, i386
@cindex i386 conversion instructions
BMI instructions provide several instructions implementing individual
bit manipulation operations such as isolation, masking, setting, or
-resetting.
+resetting.
@c Need to add a specification citation here when available.
@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om}
@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
-@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2}
+@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
+@item @samp{bdver4} @tab @samp{btver1} @tab @samp{btver2}
@item @samp{generic32} @tab @samp{generic64}
@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3}
@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
@item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
@item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
-@item @samp{.lzcnt} @tab @samp{.invpcid}
+@item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
+@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
+@item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
+@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
+@item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
+@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
+@item @samp{.avx512vbmi} @tab @samp{.clwb} @tab @samp{.pcommit}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
-@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
+@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
@item @samp{.padlock}
@end multitable
projects / deliverable / binutils-gdb.git / blobdiff