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[deliverable/binutils-gdb.git] / gas / doc / c-i860.texi

diff --git a/gas/doc/c-i860.texi b/gas/doc/c-i860.texi
index 9f868c975a910fd99ecf231cdeb8a2eac1a7be12..22f13778f064493f80671c5be3b4c90ccb515901 100644 (file)
--- a/gas/doc/c-i860.texi
+++ b/gas/doc/c-i860.texi
@@ -104,6 +104,14 @@ Change the temporary register used when expanding pseudo operations. The
 default register is @code{r31}.
 @end table
 
+The @code{.dual}, @code{.enddual}, and @code{.atmp} directives are available only in the Intel syntax mode.
+
+Both syntaxes allow for the standard @code{.align} directive.  However,
+the Intel syntax additionally allows keywords for the alignment
+parameter: "@code{.align type}", where `type' is one of @code{.short}, @code{.long},
+@code{.quad}, @code{.single}, @code{.double} representing alignments of 2, 4,
+16, 4, and 8, respectively.
+
 @node Opcodes for i860
 @section i860 Opcodes
 
@@ -128,10 +136,10 @@ or large_imm@@l,%rn,%rn
 @end smallexample
 @item Load/store with relocatable address expression:
 
-For example, the pseudo-instruction @code{ld.b addr,%rn} 
+For example, the pseudo-instruction @code{ld.b addr_exp(%rx),%rn} 
 will be expanded into:
 @smallexample
-orh addr_exp@@ha,%r0,%r31
+orh addr_exp@@ha,%rx,%r31
 ld.l addr_exp@@l(%r31),%rn
 @end smallexample