* MIPS Object:: ECOFF object code
* MIPS Stabs:: Directives for debugging information
* MIPS ISA:: Directives to override the ISA level
+* MIPS symbol sizes:: Directives to override the size of symbols
* MIPS autoextend:: Directives for extending MIPS 16 bit instructions
* MIPS insn:: Directive to mark data as an instruction
* MIPS option stack:: Directives to save and restore options
* MIPS ASE instruction generation overrides:: Directives to control
generation of MIPS ASE instructions
+* MIPS floating-point:: Directives to override floating-point options
@end menu
@node MIPS Opts
tools, which must be configured for one or the other). Use @samp{-EB}
to select big-endian output, and @samp{-EL} for little-endian.
+@item -KPIC
+@cindex PIC selection, MIPS
+@cindex @option{-KPIC} option, MIPS
+Generate SVR4-style PIC. This option tells the assembler to generate
+SVR4-style position-independent macro expansions. It also tells the
+assembler to mark the output file as PIC.
+
+@item -mvxworks-pic
+@cindex @option{-mvxworks-pic} option, MIPS
+Generate VxWorks PIC. This option tells the assembler to generate
+VxWorks-style position-independent macro expansions.
+
@cindex MIPS architecture options
@item -mips1
@itemx -mips2
all times. @samp{-mgp32} controls the size of general-purpose registers
and @samp{-mfp32} controls the size of floating-point registers.
+The @code{.set gp=32} and @code{.set fp=32} directives allow the size
+of registers to be changed for parts of an object. The default value is
+restored by @code{.set gp=default} and @code{.set fp=default}.
+
On some MIPS variants there is a 32-bit mode flag; when this flag is
set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
save the 32-bit registers on a context switch, so it is essential never
to use the 64-bit registers.
@item -mgp64
-Assume that 64-bit general purpose registers are available. This is
-provided in the interests of symmetry with -gp32.
+@itemx -mfp64
+Assume that 64-bit registers are available. This is provided in the
+interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
+
+The @code{.set gp=64} and @code{.set fp=64} directives allow the size
+of registers to be changed for parts of an object. The default value is
+restored by @code{.set gp=default} and @code{.set fp=default}.
@item -mips16
@itemx -no-mips16
Generate code for the MIPS 16 processor. This is equivalent to putting
-@samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
+@code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
turns off this option.
+@item -msmartmips
+@itemx -mno-smartmips
+Enables the SmartMIPS extensions to the MIPS32 instruction set, which
+provides a number of new instructions which target smartcard and
+cryptographic applications. This is equivalent to putting
+@code{.set smartmips} at the start of the assembly file.
+@samp{-mno-smartmips} turns off this option.
+
@item -mips3d
@itemx -no-mips3d
Generate code for the MIPS-3D Application Specific Extension.
This tells the assembler to accept MDMX instructions.
@samp{-no-mdmx} turns off this option.
+@item -mdsp
+@itemx -mno-dsp
+Generate code for the DSP Release 1 Application Specific Extension.
+This tells the assembler to accept DSP Release 1 instructions.
+@samp{-mno-dsp} turns off this option.
+
+@item -mdspr2
+@itemx -mno-dspr2
+Generate code for the DSP Release 2 Application Specific Extension.
+This option implies -mdsp.
+This tells the assembler to accept DSP Release 2 instructions.
+@samp{-mno-dspr2} turns off this option.
+
+@item -mmt
+@itemx -mno-mt
+Generate code for the MT Application Specific Extension.
+This tells the assembler to accept MT instructions.
+@samp{-mno-mt} turns off this option.
+
@item -mfix7000
@itemx -mno-fix7000
Cause nops to be inserted if the read of the destination register
intended to be used on GCC-generated code: it is not designed to catch
all problems in hand-written assembler code.
+@item -mfix-vr4130
+@itemx -no-mfix-vr4130
+Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
+
@item -m4010
@itemx -no-m4010
Generate code for the LSI @sc{r4010} chip. This tells the assembler to
rm9000,
10000,
12000,
-mips32-4k,
-sb1
+4kc,
+4km,
+4kp,
+4ksc,
+4kec,
+4kem,
+4kep,
+4ksd,
+m4k,
+m4kp,
+24kc,
+24kf2_1,
+24kf,
+24kf1_1,
+24kec,
+24kef2_1,
+24kef,
+24kef1_1,
+34kc,
+34kf2_1,
+34kf,
+34kf1_1,
+74kc,
+74kf2_1,
+74kf,
+74kf1_1,
+74kf3_2,
+5kc,
+5kf,
+20kc,
+25kf,
+sb1,
+sb1a,
+loongson2e,
+loongson2f,
+octeon
@end quotation
+For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
+accepted as synonyms for @samp{@var{n}f1_1}. These values are
+deprecated.
+
@item -mtune=@var{cpu}
Schedule and tune for a particular MIPS cpu. Valid @var{cpu} values are
identical to @samp{-march=@var{cpu}}.
Record which ABI the source code uses. The recognized arguments
are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
+@item -msym32
+@itemx -mno-sym32
+@cindex -msym32
+@cindex -mno-sym32
+Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
+the beginning of the assembler input. @xref{MIPS symbol sizes}.
+
@cindex @code{-nocpp} ignored (MIPS)
@item -nocpp
This option is ignored. It is accepted for command-line compatibility with
@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
@sc{gnu} assembler itself never runs the C preprocessor.
+@item -msoft-float
+@itemx -mhard-float
+Disable or enable floating-point instructions. Note that by default
+floating-point instructions are always allowed even with CPU targets
+that don't have support for these instructions.
+
+@item -msingle-float
+@itemx -mdouble-float
+Disable or enable double-precision floating-point operations. Note
+that by default double-precision floating-point operations are always
+allowed even with CPU targets that don't have support for these
+operations.
+
@item --construct-floats
@itemx --no-construct-floats
-@cindex --construct-floats
-@cindex --no-construct-floats
The @code{--no-construct-floats} option disables the construction of
double width floating point constants by loading the two halves of the
value into the two single width floating point registers that make up
@itemx -mno-pdr
Control generation of @code{.pdr} sections. Off by default on IRIX, on
elsewhere.
+
+@item -mshared
+@itemx -mno-shared
+When generating code using the Unix calling conventions (selected by
+@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
+which can go into a shared library. The @samp{-mno-shared} option
+tells gas to generate code which uses the calling convention, but can
+not go into a shared library. The resulting code is slightly more
+efficient. This option only affects the handling of the
+@samp{.cpload} and @samp{.cpsetup} pseudo-ops.
@end table
@node MIPS Object
support C++ debugging). These directives are primarily used by compilers, not
assembly language programmers!
+@node MIPS symbol sizes
+@section Directives to override the size of symbols
+
+@cindex @code{.set sym32}
+@cindex @code{.set nosym32}
+The n64 ABI allows symbols to have any 64-bit value. Although this
+provides a great deal of flexibility, it means that some macros have
+much longer expansions than their 32-bit counterparts. For example,
+the non-PIC expansion of @samp{dla $4,sym} is usually:
+
+@smallexample
+lui $4,%highest(sym)
+lui $1,%hi(sym)
+daddiu $4,$4,%higher(sym)
+daddiu $1,$1,%lo(sym)
+dsll32 $4,$4,0
+daddu $4,$4,$1
+@end smallexample
+
+whereas the 32-bit expansion is simply:
+
+@smallexample
+lui $4,%hi(sym)
+daddiu $4,$4,%lo(sym)
+@end smallexample
+
+n64 code is sometimes constructed in such a way that all symbolic
+constants are known to have 32-bit values, and in such cases, it's
+preferable to use the 32-bit expansion instead of the 64-bit
+expansion.
+
+You can use the @code{.set sym32} directive to tell the assembler
+that, from this point on, all expressions of the form
+@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
+have 32-bit values. For example:
+
+@smallexample
+.set sym32
+dla $4,sym
+lw $4,sym+16
+sw $4,sym+0x8000($4)
+@end smallexample
+
+will cause the assembler to treat @samp{sym}, @code{sym+16} and
+@code{sym+0x8000} as 32-bit values. The handling of non-symbolic
+addresses is not affected.
+
+The directive @code{.set nosym32} ends a @code{.set sym32} block and
+reverts to the normal behavior. It is also possible to change the
+symbol size using the command-line options @option{-msym32} and
+@option{-mno-sym32}.
+
+These options and directives are always accepted, but at present,
+they have no effect for anything other than n64.
+
@node MIPS ISA
@section Directives to override the ISA level
are permitted, but also how certain macros are expanded. @code{.set
mips0} restores the @sc{isa} level to its original level: either the
level you selected with command line options, or the default for your
-configuration. You can use this feature to permit specific @sc{r4000}
+configuration. You can use this feature to permit specific @sc{mips3}
instructions while assembling in 32 bit mode. Use this directive with
care!
-The directive @samp{.set mips16} puts the assembler into MIPS 16 mode,
+@cindex MIPS CPU override
+@kindex @code{.set arch=@var{cpu}}
+The @code{.set arch=@var{cpu}} directive provides even finer control.
+It changes the effective CPU target and allows the assembler to use
+instructions specific to a particular CPU. All CPUs supported by the
+@samp{-march} command line option are also selectable by this directive.
+The original value is restored by @code{.set arch=default}.
+
+The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
in which it will assemble instructions for the MIPS 16 processor. Use
-@samp{.set nomips16} to return to normal 32 bit mode.
+@code{.set nomips16} to return to normal 32 bit mode.
Traditional @sc{mips} assemblers do not support this directive.
@kindex @code{.set autoextend}
@kindex @code{.set noautoextend}
By default, MIPS 16 instructions are automatically extended to 32 bits
-when necessary. The directive @samp{.set noautoextend} will turn this
-off. When @samp{.set noautoextend} is in effect, any 32 bit instruction
-must be explicitly extended with the @samp{.e} modifier (e.g.,
-@samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used
+when necessary. The directive @code{.set noautoextend} will turn this
+off. When @code{.set noautoextend} is in effect, any 32 bit instruction
+must be explicitly extended with the @code{.e} modifier (e.g.,
+@code{li.e $4,1000}). The directive @code{.set autoextend} may be used
to once again automatically extend instructions when necessary.
This directive is only meaningful when in MIPS 16 mode. Traditional
in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
instructions from being accepted.
+@cindex SmartMIPS instruction generation override
+@kindex @code{.set smartmips}
+@kindex @code{.set nosmartmips}
+The directive @code{.set smartmips} makes the assembler accept
+instructions from the SmartMIPS Application Specific Extension to the
+MIPS32 @sc{isa} from that point on in the assembly. The
+@code{.set nosmartmips} directive prevents SmartMIPS instructions from
+being accepted.
+
@cindex MIPS MDMX instruction generation override
@kindex @code{.set mdmx}
@kindex @code{.set nomdmx}
in the assembly. The @code{.set nomdmx} directive prevents MDMX
instructions from being accepted.
+@cindex MIPS DSP Release 1 instruction generation override
+@kindex @code{.set dsp}
+@kindex @code{.set nodsp}
+The directive @code{.set dsp} makes the assembler accept instructions
+from the DSP Release 1 Application Specific Extension from that point
+on in the assembly. The @code{.set nodsp} directive prevents DSP
+Release 1 instructions from being accepted.
+
+@cindex MIPS DSP Release 2 instruction generation override
+@kindex @code{.set dspr2}
+@kindex @code{.set nodspr2}
+The directive @code{.set dspr2} makes the assembler accept instructions
+from the DSP Release 2 Application Specific Extension from that point
+on in the assembly. This dirctive implies @code{.set dsp}. The
+@code{.set nodspr2} directive prevents DSP Release 2 instructions from
+being accepted.
+
+@cindex MIPS MT instruction generation override
+@kindex @code{.set mt}
+@kindex @code{.set nomt}
+The directive @code{.set mt} makes the assembler accept instructions
+from the MT Application Specific Extension from that point on
+in the assembly. The @code{.set nomt} directive prevents MT
+instructions from being accepted.
+
+Traditional @sc{mips} assemblers do not support these directives.
+
+@node MIPS floating-point
+@section Directives to override floating-point options
+
+@cindex Disable floating-point instructions
+@kindex @code{.set softfloat}
+@kindex @code{.set hardfloat}
+The directives @code{.set softfloat} and @code{.set hardfloat} provide
+finer control of disabling and enabling float-point instructions.
+These directives always override the default (that hard-float
+instructions are accepted) or the command-line options
+(@samp{-msoft-float} and @samp{-mhard-float}).
+
+@cindex Disable single-precision floating-point operations
+@kindex @code{.set softfloat}
+@kindex @code{.set hardfloat}
+The directives @code{.set singlefloat} and @code{.set doublefloat}
+provide finer control of disabling and enabling double-precision
+float-point operations. These directives always override the default
+(that double-precision operations are accepted) or the command-line
+options (@samp{-msingle-float} and @samp{-mdouble-float}).
+
Traditional @sc{mips} assemblers do not support these directives.