@cindex MIPS processor
@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
-different @sc{mips} processors, and MIPS ISA levels I through IV. For
+different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
+and MIPS64. For
information about the @sc{mips} instruction set, see @cite{MIPS RISC
Architecture}, by Kane and Heindrich (Prentice-Hall). For an overview
of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
@itemx -mips2
@itemx -mips3
@itemx -mips4
+@itemx -mips5
+@itemx -mips32
+@itemx -mips64
Generate code for a particular MIPS Instruction Set Architecture level.
@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
-@sc{r10000} processors. You can also switch instruction sets during the
-assembly; see @ref{MIPS ISA,, Directives to override the ISA level}.
+@sc{r10000} processors.
+@samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
+to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
+processors, respectively.
+You can also switch instruction sets during the
+assembly; see @ref{MIPS ISA, Directives to override the ISA level}.
+
+@item -mgp32
+Assume that 32-bit general purpose registers are available. This
+affects synthetic instructions such as @code{move}, which will assemble
+to a 32-bit or a 64-bit instruction depending on this flag. On some
+MIPS variants there is a 32-bit mode flag; when this flag is set,
+64-bit instructions generate a trap. Also, some 32-bit OSes only save
+the 32-bit registers on a context switch, so it is essential never to
+use the 64-bit registers.
+
+@item -mgp64
+Assume that 64-bit general purpose registers are available. This is
+provided in the interests of symmetry with -gp32.
@item -mips16
@itemx -no-mips16
@samp{.set mips16} at the start of the assembly file. @samp{-no-mips16}
turns off this option.
+@item -mfix7000
+@itemx -no-mfix7000
+Cause nops to be inserted if the read of the destination register
+of an mfhi or mflo instruction occurs in the following two instructions.
+
@item -m4010
@itemx -no-m4010
Generate code for the LSI @sc{r4010} chip. This tells the assembler to
instructions around accesses to the @samp{HI} and @samp{LO} registers.
@samp{-no-m4650} turns off this option.
-@c start-sanitize-tx19
-@item -m1900
-@itemx -no-m1900
-@c end-sanitize-tx19
@itemx -m3900
@itemx -no-m3900
@itemx -m4100
@itemx -no-m4100
-@c start-sanitize-vr4xxx
-@itemx -m4121
-@itemx -no-m4121
-@c end-sanitize-vr4xxx
-@c start-sanitize-4320
-@itemx -m4320
-@itemx -no-m4320
-@c end-sanitize-4320
-@c start-sanitize-tx49
-@itemx -m4900
-@itemx -no-m4900
-@c end-sanitize-tx49
-@c start-sanitize-cygnus
-@itemx -m5400
-@itemx -no-m5400
-@c end-sanitize-cygnus
-@c start-sanitize-r5900
-@itemx -m5900
-@itemx -no-m5900
-@c end-sanitize-r5900
For each option @samp{-m@var{nnnn}}, generate code for the MIPS
@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions
specific to that chip, and to schedule for that chip's hazards.
understood. Valid @var{cpu} value are:
@quotation
-@c start-sanitize-tx19
-1900,
-@c end-sanitize-tx19
2000,
3000,
3900,
4000,
4010,
4100,
-@c start-sanitize-vr4xxx
4111,
-4121,
-@c end-sanitize-vr4xxx
4300,
-@c start-sanitize-vr4320
-4320,
-@c end-sanitize-vr4320
4400,
4600,
4650,
-@c start-sanitize-tx49
-4900,
-@c end-sanitize-tx49
5000,
-@c start-sanitize-cygnus
-5400,
-@c end-sanitize-cygnus
-@c start-sanitize-r5900
-5900,
-@c end-sanitize-r5900
+rm5200,
+rm5230,
+rm5231,
+rm5261,
+rm5721,
6000,
+rm7000,
8000,
-10000
+10000,
+mips32-4k
@end quotation
@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
@sc{gnu} assembler itself never runs the C preprocessor.
+@item --construct-floats
+@itemx --no-construct-floats
+@cindex --construct-floats
+@cindex --no-construct-floats
+The @code{--no-construct-floats} option disables the construction of
+double width floating point constants by loading the two halves of the
+value into the two single width floating point registers that make up
+the double width register. This feature is useful if the processor
+support the FR bit in its status register, and this bit is known (by
+the programmer) to be set. This bit prevents the aliasing of the double
+width register by the single width registers.
+
+By default @code{--construct-floats} is selected, allowing construction
+of these floating point constants.
+
@item --trap
@itemx --no-break
@c FIXME! (1) reflect these options (next item too) in option summaries;
@kindex @code{.set mips@var{n}}
@sc{gnu} @code{@value{AS}} supports an additional directive to change
the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
-mips@var{n}}. @var{n} should be a number from 0 to 4. A value from 1
-to 4 makes the assembler accept instructions for the corresponding
+mips@var{n}}. @var{n} should be a number from 0 to 5, or 32 or 64.
+The values 1 to 5, 32, and 64 make the assembler accept instructions
+for the corresponding
@sc{isa} level, from that point on in the assembly. @code{.set
mips@var{n}} affects not only which instructions are permitted, but also
how certain macros are expanded. @code{.set mips0} restores the
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