Add new command line switch --no-construct-floats

[deliverable/binutils-gdb.git] / gas / doc / c-mips.texi

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index fc2555a172ae205c72fdc204eaef75dd45f8c99e..cb200bcaf769cd8bfcdf9f81b71577c61c75e971 100644 (file)
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -67,6 +67,19 @@ Generate code for a particular MIPS Instruction Set Architecture level.
 @sc{r10000} processors.  You can also switch instruction sets during the
 assembly; see @ref{MIPS ISA,, Directives to override the ISA level}.
 
+@item -mgp32
+Assume that 32-bit general purpose registers are available.  This
+affects synthetic instructions such as @code{move}, which will assemble
+to a 32-bit or a 64-bit instruction depending on this flag.  On some
+MIPS variants there is a 32-bit mode flag; when this flag is set,
+64-bit instructions generate a trap.  Also, some 32-bit OSes only save
+the 32-bit registers on a context switch, so it is essential never to
+use the 64-bit registers.
+
+@item -mgp64
+Assume that 64-bit general purpose registers are available.  This is
+provided in the interests of symmetry with -gp32.
+
 @item -mips16
 @itemx -no-mips16
 Generate code for the MIPS 16 processor.  This is equivalent to putting
@@ -119,7 +132,13 @@ understood.  Valid @var{cpu} value are:
 4600,
 4650,
 5000,
+rm5200,
+rm5230,
+rm5231,
+rm5261,
+rm5721,
 6000,
+rm7000,
 8000,
 10000
 @end quotation
@@ -132,6 +151,21 @@ other assemblers, which use it to turn off C style preprocessing.  With
 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
 @sc{gnu} assembler itself never runs the C preprocessor.
 
+@item --construct-floats
+@itemx --no-construct-floats
+@cindex --construct-floats
+@cindex --no-construct-floats
+The @code{--no-construct-floats} option disables the construction of
+double width floating point constants by loading the two halves of the
+value into the two single width floating point registers that make up
+the double width register.  This feature is useful if the processor
+support the FR bit in its status  register, and this bit is known (by
+the programmer) to be set.  This bit prevents the aliasing of the double
+width register by the single width registers.
+
+By default @code {--construct-floats} is selected, allowing construction
+of these floating point constants.
+
 @item --trap
 @itemx --no-break
 @c FIXME!  (1) reflect these options (next item too) in option summaries;