-@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001
+@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004, 2005
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
(formerly Hitachi) / SuperH SH family.
@table @code
-@kindex -little
-@kindex -big
-@kindex -relax
-@kindex -small
-@kindex -dsp
-
-@item -little
+@kindex --little
+@kindex --big
+@kindex --relax
+@kindex --small
+@kindex --dsp
+@kindex --renesas
+@kindex --allow-reg-prefix
+
+@item --little
Generate little endian code.
-@item -big
+@item --big
Generate big endian code.
-@item -relax
+@item --relax
Alter jump instructions for long displacements.
-@item -small
+@item --small
Align sections to 4 byte boundaries, not 16.
-@item -dsp
+@item --dsp
+Enable sh-dsp insns, and disable sh3e / sh4 insns.
+
+@item --renesas
+Disable optimization with section symbol for compatibility with
+Renesas assembler.
+
+@item --allow-reg-prefix
+Allow '$' as a register name prefix.
+
+@item --isa=sh4 | sh4a
+Specify the sh4 or sh4a instruction set.
+@item --isa=dsp
Enable sh-dsp insns, and disable sh3e / sh4 insns.
+@item --isa=fp
+Enable sh2e, sh3e, sh4, and sh4a insn sets.
+@item --isa=all
+Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
@end table
@cindex floating point, SH (@sc{ieee})
@cindex SH floating point (@sc{ieee})
-The SH family has no hardware floating point, but the @code{.float}
-directive generates @sc{ieee} floating-point numbers for compatibility
-with other development tools.
+SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
+SH groups can use @code{.float} directive to generate @sc{ieee}
+floating-point numbers.
+
+SH2E and SH3E support single-precision floating point calculations as
+well as entirely PCAPI compatible emulation of double-precision
+floating point calculations. SH2E and SH3E instructions are a subset of
+the floating point calculations conforming to the IEEE754 standard.
+
+In addition to single-precision and double-precision floating-point
+operation capability, the on-chip FPU of SH4 has a 128-bit graphic
+engine that enables 32-bit floating-point data to be processed 128
+bits at a time. It also supports 4 * 4 array operations and inner
+product operations. Also, a superscalar architecture is employed that
+enables simultaneous execution of two instructions (including FPU
+instructions), providing performance of up to twice that of
+conventional architectures at the same frequency.
@node SH Directives
@section SH Machine Directives