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[deliverable/binutils-gdb.git] / gas / doc / c-sh.texi

diff --git a/gas/doc/c-sh.texi b/gas/doc/c-sh.texi
index e20f55437883a3dab60f4b564a9bd9a9b9c7a9ba..e6dbe4bf5c2ca4c1dd3088e3d1e590e125df1d34 100644 (file)
--- a/gas/doc/c-sh.texi
+++ b/gas/doc/c-sh.texi
@@ -1,9 +1,10 @@
-@c Copyright (C) 1991, 92, 93, 94, 95, 1997 Free Software Foundation, Inc.
+@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004, 2005
+@c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @page
 @node SH-Dependent
-@chapter Hitachi SH Dependent Features
+@chapter Renesas / SuperH SH Dependent Features
 
 @cindex SH support
 @menu
@@ -17,10 +18,52 @@
 @node SH Options
 @section Options
 
-@cindex SH options (none)
-@cindex options, SH (none)
-@code{@value{AS}} has no additional command-line options for the Hitachi
-SH family.
+@cindex SH options
+@cindex options, SH
+@code{@value{AS}} has following command-line options for the Renesas
+(formerly Hitachi) / SuperH SH family.
+
+@table @code
+@kindex --little
+@kindex --big
+@kindex --relax
+@kindex --small
+@kindex --dsp
+@kindex --renesas
+@kindex --allow-reg-prefix
+
+@item --little
+Generate little endian code.
+
+@item --big
+Generate big endian code.
+
+@item --relax
+Alter jump instructions for long displacements.
+
+@item --small
+Align sections to 4 byte boundaries, not 16.
+
+@item --dsp
+Enable sh-dsp insns, and disable sh3e / sh4 insns.
+
+@item --renesas
+Disable optimization with section symbol for compatibility with
+Renesas assembler.
+
+@item --allow-reg-prefix
+Allow '$' as a register name prefix.
+
+@item --isa=sh4 | sh4a
+Specify the sh4 or sh4a instruction set.
+@item --isa=dsp
+Enable sh-dsp insns, and disable sh3e / sh4 insns.
+@item --isa=fp
+Enable sh2e, sh3e, sh4, and sh4a insn sets.
+@item --isa=all
+Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
+
+@end table
 
 @node SH Syntax
 @section Syntax
@@ -130,9 +173,23 @@ Immediate data
 
 @cindex floating point, SH (@sc{ieee})
 @cindex SH floating point (@sc{ieee})
-The SH family has no hardware floating point, but the @code{.float}
-directive generates @sc{ieee} floating-point numbers for compatibility
-with other development tools.
+SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
+SH groups can use @code{.float} directive to generate @sc{ieee} 
+floating-point numbers. 
+
+SH2E and SH3E support single-precision floating point calculations as 
+well as entirely PCAPI compatible emulation of double-precision 
+floating point calculations. SH2E and SH3E instructions are a subset of
+the floating point calculations conforming to the IEEE754 standard.
+
+In addition to single-precision and double-precision floating-point 
+operation capability, the on-chip FPU of SH4 has a 128-bit graphic 
+engine that enables 32-bit floating-point data to be processed 128 
+bits at a time. It also supports 4 * 4 array operations and inner 
+product operations. Also, a superscalar architecture is employed that 
+enables simultaneous execution of two instructions (including FPU 
+instructions), providing performance of up to twice that of 
+conventional architectures at the same frequency.
 
 @node SH Directives
 @section SH Machine Directives
@@ -158,7 +215,9 @@ with other development tools.
 @cindex mnemonics, SH
 @cindex instruction summary, SH
 For detailed information on the SH machine instruction set, see
-@cite{SH-Microcomputer User's Manual} (Hitachi Micro Systems, Inc.).
+@cite{SH-Microcomputer User's Manual} (Renesas) or
+@cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
+@cite{SuperH (SH) 64-Bit RISC Series} (SuperH).
 
 @code{@value{AS}} implements all the standard SH opcodes.  No additional
 pseudo-instructions are needed on this family.  Note, however, that
@@ -264,7 +323,7 @@ stc SR,Rn
 @end smallexample
 @end ifset
 
-@ifset Hitachi-all
+@ifset Renesas-all
 @ifclear GENERIC
 @raisesections
 @end ifclear