[AArch64] Print spaces after commas in addresses

[deliverable/binutils-gdb.git] / gas / testsuite / gas / aarch64 / sve.d

diff --git a/gas/testsuite/gas/aarch64/sve.d b/gas/testsuite/gas/aarch64/sve.d
index e8068c8fb7327f5ae6c5f24d6d34564443ee9cb6..b8492e57bf3d40f4450360c68e38740822a5e098 100644 (file)
--- a/gas/testsuite/gas/aarch64/sve.d
+++ b/gas/testsuite/gas/aarch64/sve.d
@@ -1421,258 +1421,258 @@ Disassembly of section .*:
 .*:    04205420        addvl   x0, x0, #-31
 .*:    042057e0        addvl   x0, x0, #-1
 .*:    042057e0        addvl   x0, x0, #-1
-.*:    0420a000        adr     z0\.d, \[z0\.d,z0\.d,sxtw\]
-.*:    0420a000        adr     z0\.d, \[z0\.d,z0\.d,sxtw\]
-.*:    0420a000        adr     z0\.d, \[z0\.d,z0\.d,sxtw\]
-.*:    0420a001        adr     z1\.d, \[z0\.d,z0\.d,sxtw\]
-.*:    0420a001        adr     z1\.d, \[z0\.d,z0\.d,sxtw\]
-.*:    0420a001        adr     z1\.d, \[z0\.d,z0\.d,sxtw\]
-.*:    0420a01f        adr     z31\.d, \[z0\.d,z0\.d,sxtw\]
-.*:    0420a01f        adr     z31\.d, \[z0\.d,z0\.d,sxtw\]
-.*:    0420a01f        adr     z31\.d, \[z0\.d,z0\.d,sxtw\]
-.*:    0420a040        adr     z0\.d, \[z2\.d,z0\.d,sxtw\]
-.*:    0420a040        adr     z0\.d, \[z2\.d,z0\.d,sxtw\]
-.*:    0420a040        adr     z0\.d, \[z2\.d,z0\.d,sxtw\]
-.*:    0420a3e0        adr     z0\.d, \[z31\.d,z0\.d,sxtw\]
-.*:    0420a3e0        adr     z0\.d, \[z31\.d,z0\.d,sxtw\]
-.*:    0420a3e0        adr     z0\.d, \[z31\.d,z0\.d,sxtw\]
-.*:    0423a000        adr     z0\.d, \[z0\.d,z3\.d,sxtw\]
-.*:    0423a000        adr     z0\.d, \[z0\.d,z3\.d,sxtw\]
-.*:    0423a000        adr     z0\.d, \[z0\.d,z3\.d,sxtw\]
-.*:    043fa000        adr     z0\.d, \[z0\.d,z31\.d,sxtw\]
-.*:    043fa000        adr     z0\.d, \[z0\.d,z31\.d,sxtw\]
-.*:    043fa000        adr     z0\.d, \[z0\.d,z31\.d,sxtw\]
-.*:    0420a400        adr     z0\.d, \[z0\.d,z0\.d,sxtw #1\]
-.*:    0420a400        adr     z0\.d, \[z0\.d,z0\.d,sxtw #1\]
-.*:    0420a401        adr     z1\.d, \[z0\.d,z0\.d,sxtw #1\]
-.*:    0420a401        adr     z1\.d, \[z0\.d,z0\.d,sxtw #1\]
-.*:    0420a41f        adr     z31\.d, \[z0\.d,z0\.d,sxtw #1\]
-.*:    0420a41f        adr     z31\.d, \[z0\.d,z0\.d,sxtw #1\]
-.*:    0420a440        adr     z0\.d, \[z2\.d,z0\.d,sxtw #1\]
-.*:    0420a440        adr     z0\.d, \[z2\.d,z0\.d,sxtw #1\]
-.*:    0420a7e0        adr     z0\.d, \[z31\.d,z0\.d,sxtw #1\]
-.*:    0420a7e0        adr     z0\.d, \[z31\.d,z0\.d,sxtw #1\]
-.*:    0423a400        adr     z0\.d, \[z0\.d,z3\.d,sxtw #1\]
-.*:    0423a400        adr     z0\.d, \[z0\.d,z3\.d,sxtw #1\]
-.*:    043fa400        adr     z0\.d, \[z0\.d,z31\.d,sxtw #1\]
-.*:    043fa400        adr     z0\.d, \[z0\.d,z31\.d,sxtw #1\]
-.*:    0420a800        adr     z0\.d, \[z0\.d,z0\.d,sxtw #2\]
-.*:    0420a800        adr     z0\.d, \[z0\.d,z0\.d,sxtw #2\]
-.*:    0420a801        adr     z1\.d, \[z0\.d,z0\.d,sxtw #2\]
-.*:    0420a801        adr     z1\.d, \[z0\.d,z0\.d,sxtw #2\]
-.*:    0420a81f        adr     z31\.d, \[z0\.d,z0\.d,sxtw #2\]
-.*:    0420a81f        adr     z31\.d, \[z0\.d,z0\.d,sxtw #2\]
-.*:    0420a840        adr     z0\.d, \[z2\.d,z0\.d,sxtw #2\]
-.*:    0420a840        adr     z0\.d, \[z2\.d,z0\.d,sxtw #2\]
-.*:    0420abe0        adr     z0\.d, \[z31\.d,z0\.d,sxtw #2\]
-.*:    0420abe0        adr     z0\.d, \[z31\.d,z0\.d,sxtw #2\]
-.*:    0423a800        adr     z0\.d, \[z0\.d,z3\.d,sxtw #2\]
-.*:    0423a800        adr     z0\.d, \[z0\.d,z3\.d,sxtw #2\]
-.*:    043fa800        adr     z0\.d, \[z0\.d,z31\.d,sxtw #2\]
-.*:    043fa800        adr     z0\.d, \[z0\.d,z31\.d,sxtw #2\]
-.*:    0420ac00        adr     z0\.d, \[z0\.d,z0\.d,sxtw #3\]
-.*:    0420ac00        adr     z0\.d, \[z0\.d,z0\.d,sxtw #3\]
-.*:    0420ac01        adr     z1\.d, \[z0\.d,z0\.d,sxtw #3\]
-.*:    0420ac01        adr     z1\.d, \[z0\.d,z0\.d,sxtw #3\]
-.*:    0420ac1f        adr     z31\.d, \[z0\.d,z0\.d,sxtw #3\]
-.*:    0420ac1f        adr     z31\.d, \[z0\.d,z0\.d,sxtw #3\]
-.*:    0420ac40        adr     z0\.d, \[z2\.d,z0\.d,sxtw #3\]
-.*:    0420ac40        adr     z0\.d, \[z2\.d,z0\.d,sxtw #3\]
-.*:    0420afe0        adr     z0\.d, \[z31\.d,z0\.d,sxtw #3\]
-.*:    0420afe0        adr     z0\.d, \[z31\.d,z0\.d,sxtw #3\]
-.*:    0423ac00        adr     z0\.d, \[z0\.d,z3\.d,sxtw #3\]
-.*:    0423ac00        adr     z0\.d, \[z0\.d,z3\.d,sxtw #3\]
-.*:    043fac00        adr     z0\.d, \[z0\.d,z31\.d,sxtw #3\]
-.*:    043fac00        adr     z0\.d, \[z0\.d,z31\.d,sxtw #3\]
-.*:    0460a000        adr     z0\.d, \[z0\.d,z0\.d,uxtw\]
-.*:    0460a000        adr     z0\.d, \[z0\.d,z0\.d,uxtw\]
-.*:    0460a000        adr     z0\.d, \[z0\.d,z0\.d,uxtw\]
-.*:    0460a001        adr     z1\.d, \[z0\.d,z0\.d,uxtw\]
-.*:    0460a001        adr     z1\.d, \[z0\.d,z0\.d,uxtw\]
-.*:    0460a001        adr     z1\.d, \[z0\.d,z0\.d,uxtw\]
-.*:    0460a01f        adr     z31\.d, \[z0\.d,z0\.d,uxtw\]
-.*:    0460a01f        adr     z31\.d, \[z0\.d,z0\.d,uxtw\]
-.*:    0460a01f        adr     z31\.d, \[z0\.d,z0\.d,uxtw\]
-.*:    0460a040        adr     z0\.d, \[z2\.d,z0\.d,uxtw\]
-.*:    0460a040        adr     z0\.d, \[z2\.d,z0\.d,uxtw\]
-.*:    0460a040        adr     z0\.d, \[z2\.d,z0\.d,uxtw\]
-.*:    0460a3e0        adr     z0\.d, \[z31\.d,z0\.d,uxtw\]
-.*:    0460a3e0        adr     z0\.d, \[z31\.d,z0\.d,uxtw\]
-.*:    0460a3e0        adr     z0\.d, \[z31\.d,z0\.d,uxtw\]
-.*:    0463a000        adr     z0\.d, \[z0\.d,z3\.d,uxtw\]
-.*:    0463a000        adr     z0\.d, \[z0\.d,z3\.d,uxtw\]
-.*:    0463a000        adr     z0\.d, \[z0\.d,z3\.d,uxtw\]
-.*:    047fa000        adr     z0\.d, \[z0\.d,z31\.d,uxtw\]
-.*:    047fa000        adr     z0\.d, \[z0\.d,z31\.d,uxtw\]
-.*:    047fa000        adr     z0\.d, \[z0\.d,z31\.d,uxtw\]
-.*:    0460a400        adr     z0\.d, \[z0\.d,z0\.d,uxtw #1\]
-.*:    0460a400        adr     z0\.d, \[z0\.d,z0\.d,uxtw #1\]
-.*:    0460a401        adr     z1\.d, \[z0\.d,z0\.d,uxtw #1\]
-.*:    0460a401        adr     z1\.d, \[z0\.d,z0\.d,uxtw #1\]
-.*:    0460a41f        adr     z31\.d, \[z0\.d,z0\.d,uxtw #1\]
-.*:    0460a41f        adr     z31\.d, \[z0\.d,z0\.d,uxtw #1\]
-.*:    0460a440        adr     z0\.d, \[z2\.d,z0\.d,uxtw #1\]
-.*:    0460a440        adr     z0\.d, \[z2\.d,z0\.d,uxtw #1\]
-.*:    0460a7e0        adr     z0\.d, \[z31\.d,z0\.d,uxtw #1\]
-.*:    0460a7e0        adr     z0\.d, \[z31\.d,z0\.d,uxtw #1\]
-.*:    0463a400        adr     z0\.d, \[z0\.d,z3\.d,uxtw #1\]
-.*:    0463a400        adr     z0\.d, \[z0\.d,z3\.d,uxtw #1\]
-.*:    047fa400        adr     z0\.d, \[z0\.d,z31\.d,uxtw #1\]
-.*:    047fa400        adr     z0\.d, \[z0\.d,z31\.d,uxtw #1\]
-.*:    0460a800        adr     z0\.d, \[z0\.d,z0\.d,uxtw #2\]
-.*:    0460a800        adr     z0\.d, \[z0\.d,z0\.d,uxtw #2\]
-.*:    0460a801        adr     z1\.d, \[z0\.d,z0\.d,uxtw #2\]
-.*:    0460a801        adr     z1\.d, \[z0\.d,z0\.d,uxtw #2\]
-.*:    0460a81f        adr     z31\.d, \[z0\.d,z0\.d,uxtw #2\]
-.*:    0460a81f        adr     z31\.d, \[z0\.d,z0\.d,uxtw #2\]
-.*:    0460a840        adr     z0\.d, \[z2\.d,z0\.d,uxtw #2\]
-.*:    0460a840        adr     z0\.d, \[z2\.d,z0\.d,uxtw #2\]
-.*:    0460abe0        adr     z0\.d, \[z31\.d,z0\.d,uxtw #2\]
-.*:    0460abe0        adr     z0\.d, \[z31\.d,z0\.d,uxtw #2\]
-.*:    0463a800        adr     z0\.d, \[z0\.d,z3\.d,uxtw #2\]
-.*:    0463a800        adr     z0\.d, \[z0\.d,z3\.d,uxtw #2\]
-.*:    047fa800        adr     z0\.d, \[z0\.d,z31\.d,uxtw #2\]
-.*:    047fa800        adr     z0\.d, \[z0\.d,z31\.d,uxtw #2\]
-.*:    0460ac00        adr     z0\.d, \[z0\.d,z0\.d,uxtw #3\]
-.*:    0460ac00        adr     z0\.d, \[z0\.d,z0\.d,uxtw #3\]
-.*:    0460ac01        adr     z1\.d, \[z0\.d,z0\.d,uxtw #3\]
-.*:    0460ac01        adr     z1\.d, \[z0\.d,z0\.d,uxtw #3\]
-.*:    0460ac1f        adr     z31\.d, \[z0\.d,z0\.d,uxtw #3\]
-.*:    0460ac1f        adr     z31\.d, \[z0\.d,z0\.d,uxtw #3\]
-.*:    0460ac40        adr     z0\.d, \[z2\.d,z0\.d,uxtw #3\]
-.*:    0460ac40        adr     z0\.d, \[z2\.d,z0\.d,uxtw #3\]
-.*:    0460afe0        adr     z0\.d, \[z31\.d,z0\.d,uxtw #3\]
-.*:    0460afe0        adr     z0\.d, \[z31\.d,z0\.d,uxtw #3\]
-.*:    0463ac00        adr     z0\.d, \[z0\.d,z3\.d,uxtw #3\]
-.*:    0463ac00        adr     z0\.d, \[z0\.d,z3\.d,uxtw #3\]
-.*:    047fac00        adr     z0\.d, \[z0\.d,z31\.d,uxtw #3\]
-.*:    047fac00        adr     z0\.d, \[z0\.d,z31\.d,uxtw #3\]
-.*:    04a0a000        adr     z0\.s, \[z0\.s,z0\.s\]
-.*:    04a0a000        adr     z0\.s, \[z0\.s,z0\.s\]
-.*:    04a0a000        adr     z0\.s, \[z0\.s,z0\.s\]
-.*:    04a0a001        adr     z1\.s, \[z0\.s,z0\.s\]
-.*:    04a0a001        adr     z1\.s, \[z0\.s,z0\.s\]
-.*:    04a0a001        adr     z1\.s, \[z0\.s,z0\.s\]
-.*:    04a0a01f        adr     z31\.s, \[z0\.s,z0\.s\]
-.*:    04a0a01f        adr     z31\.s, \[z0\.s,z0\.s\]
-.*:    04a0a01f        adr     z31\.s, \[z0\.s,z0\.s\]
-.*:    04a0a040        adr     z0\.s, \[z2\.s,z0\.s\]
-.*:    04a0a040        adr     z0\.s, \[z2\.s,z0\.s\]
-.*:    04a0a040        adr     z0\.s, \[z2\.s,z0\.s\]
-.*:    04a0a3e0        adr     z0\.s, \[z31\.s,z0\.s\]
-.*:    04a0a3e0        adr     z0\.s, \[z31\.s,z0\.s\]
-.*:    04a0a3e0        adr     z0\.s, \[z31\.s,z0\.s\]
-.*:    04a3a000        adr     z0\.s, \[z0\.s,z3\.s\]
-.*:    04a3a000        adr     z0\.s, \[z0\.s,z3\.s\]
-.*:    04a3a000        adr     z0\.s, \[z0\.s,z3\.s\]
-.*:    04bfa000        adr     z0\.s, \[z0\.s,z31\.s\]
-.*:    04bfa000        adr     z0\.s, \[z0\.s,z31\.s\]
-.*:    04bfa000        adr     z0\.s, \[z0\.s,z31\.s\]
-.*:    04a0a400        adr     z0\.s, \[z0\.s,z0\.s,lsl #1\]
-.*:    04a0a400        adr     z0\.s, \[z0\.s,z0\.s,lsl #1\]
-.*:    04a0a401        adr     z1\.s, \[z0\.s,z0\.s,lsl #1\]
-.*:    04a0a401        adr     z1\.s, \[z0\.s,z0\.s,lsl #1\]
-.*:    04a0a41f        adr     z31\.s, \[z0\.s,z0\.s,lsl #1\]
-.*:    04a0a41f        adr     z31\.s, \[z0\.s,z0\.s,lsl #1\]
-.*:    04a0a440        adr     z0\.s, \[z2\.s,z0\.s,lsl #1\]
-.*:    04a0a440        adr     z0\.s, \[z2\.s,z0\.s,lsl #1\]
-.*:    04a0a7e0        adr     z0\.s, \[z31\.s,z0\.s,lsl #1\]
-.*:    04a0a7e0        adr     z0\.s, \[z31\.s,z0\.s,lsl #1\]
-.*:    04a3a400        adr     z0\.s, \[z0\.s,z3\.s,lsl #1\]
-.*:    04a3a400        adr     z0\.s, \[z0\.s,z3\.s,lsl #1\]
-.*:    04bfa400        adr     z0\.s, \[z0\.s,z31\.s,lsl #1\]
-.*:    04bfa400        adr     z0\.s, \[z0\.s,z31\.s,lsl #1\]
-.*:    04a0a800        adr     z0\.s, \[z0\.s,z0\.s,lsl #2\]
-.*:    04a0a800        adr     z0\.s, \[z0\.s,z0\.s,lsl #2\]
-.*:    04a0a801        adr     z1\.s, \[z0\.s,z0\.s,lsl #2\]
-.*:    04a0a801        adr     z1\.s, \[z0\.s,z0\.s,lsl #2\]
-.*:    04a0a81f        adr     z31\.s, \[z0\.s,z0\.s,lsl #2\]
-.*:    04a0a81f        adr     z31\.s, \[z0\.s,z0\.s,lsl #2\]
-.*:    04a0a840        adr     z0\.s, \[z2\.s,z0\.s,lsl #2\]
-.*:    04a0a840        adr     z0\.s, \[z2\.s,z0\.s,lsl #2\]
-.*:    04a0abe0        adr     z0\.s, \[z31\.s,z0\.s,lsl #2\]
-.*:    04a0abe0        adr     z0\.s, \[z31\.s,z0\.s,lsl #2\]
-.*:    04a3a800        adr     z0\.s, \[z0\.s,z3\.s,lsl #2\]
-.*:    04a3a800        adr     z0\.s, \[z0\.s,z3\.s,lsl #2\]
-.*:    04bfa800        adr     z0\.s, \[z0\.s,z31\.s,lsl #2\]
-.*:    04bfa800        adr     z0\.s, \[z0\.s,z31\.s,lsl #2\]
-.*:    04a0ac00        adr     z0\.s, \[z0\.s,z0\.s,lsl #3\]
-.*:    04a0ac00        adr     z0\.s, \[z0\.s,z0\.s,lsl #3\]
-.*:    04a0ac01        adr     z1\.s, \[z0\.s,z0\.s,lsl #3\]
-.*:    04a0ac01        adr     z1\.s, \[z0\.s,z0\.s,lsl #3\]
-.*:    04a0ac1f        adr     z31\.s, \[z0\.s,z0\.s,lsl #3\]
-.*:    04a0ac1f        adr     z31\.s, \[z0\.s,z0\.s,lsl #3\]
-.*:    04a0ac40        adr     z0\.s, \[z2\.s,z0\.s,lsl #3\]
-.*:    04a0ac40        adr     z0\.s, \[z2\.s,z0\.s,lsl #3\]
-.*:    04a0afe0        adr     z0\.s, \[z31\.s,z0\.s,lsl #3\]
-.*:    04a0afe0        adr     z0\.s, \[z31\.s,z0\.s,lsl #3\]
-.*:    04a3ac00        adr     z0\.s, \[z0\.s,z3\.s,lsl #3\]
-.*:    04a3ac00        adr     z0\.s, \[z0\.s,z3\.s,lsl #3\]
-.*:    04bfac00        adr     z0\.s, \[z0\.s,z31\.s,lsl #3\]
-.*:    04bfac00        adr     z0\.s, \[z0\.s,z31\.s,lsl #3\]
-.*:    04e0a000        adr     z0\.d, \[z0\.d,z0\.d\]
-.*:    04e0a000        adr     z0\.d, \[z0\.d,z0\.d\]
-.*:    04e0a000        adr     z0\.d, \[z0\.d,z0\.d\]
-.*:    04e0a001        adr     z1\.d, \[z0\.d,z0\.d\]
-.*:    04e0a001        adr     z1\.d, \[z0\.d,z0\.d\]
-.*:    04e0a001        adr     z1\.d, \[z0\.d,z0\.d\]
-.*:    04e0a01f        adr     z31\.d, \[z0\.d,z0\.d\]
-.*:    04e0a01f        adr     z31\.d, \[z0\.d,z0\.d\]
-.*:    04e0a01f        adr     z31\.d, \[z0\.d,z0\.d\]
-.*:    04e0a040        adr     z0\.d, \[z2\.d,z0\.d\]
-.*:    04e0a040        adr     z0\.d, \[z2\.d,z0\.d\]
-.*:    04e0a040        adr     z0\.d, \[z2\.d,z0\.d\]
-.*:    04e0a3e0        adr     z0\.d, \[z31\.d,z0\.d\]
-.*:    04e0a3e0        adr     z0\.d, \[z31\.d,z0\.d\]
-.*:    04e0a3e0        adr     z0\.d, \[z31\.d,z0\.d\]
-.*:    04e3a000        adr     z0\.d, \[z0\.d,z3\.d\]
-.*:    04e3a000        adr     z0\.d, \[z0\.d,z3\.d\]
-.*:    04e3a000        adr     z0\.d, \[z0\.d,z3\.d\]
-.*:    04ffa000        adr     z0\.d, \[z0\.d,z31\.d\]
-.*:    04ffa000        adr     z0\.d, \[z0\.d,z31\.d\]
-.*:    04ffa000        adr     z0\.d, \[z0\.d,z31\.d\]
-.*:    04e0a400        adr     z0\.d, \[z0\.d,z0\.d,lsl #1\]
-.*:    04e0a400        adr     z0\.d, \[z0\.d,z0\.d,lsl #1\]
-.*:    04e0a401        adr     z1\.d, \[z0\.d,z0\.d,lsl #1\]
-.*:    04e0a401        adr     z1\.d, \[z0\.d,z0\.d,lsl #1\]
-.*:    04e0a41f        adr     z31\.d, \[z0\.d,z0\.d,lsl #1\]
-.*:    04e0a41f        adr     z31\.d, \[z0\.d,z0\.d,lsl #1\]
-.*:    04e0a440        adr     z0\.d, \[z2\.d,z0\.d,lsl #1\]
-.*:    04e0a440        adr     z0\.d, \[z2\.d,z0\.d,lsl #1\]
-.*:    04e0a7e0        adr     z0\.d, \[z31\.d,z0\.d,lsl #1\]
-.*:    04e0a7e0        adr     z0\.d, \[z31\.d,z0\.d,lsl #1\]
-.*:    04e3a400        adr     z0\.d, \[z0\.d,z3\.d,lsl #1\]
-.*:    04e3a400        adr     z0\.d, \[z0\.d,z3\.d,lsl #1\]
-.*:    04ffa400        adr     z0\.d, \[z0\.d,z31\.d,lsl #1\]
-.*:    04ffa400        adr     z0\.d, \[z0\.d,z31\.d,lsl #1\]
-.*:    04e0a800        adr     z0\.d, \[z0\.d,z0\.d,lsl #2\]
-.*:    04e0a800        adr     z0\.d, \[z0\.d,z0\.d,lsl #2\]
-.*:    04e0a801        adr     z1\.d, \[z0\.d,z0\.d,lsl #2\]
-.*:    04e0a801        adr     z1\.d, \[z0\.d,z0\.d,lsl #2\]
-.*:    04e0a81f        adr     z31\.d, \[z0\.d,z0\.d,lsl #2\]
-.*:    04e0a81f        adr     z31\.d, \[z0\.d,z0\.d,lsl #2\]
-.*:    04e0a840        adr     z0\.d, \[z2\.d,z0\.d,lsl #2\]
-.*:    04e0a840        adr     z0\.d, \[z2\.d,z0\.d,lsl #2\]
-.*:    04e0abe0        adr     z0\.d, \[z31\.d,z0\.d,lsl #2\]
-.*:    04e0abe0        adr     z0\.d, \[z31\.d,z0\.d,lsl #2\]
-.*:    04e3a800        adr     z0\.d, \[z0\.d,z3\.d,lsl #2\]
-.*:    04e3a800        adr     z0\.d, \[z0\.d,z3\.d,lsl #2\]
-.*:    04ffa800        adr     z0\.d, \[z0\.d,z31\.d,lsl #2\]
-.*:    04ffa800        adr     z0\.d, \[z0\.d,z31\.d,lsl #2\]
-.*:    04e0ac00        adr     z0\.d, \[z0\.d,z0\.d,lsl #3\]
-.*:    04e0ac00        adr     z0\.d, \[z0\.d,z0\.d,lsl #3\]
-.*:    04e0ac01        adr     z1\.d, \[z0\.d,z0\.d,lsl #3\]
-.*:    04e0ac01        adr     z1\.d, \[z0\.d,z0\.d,lsl #3\]
-.*:    04e0ac1f        adr     z31\.d, \[z0\.d,z0\.d,lsl #3\]
-.*:    04e0ac1f        adr     z31\.d, \[z0\.d,z0\.d,lsl #3\]
-.*:    04e0ac40        adr     z0\.d, \[z2\.d,z0\.d,lsl #3\]
-.*:    04e0ac40        adr     z0\.d, \[z2\.d,z0\.d,lsl #3\]
-.*:    04e0afe0        adr     z0\.d, \[z31\.d,z0\.d,lsl #3\]
-.*:    04e0afe0        adr     z0\.d, \[z31\.d,z0\.d,lsl #3\]
-.*:    04e3ac00        adr     z0\.d, \[z0\.d,z3\.d,lsl #3\]
-.*:    04e3ac00        adr     z0\.d, \[z0\.d,z3\.d,lsl #3\]
-.*:    04ffac00        adr     z0\.d, \[z0\.d,z31\.d,lsl #3\]
-.*:    04ffac00        adr     z0\.d, \[z0\.d,z31\.d,lsl #3\]
+.*:    0420a000        adr     z0\.d, \[z0\.d, z0\.d, sxtw\]
+.*:    0420a000        adr     z0\.d, \[z0\.d, z0\.d, sxtw\]
+.*:    0420a000        adr     z0\.d, \[z0\.d, z0\.d, sxtw\]
+.*:    0420a001        adr     z1\.d, \[z0\.d, z0\.d, sxtw\]
+.*:    0420a001        adr     z1\.d, \[z0\.d, z0\.d, sxtw\]
+.*:    0420a001        adr     z1\.d, \[z0\.d, z0\.d, sxtw\]
+.*:    0420a01f        adr     z31\.d, \[z0\.d, z0\.d, sxtw\]
+.*:    0420a01f        adr     z31\.d, \[z0\.d, z0\.d, sxtw\]
+.*:    0420a01f        adr     z31\.d, \[z0\.d, z0\.d, sxtw\]
+.*:    0420a040        adr     z0\.d, \[z2\.d, z0\.d, sxtw\]
+.*:    0420a040        adr     z0\.d, \[z2\.d, z0\.d, sxtw\]
+.*:    0420a040        adr     z0\.d, \[z2\.d, z0\.d, sxtw\]
+.*:    0420a3e0        adr     z0\.d, \[z31\.d, z0\.d, sxtw\]
+.*:    0420a3e0        adr     z0\.d, \[z31\.d, z0\.d, sxtw\]
+.*:    0420a3e0        adr     z0\.d, \[z31\.d, z0\.d, sxtw\]
+.*:    0423a000        adr     z0\.d, \[z0\.d, z3\.d, sxtw\]
+.*:    0423a000        adr     z0\.d, \[z0\.d, z3\.d, sxtw\]
+.*:    0423a000        adr     z0\.d, \[z0\.d, z3\.d, sxtw\]
+.*:    043fa000        adr     z0\.d, \[z0\.d, z31\.d, sxtw\]
+.*:    043fa000        adr     z0\.d, \[z0\.d, z31\.d, sxtw\]
+.*:    043fa000        adr     z0\.d, \[z0\.d, z31\.d, sxtw\]
+.*:    0420a400        adr     z0\.d, \[z0\.d, z0\.d, sxtw #1\]
+.*:    0420a400        adr     z0\.d, \[z0\.d, z0\.d, sxtw #1\]
+.*:    0420a401        adr     z1\.d, \[z0\.d, z0\.d, sxtw #1\]
+.*:    0420a401        adr     z1\.d, \[z0\.d, z0\.d, sxtw #1\]
+.*:    0420a41f        adr     z31\.d, \[z0\.d, z0\.d, sxtw #1\]
+.*:    0420a41f        adr     z31\.d, \[z0\.d, z0\.d, sxtw #1\]
+.*:    0420a440        adr     z0\.d, \[z2\.d, z0\.d, sxtw #1\]
+.*:    0420a440        adr     z0\.d, \[z2\.d, z0\.d, sxtw #1\]
+.*:    0420a7e0        adr     z0\.d, \[z31\.d, z0\.d, sxtw #1\]
+.*:    0420a7e0        adr     z0\.d, \[z31\.d, z0\.d, sxtw #1\]
+.*:    0423a400        adr     z0\.d, \[z0\.d, z3\.d, sxtw #1\]
+.*:    0423a400        adr     z0\.d, \[z0\.d, z3\.d, sxtw #1\]
+.*:    043fa400        adr     z0\.d, \[z0\.d, z31\.d, sxtw #1\]
+.*:    043fa400        adr     z0\.d, \[z0\.d, z31\.d, sxtw #1\]
+.*:    0420a800        adr     z0\.d, \[z0\.d, z0\.d, sxtw #2\]
+.*:    0420a800        adr     z0\.d, \[z0\.d, z0\.d, sxtw #2\]
+.*:    0420a801        adr     z1\.d, \[z0\.d, z0\.d, sxtw #2\]
+.*:    0420a801        adr     z1\.d, \[z0\.d, z0\.d, sxtw #2\]
+.*:    0420a81f        adr     z31\.d, \[z0\.d, z0\.d, sxtw #2\]
+.*:    0420a81f        adr     z31\.d, \[z0\.d, z0\.d, sxtw #2\]
+.*:    0420a840        adr     z0\.d, \[z2\.d, z0\.d, sxtw #2\]
+.*:    0420a840        adr     z0\.d, \[z2\.d, z0\.d, sxtw #2\]
+.*:    0420abe0        adr     z0\.d, \[z31\.d, z0\.d, sxtw #2\]
+.*:    0420abe0        adr     z0\.d, \[z31\.d, z0\.d, sxtw #2\]
+.*:    0423a800        adr     z0\.d, \[z0\.d, z3\.d, sxtw #2\]
+.*:    0423a800        adr     z0\.d, \[z0\.d, z3\.d, sxtw #2\]
+.*:    043fa800        adr     z0\.d, \[z0\.d, z31\.d, sxtw #2\]
+.*:    043fa800        adr     z0\.d, \[z0\.d, z31\.d, sxtw #2\]
+.*:    0420ac00        adr     z0\.d, \[z0\.d, z0\.d, sxtw #3\]
+.*:    0420ac00        adr     z0\.d, \[z0\.d, z0\.d, sxtw #3\]
+.*:    0420ac01        adr     z1\.d, \[z0\.d, z0\.d, sxtw #3\]
+.*:    0420ac01        adr     z1\.d, \[z0\.d, z0\.d, sxtw #3\]
+.*:    0420ac1f        adr     z31\.d, \[z0\.d, z0\.d, sxtw #3\]
+.*:    0420ac1f        adr     z31\.d, \[z0\.d, z0\.d, sxtw #3\]
+.*:    0420ac40        adr     z0\.d, \[z2\.d, z0\.d, sxtw #3\]
+.*:    0420ac40        adr     z0\.d, \[z2\.d, z0\.d, sxtw #3\]
+.*:    0420afe0        adr     z0\.d, \[z31\.d, z0\.d, sxtw #3\]
+.*:    0420afe0        adr     z0\.d, \[z31\.d, z0\.d, sxtw #3\]
+.*:    0423ac00        adr     z0\.d, \[z0\.d, z3\.d, sxtw #3\]
+.*:    0423ac00        adr     z0\.d, \[z0\.d, z3\.d, sxtw #3\]
+.*:    043fac00        adr     z0\.d, \[z0\.d, z31\.d, sxtw #3\]
+.*:    043fac00        adr     z0\.d, \[z0\.d, z31\.d, sxtw #3\]
+.*:    0460a000        adr     z0\.d, \[z0\.d, z0\.d, uxtw\]
+.*:    0460a000        adr     z0\.d, \[z0\.d, z0\.d, uxtw\]
+.*:    0460a000        adr     z0\.d, \[z0\.d, z0\.d, uxtw\]
+.*:    0460a001        adr     z1\.d, \[z0\.d, z0\.d, uxtw\]
+.*:    0460a001        adr     z1\.d, \[z0\.d, z0\.d, uxtw\]
+.*:    0460a001        adr     z1\.d, \[z0\.d, z0\.d, uxtw\]
+.*:    0460a01f        adr     z31\.d, \[z0\.d, z0\.d, uxtw\]
+.*:    0460a01f        adr     z31\.d, \[z0\.d, z0\.d, uxtw\]
+.*:    0460a01f        adr     z31\.d, \[z0\.d, z0\.d, uxtw\]
+.*:    0460a040        adr     z0\.d, \[z2\.d, z0\.d, uxtw\]
+.*:    0460a040        adr     z0\.d, \[z2\.d, z0\.d, uxtw\]
+.*:    0460a040        adr     z0\.d, \[z2\.d, z0\.d, uxtw\]
+.*:    0460a3e0        adr     z0\.d, \[z31\.d, z0\.d, uxtw\]
+.*:    0460a3e0        adr     z0\.d, \[z31\.d, z0\.d, uxtw\]
+.*:    0460a3e0        adr     z0\.d, \[z31\.d, z0\.d, uxtw\]
+.*:    0463a000        adr     z0\.d, \[z0\.d, z3\.d, uxtw\]
+.*:    0463a000        adr     z0\.d, \[z0\.d, z3\.d, uxtw\]
+.*:    0463a000        adr     z0\.d, \[z0\.d, z3\.d, uxtw\]
+.*:    047fa000        adr     z0\.d, \[z0\.d, z31\.d, uxtw\]
+.*:    047fa000        adr     z0\.d, \[z0\.d, z31\.d, uxtw\]
+.*:    047fa000        adr     z0\.d, \[z0\.d, z31\.d, uxtw\]
+.*:    0460a400        adr     z0\.d, \[z0\.d, z0\.d, uxtw #1\]
+.*:    0460a400        adr     z0\.d, \[z0\.d, z0\.d, uxtw #1\]
+.*:    0460a401        adr     z1\.d, \[z0\.d, z0\.d, uxtw #1\]
+.*:    0460a401        adr     z1\.d, \[z0\.d, z0\.d, uxtw #1\]
+.*:    0460a41f        adr     z31\.d, \[z0\.d, z0\.d, uxtw #1\]
+.*:    0460a41f        adr     z31\.d, \[z0\.d, z0\.d, uxtw #1\]
+.*:    0460a440        adr     z0\.d, \[z2\.d, z0\.d, uxtw #1\]
+.*:    0460a440        adr     z0\.d, \[z2\.d, z0\.d, uxtw #1\]
+.*:    0460a7e0        adr     z0\.d, \[z31\.d, z0\.d, uxtw #1\]
+.*:    0460a7e0        adr     z0\.d, \[z31\.d, z0\.d, uxtw #1\]
+.*:    0463a400        adr     z0\.d, \[z0\.d, z3\.d, uxtw #1\]
+.*:    0463a400        adr     z0\.d, \[z0\.d, z3\.d, uxtw #1\]
+.*:    047fa400        adr     z0\.d, \[z0\.d, z31\.d, uxtw #1\]
+.*:    047fa400        adr     z0\.d, \[z0\.d, z31\.d, uxtw #1\]
+.*:    0460a800        adr     z0\.d, \[z0\.d, z0\.d, uxtw #2\]
+.*:    0460a800        adr     z0\.d, \[z0\.d, z0\.d, uxtw #2\]
+.*:    0460a801        adr     z1\.d, \[z0\.d, z0\.d, uxtw #2\]
+.*:    0460a801        adr     z1\.d, \[z0\.d, z0\.d, uxtw #2\]
+.*:    0460a81f        adr     z31\.d, \[z0\.d, z0\.d, uxtw #2\]
+.*:    0460a81f        adr     z31\.d, \[z0\.d, z0\.d, uxtw #2\]
+.*:    0460a840        adr     z0\.d, \[z2\.d, z0\.d, uxtw #2\]
+.*:    0460a840        adr     z0\.d, \[z2\.d, z0\.d, uxtw #2\]
+.*:    0460abe0        adr     z0\.d, \[z31\.d, z0\.d, uxtw #2\]
+.*:    0460abe0        adr     z0\.d, \[z31\.d, z0\.d, uxtw #2\]
+.*:    0463a800        adr     z0\.d, \[z0\.d, z3\.d, uxtw #2\]
+.*:    0463a800        adr     z0\.d, \[z0\.d, z3\.d, uxtw #2\]
+.*:    047fa800        adr     z0\.d, \[z0\.d, z31\.d, uxtw #2\]
+.*:    047fa800        adr     z0\.d, \[z0\.d, z31\.d, uxtw #2\]
+.*:    0460ac00        adr     z0\.d, \[z0\.d, z0\.d, uxtw #3\]
+.*:    0460ac00        adr     z0\.d, \[z0\.d, z0\.d, uxtw #3\]
+.*:    0460ac01        adr     z1\.d, \[z0\.d, z0\.d, uxtw #3\]
+.*:    0460ac01        adr     z1\.d, \[z0\.d, z0\.d, uxtw #3\]
+.*:    0460ac1f        adr     z31\.d, \[z0\.d, z0\.d, uxtw #3\]
+.*:    0460ac1f        adr     z31\.d, \[z0\.d, z0\.d, uxtw #3\]
+.*:    0460ac40        adr     z0\.d, \[z2\.d, z0\.d, uxtw #3\]
+.*:    0460ac40        adr     z0\.d, \[z2\.d, z0\.d, uxtw #3\]
+.*:    0460afe0        adr     z0\.d, \[z31\.d, z0\.d, uxtw #3\]
+.*:    0460afe0        adr     z0\.d, \[z31\.d, z0\.d, uxtw #3\]
+.*:    0463ac00        adr     z0\.d, \[z0\.d, z3\.d, uxtw #3\]
+.*:    0463ac00        adr     z0\.d, \[z0\.d, z3\.d, uxtw #3\]
+.*:    047fac00        adr     z0\.d, \[z0\.d, z31\.d, uxtw #3\]
+.*:    047fac00        adr     z0\.d, \[z0\.d, z31\.d, uxtw #3\]
+.*:    04a0a000        adr     z0\.s, \[z0\.s, z0\.s\]
+.*:    04a0a000        adr     z0\.s, \[z0\.s, z0\.s\]
+.*:    04a0a000        adr     z0\.s, \[z0\.s, z0\.s\]
+.*:    04a0a001        adr     z1\.s, \[z0\.s, z0\.s\]
+.*:    04a0a001        adr     z1\.s, \[z0\.s, z0\.s\]
+.*:    04a0a001        adr     z1\.s, \[z0\.s, z0\.s\]
+.*:    04a0a01f        adr     z31\.s, \[z0\.s, z0\.s\]
+.*:    04a0a01f        adr     z31\.s, \[z0\.s, z0\.s\]
+.*:    04a0a01f        adr     z31\.s, \[z0\.s, z0\.s\]
+.*:    04a0a040        adr     z0\.s, \[z2\.s, z0\.s\]
+.*:    04a0a040        adr     z0\.s, \[z2\.s, z0\.s\]
+.*:    04a0a040        adr     z0\.s, \[z2\.s, z0\.s\]
+.*:    04a0a3e0        adr     z0\.s, \[z31\.s, z0\.s\]
+.*:    04a0a3e0        adr     z0\.s, \[z31\.s, z0\.s\]
+.*:    04a0a3e0        adr     z0\.s, \[z31\.s, z0\.s\]
+.*:    04a3a000        adr     z0\.s, \[z0\.s, z3\.s\]
+.*:    04a3a000        adr     z0\.s, \[z0\.s, z3\.s\]
+.*:    04a3a000        adr     z0\.s, \[z0\.s, z3\.s\]
+.*:    04bfa000        adr     z0\.s, \[z0\.s, z31\.s\]
+.*:    04bfa000        adr     z0\.s, \[z0\.s, z31\.s\]
+.*:    04bfa000        adr     z0\.s, \[z0\.s, z31\.s\]
+.*:    04a0a400        adr     z0\.s, \[z0\.s, z0\.s, lsl #1\]
+.*:    04a0a400        adr     z0\.s, \[z0\.s, z0\.s, lsl #1\]
+.*:    04a0a401        adr     z1\.s, \[z0\.s, z0\.s, lsl #1\]
+.*:    04a0a401        adr     z1\.s, \[z0\.s, z0\.s, lsl #1\]
+.*:    04a0a41f        adr     z31\.s, \[z0\.s, z0\.s, lsl #1\]
+.*:    04a0a41f        adr     z31\.s, \[z0\.s, z0\.s, lsl #1\]
+.*:    04a0a440        adr     z0\.s, \[z2\.s, z0\.s, lsl #1\]
+.*:    04a0a440        adr     z0\.s, \[z2\.s, z0\.s, lsl #1\]
+.*:    04a0a7e0        adr     z0\.s, \[z31\.s, z0\.s, lsl #1\]
+.*:    04a0a7e0        adr     z0\.s, \[z31\.s, z0\.s, lsl #1\]
+.*:    04a3a400        adr     z0\.s, \[z0\.s, z3\.s, lsl #1\]
+.*:    04a3a400        adr     z0\.s, \[z0\.s, z3\.s, lsl #1\]
+.*:    04bfa400        adr     z0\.s, \[z0\.s, z31\.s, lsl #1\]
+.*:    04bfa400        adr     z0\.s, \[z0\.s, z31\.s, lsl #1\]
+.*:    04a0a800        adr     z0\.s, \[z0\.s, z0\.s, lsl #2\]
+.*:    04a0a800        adr     z0\.s, \[z0\.s, z0\.s, lsl #2\]
+.*:    04a0a801        adr     z1\.s, \[z0\.s, z0\.s, lsl #2\]
+.*:    04a0a801        adr     z1\.s, \[z0\.s, z0\.s, lsl #2\]
+.*:    04a0a81f        adr     z31\.s, \[z0\.s, z0\.s, lsl #2\]
+.*:    04a0a81f        adr     z31\.s, \[z0\.s, z0\.s, lsl #2\]
+.*:    04a0a840        adr     z0\.s, \[z2\.s, z0\.s, lsl #2\]
+.*:    04a0a840        adr     z0\.s, \[z2\.s, z0\.s, lsl #2\]
+.*:    04a0abe0        adr     z0\.s, \[z31\.s, z0\.s, lsl #2\]
+.*:    04a0abe0        adr     z0\.s, \[z31\.s, z0\.s, lsl #2\]
+.*:    04a3a800        adr     z0\.s, \[z0\.s, z3\.s, lsl #2\]
+.*:    04a3a800        adr     z0\.s, \[z0\.s, z3\.s, lsl #2\]
+.*:    04bfa800        adr     z0\.s, \[z0\.s, z31\.s, lsl #2\]
+.*:    04bfa800        adr     z0\.s, \[z0\.s, z31\.s, lsl #2\]
+.*:    04a0ac00        adr     z0\.s, \[z0\.s, z0\.s, lsl #3\]
+.*:    04a0ac00        adr     z0\.s, \[z0\.s, z0\.s, lsl #3\]
+.*:    04a0ac01        adr     z1\.s, \[z0\.s, z0\.s, lsl #3\]
+.*:    04a0ac01        adr     z1\.s, \[z0\.s, z0\.s, lsl #3\]
+.*:    04a0ac1f        adr     z31\.s, \[z0\.s, z0\.s, lsl #3\]
+.*:    04a0ac1f        adr     z31\.s, \[z0\.s, z0\.s, lsl #3\]
+.*:    04a0ac40        adr     z0\.s, \[z2\.s, z0\.s, lsl #3\]
+.*:    04a0ac40        adr     z0\.s, \[z2\.s, z0\.s, lsl #3\]
+.*:    04a0afe0        adr     z0\.s, \[z31\.s, z0\.s, lsl #3\]
+.*:    04a0afe0        adr     z0\.s, \[z31\.s, z0\.s, lsl #3\]
+.*:    04a3ac00        adr     z0\.s, \[z0\.s, z3\.s, lsl #3\]
+.*:    04a3ac00        adr     z0\.s, \[z0\.s, z3\.s, lsl #3\]
+.*:    04bfac00        adr     z0\.s, \[z0\.s, z31\.s, lsl #3\]
+.*:    04bfac00        adr     z0\.s, \[z0\.s, z31\.s, lsl #3\]
+.*:    04e0a000        adr     z0\.d, \[z0\.d, z0\.d\]
+.*:    04e0a000        adr     z0\.d, \[z0\.d, z0\.d\]
+.*:    04e0a000        adr     z0\.d, \[z0\.d, z0\.d\]
+.*:    04e0a001        adr     z1\.d, \[z0\.d, z0\.d\]
+.*:    04e0a001        adr     z1\.d, \[z0\.d, z0\.d\]
+.*:    04e0a001        adr     z1\.d, \[z0\.d, z0\.d\]
+.*:    04e0a01f        adr     z31\.d, \[z0\.d, z0\.d\]
+.*:    04e0a01f        adr     z31\.d, \[z0\.d, z0\.d\]
+.*:    04e0a01f        adr     z31\.d, \[z0\.d, z0\.d\]
+.*:    04e0a040        adr     z0\.d, \[z2\.d, z0\.d\]
+.*:    04e0a040        adr     z0\.d, \[z2\.d, z0\.d\]
+.*:    04e0a040        adr     z0\.d, \[z2\.d, z0\.d\]
+.*:    04e0a3e0        adr     z0\.d, \[z31\.d, z0\.d\]
+.*:    04e0a3e0        adr     z0\.d, \[z31\.d, z0\.d\]
+.*:    04e0a3e0        adr     z0\.d, \[z31\.d, z0\.d\]
+.*:    04e3a000        adr     z0\.d, \[z0\.d, z3\.d\]
+.*:    04e3a000        adr     z0\.d, \[z0\.d, z3\.d\]
+.*:    04e3a000        adr     z0\.d, \[z0\.d, z3\.d\]
+.*:    04ffa000        adr     z0\.d, \[z0\.d, z31\.d\]
+.*:    04ffa000        adr     z0\.d, \[z0\.d, z31\.d\]
+.*:    04ffa000        adr     z0\.d, \[z0\.d, z31\.d\]
+.*:    04e0a400        adr     z0\.d, \[z0\.d, z0\.d, lsl #1\]
+.*:    04e0a400        adr     z0\.d, \[z0\.d, z0\.d, lsl #1\]
+.*:    04e0a401        adr     z1\.d, \[z0\.d, z0\.d, lsl #1\]
+.*:    04e0a401        adr     z1\.d, \[z0\.d, z0\.d, lsl #1\]
+.*:    04e0a41f        adr     z31\.d, \[z0\.d, z0\.d, lsl #1\]
+.*:    04e0a41f        adr     z31\.d, \[z0\.d, z0\.d, lsl #1\]
+.*:    04e0a440        adr     z0\.d, \[z2\.d, z0\.d, lsl #1\]
+.*:    04e0a440        adr     z0\.d, \[z2\.d, z0\.d, lsl #1\]
+.*:    04e0a7e0        adr     z0\.d, \[z31\.d, z0\.d, lsl #1\]
+.*:    04e0a7e0        adr     z0\.d, \[z31\.d, z0\.d, lsl #1\]
+.*:    04e3a400        adr     z0\.d, \[z0\.d, z3\.d, lsl #1\]
+.*:    04e3a400        adr     z0\.d, \[z0\.d, z3\.d, lsl #1\]
+.*:    04ffa400        adr     z0\.d, \[z0\.d, z31\.d, lsl #1\]
+.*:    04ffa400        adr     z0\.d, \[z0\.d, z31\.d, lsl #1\]
+.*:    04e0a800        adr     z0\.d, \[z0\.d, z0\.d, lsl #2\]
+.*:    04e0a800        adr     z0\.d, \[z0\.d, z0\.d, lsl #2\]
+.*:    04e0a801        adr     z1\.d, \[z0\.d, z0\.d, lsl #2\]
+.*:    04e0a801        adr     z1\.d, \[z0\.d, z0\.d, lsl #2\]
+.*:    04e0a81f        adr     z31\.d, \[z0\.d, z0\.d, lsl #2\]
+.*:    04e0a81f        adr     z31\.d, \[z0\.d, z0\.d, lsl #2\]
+.*:    04e0a840        adr     z0\.d, \[z2\.d, z0\.d, lsl #2\]
+.*:    04e0a840        adr     z0\.d, \[z2\.d, z0\.d, lsl #2\]
+.*:    04e0abe0        adr     z0\.d, \[z31\.d, z0\.d, lsl #2\]
+.*:    04e0abe0        adr     z0\.d, \[z31\.d, z0\.d, lsl #2\]
+.*:    04e3a800        adr     z0\.d, \[z0\.d, z3\.d, lsl #2\]
+.*:    04e3a800        adr     z0\.d, \[z0\.d, z3\.d, lsl #2\]
+.*:    04ffa800        adr     z0\.d, \[z0\.d, z31\.d, lsl #2\]
+.*:    04ffa800        adr     z0\.d, \[z0\.d, z31\.d, lsl #2\]
+.*:    04e0ac00        adr     z0\.d, \[z0\.d, z0\.d, lsl #3\]
+.*:    04e0ac00        adr     z0\.d, \[z0\.d, z0\.d, lsl #3\]
+.*:    04e0ac01        adr     z1\.d, \[z0\.d, z0\.d, lsl #3\]
+.*:    04e0ac01        adr     z1\.d, \[z0\.d, z0\.d, lsl #3\]
+.*:    04e0ac1f        adr     z31\.d, \[z0\.d, z0\.d, lsl #3\]
+.*:    04e0ac1f        adr     z31\.d, \[z0\.d, z0\.d, lsl #3\]
+.*:    04e0ac40        adr     z0\.d, \[z2\.d, z0\.d, lsl #3\]
+.*:    04e0ac40        adr     z0\.d, \[z2\.d, z0\.d, lsl #3\]
+.*:    04e0afe0        adr     z0\.d, \[z31\.d, z0\.d, lsl #3\]
+.*:    04e0afe0        adr     z0\.d, \[z31\.d, z0\.d, lsl #3\]
+.*:    04e3ac00        adr     z0\.d, \[z0\.d, z3\.d, lsl #3\]
+.*:    04e3ac00        adr     z0\.d, \[z0\.d, z3\.d, lsl #3\]
+.*:    04ffac00        adr     z0\.d, \[z0\.d, z31\.d, lsl #3\]
+.*:    04ffac00        adr     z0\.d, \[z0\.d, z31\.d, lsl #3\]
 .*:    04203000        and     z0\.d, z0\.d, z0\.d
 .*:    04203000        and     z0\.d, z0\.d, z0\.d
 .*:    04203001        and     z1\.d, z0\.d, z0\.d
@@ -12155,276 +12155,276 @@ Disassembly of section .*:
 .*:    05e38060        lastb   d0, p0, z3\.d
 .*:    05e383e0        lastb   d0, p0, z31\.d
 .*:    05e383e0        lastb   d0, p0, z31\.d
-.*:    84004000        ld1b    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84004000        ld1b    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84004000        ld1b    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84004000        ld1b    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84004001        ld1b    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84004001        ld1b    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84004001        ld1b    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84004001        ld1b    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400401f        ld1b    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400401f        ld1b    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400401f        ld1b    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400401f        ld1b    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84004800        ld1b    \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84004800        ld1b    \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84004800        ld1b    \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84005c00        ld1b    \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84005c00        ld1b    \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84005c00        ld1b    \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84004060        ld1b    \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84004060        ld1b    \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84004060        ld1b    \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    840043e0        ld1b    \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    840043e0        ld1b    \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    840043e0        ld1b    \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    84044000        ld1b    \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84044000        ld1b    \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84044000        ld1b    \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    841f4000        ld1b    \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    841f4000        ld1b    \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    841f4000        ld1b    \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    84404000        ld1b    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84404000        ld1b    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84404000        ld1b    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84404000        ld1b    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84404001        ld1b    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84404001        ld1b    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84404001        ld1b    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84404001        ld1b    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440401f        ld1b    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440401f        ld1b    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440401f        ld1b    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440401f        ld1b    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84404800        ld1b    \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84404800        ld1b    \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84404800        ld1b    \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84405c00        ld1b    \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84405c00        ld1b    \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84405c00        ld1b    \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84404060        ld1b    \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84404060        ld1b    \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84404060        ld1b    \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    844043e0        ld1b    \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    844043e0        ld1b    \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    844043e0        ld1b    \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84444000        ld1b    \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84444000        ld1b    \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84444000        ld1b    \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    845f4000        ld1b    \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    845f4000        ld1b    \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    845f4000        ld1b    \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    a4004000        ld1b    \{z0\.b\}, p0/z, \[x0,x0\]
-.*:    a4004000        ld1b    \{z0\.b\}, p0/z, \[x0,x0\]
-.*:    a4004000        ld1b    \{z0\.b\}, p0/z, \[x0,x0\]
-.*:    a4004000        ld1b    \{z0\.b\}, p0/z, \[x0,x0\]
-.*:    a4004001        ld1b    \{z1\.b\}, p0/z, \[x0,x0\]
-.*:    a4004001        ld1b    \{z1\.b\}, p0/z, \[x0,x0\]
-.*:    a4004001        ld1b    \{z1\.b\}, p0/z, \[x0,x0\]
-.*:    a4004001        ld1b    \{z1\.b\}, p0/z, \[x0,x0\]
-.*:    a400401f        ld1b    \{z31\.b\}, p0/z, \[x0,x0\]
-.*:    a400401f        ld1b    \{z31\.b\}, p0/z, \[x0,x0\]
-.*:    a400401f        ld1b    \{z31\.b\}, p0/z, \[x0,x0\]
-.*:    a400401f        ld1b    \{z31\.b\}, p0/z, \[x0,x0\]
-.*:    a4004800        ld1b    \{z0\.b\}, p2/z, \[x0,x0\]
-.*:    a4004800        ld1b    \{z0\.b\}, p2/z, \[x0,x0\]
-.*:    a4004800        ld1b    \{z0\.b\}, p2/z, \[x0,x0\]
-.*:    a4005c00        ld1b    \{z0\.b\}, p7/z, \[x0,x0\]
-.*:    a4005c00        ld1b    \{z0\.b\}, p7/z, \[x0,x0\]
-.*:    a4005c00        ld1b    \{z0\.b\}, p7/z, \[x0,x0\]
-.*:    a4004060        ld1b    \{z0\.b\}, p0/z, \[x3,x0\]
-.*:    a4004060        ld1b    \{z0\.b\}, p0/z, \[x3,x0\]
-.*:    a4004060        ld1b    \{z0\.b\}, p0/z, \[x3,x0\]
-.*:    a40043e0        ld1b    \{z0\.b\}, p0/z, \[sp,x0\]
-.*:    a40043e0        ld1b    \{z0\.b\}, p0/z, \[sp,x0\]
-.*:    a40043e0        ld1b    \{z0\.b\}, p0/z, \[sp,x0\]
-.*:    a4044000        ld1b    \{z0\.b\}, p0/z, \[x0,x4\]
-.*:    a4044000        ld1b    \{z0\.b\}, p0/z, \[x0,x4\]
-.*:    a4044000        ld1b    \{z0\.b\}, p0/z, \[x0,x4\]
-.*:    a41e4000        ld1b    \{z0\.b\}, p0/z, \[x0,x30\]
-.*:    a41e4000        ld1b    \{z0\.b\}, p0/z, \[x0,x30\]
-.*:    a41e4000        ld1b    \{z0\.b\}, p0/z, \[x0,x30\]
-.*:    a4204000        ld1b    \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a4204000        ld1b    \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a4204000        ld1b    \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a4204000        ld1b    \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a4204001        ld1b    \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a4204001        ld1b    \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a4204001        ld1b    \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a4204001        ld1b    \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a420401f        ld1b    \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a420401f        ld1b    \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a420401f        ld1b    \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a420401f        ld1b    \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a4204800        ld1b    \{z0\.h\}, p2/z, \[x0,x0\]
-.*:    a4204800        ld1b    \{z0\.h\}, p2/z, \[x0,x0\]
-.*:    a4204800        ld1b    \{z0\.h\}, p2/z, \[x0,x0\]
-.*:    a4205c00        ld1b    \{z0\.h\}, p7/z, \[x0,x0\]
-.*:    a4205c00        ld1b    \{z0\.h\}, p7/z, \[x0,x0\]
-.*:    a4205c00        ld1b    \{z0\.h\}, p7/z, \[x0,x0\]
-.*:    a4204060        ld1b    \{z0\.h\}, p0/z, \[x3,x0\]
-.*:    a4204060        ld1b    \{z0\.h\}, p0/z, \[x3,x0\]
-.*:    a4204060        ld1b    \{z0\.h\}, p0/z, \[x3,x0\]
-.*:    a42043e0        ld1b    \{z0\.h\}, p0/z, \[sp,x0\]
-.*:    a42043e0        ld1b    \{z0\.h\}, p0/z, \[sp,x0\]
-.*:    a42043e0        ld1b    \{z0\.h\}, p0/z, \[sp,x0\]
-.*:    a4244000        ld1b    \{z0\.h\}, p0/z, \[x0,x4\]
-.*:    a4244000        ld1b    \{z0\.h\}, p0/z, \[x0,x4\]
-.*:    a4244000        ld1b    \{z0\.h\}, p0/z, \[x0,x4\]
-.*:    a43e4000        ld1b    \{z0\.h\}, p0/z, \[x0,x30\]
-.*:    a43e4000        ld1b    \{z0\.h\}, p0/z, \[x0,x30\]
-.*:    a43e4000        ld1b    \{z0\.h\}, p0/z, \[x0,x30\]
-.*:    a4404000        ld1b    \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a4404000        ld1b    \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a4404000        ld1b    \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a4404000        ld1b    \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a4404001        ld1b    \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a4404001        ld1b    \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a4404001        ld1b    \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a4404001        ld1b    \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a440401f        ld1b    \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a440401f        ld1b    \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a440401f        ld1b    \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a440401f        ld1b    \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a4404800        ld1b    \{z0\.s\}, p2/z, \[x0,x0\]
-.*:    a4404800        ld1b    \{z0\.s\}, p2/z, \[x0,x0\]
-.*:    a4404800        ld1b    \{z0\.s\}, p2/z, \[x0,x0\]
-.*:    a4405c00        ld1b    \{z0\.s\}, p7/z, \[x0,x0\]
-.*:    a4405c00        ld1b    \{z0\.s\}, p7/z, \[x0,x0\]
-.*:    a4405c00        ld1b    \{z0\.s\}, p7/z, \[x0,x0\]
-.*:    a4404060        ld1b    \{z0\.s\}, p0/z, \[x3,x0\]
-.*:    a4404060        ld1b    \{z0\.s\}, p0/z, \[x3,x0\]
-.*:    a4404060        ld1b    \{z0\.s\}, p0/z, \[x3,x0\]
-.*:    a44043e0        ld1b    \{z0\.s\}, p0/z, \[sp,x0\]
-.*:    a44043e0        ld1b    \{z0\.s\}, p0/z, \[sp,x0\]
-.*:    a44043e0        ld1b    \{z0\.s\}, p0/z, \[sp,x0\]
-.*:    a4444000        ld1b    \{z0\.s\}, p0/z, \[x0,x4\]
-.*:    a4444000        ld1b    \{z0\.s\}, p0/z, \[x0,x4\]
-.*:    a4444000        ld1b    \{z0\.s\}, p0/z, \[x0,x4\]
-.*:    a45e4000        ld1b    \{z0\.s\}, p0/z, \[x0,x30\]
-.*:    a45e4000        ld1b    \{z0\.s\}, p0/z, \[x0,x30\]
-.*:    a45e4000        ld1b    \{z0\.s\}, p0/z, \[x0,x30\]
-.*:    a4604000        ld1b    \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a4604000        ld1b    \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a4604000        ld1b    \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a4604000        ld1b    \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a4604001        ld1b    \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a4604001        ld1b    \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a4604001        ld1b    \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a4604001        ld1b    \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a460401f        ld1b    \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a460401f        ld1b    \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a460401f        ld1b    \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a460401f        ld1b    \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a4604800        ld1b    \{z0\.d\}, p2/z, \[x0,x0\]
-.*:    a4604800        ld1b    \{z0\.d\}, p2/z, \[x0,x0\]
-.*:    a4604800        ld1b    \{z0\.d\}, p2/z, \[x0,x0\]
-.*:    a4605c00        ld1b    \{z0\.d\}, p7/z, \[x0,x0\]
-.*:    a4605c00        ld1b    \{z0\.d\}, p7/z, \[x0,x0\]
-.*:    a4605c00        ld1b    \{z0\.d\}, p7/z, \[x0,x0\]
-.*:    a4604060        ld1b    \{z0\.d\}, p0/z, \[x3,x0\]
-.*:    a4604060        ld1b    \{z0\.d\}, p0/z, \[x3,x0\]
-.*:    a4604060        ld1b    \{z0\.d\}, p0/z, \[x3,x0\]
-.*:    a46043e0        ld1b    \{z0\.d\}, p0/z, \[sp,x0\]
-.*:    a46043e0        ld1b    \{z0\.d\}, p0/z, \[sp,x0\]
-.*:    a46043e0        ld1b    \{z0\.d\}, p0/z, \[sp,x0\]
-.*:    a4644000        ld1b    \{z0\.d\}, p0/z, \[x0,x4\]
-.*:    a4644000        ld1b    \{z0\.d\}, p0/z, \[x0,x4\]
-.*:    a4644000        ld1b    \{z0\.d\}, p0/z, \[x0,x4\]
-.*:    a47e4000        ld1b    \{z0\.d\}, p0/z, \[x0,x30\]
-.*:    a47e4000        ld1b    \{z0\.d\}, p0/z, \[x0,x30\]
-.*:    a47e4000        ld1b    \{z0\.d\}, p0/z, \[x0,x30\]
-.*:    c4004000        ld1b    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4004000        ld1b    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4004000        ld1b    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4004000        ld1b    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4004001        ld1b    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4004001        ld1b    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4004001        ld1b    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4004001        ld1b    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400401f        ld1b    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400401f        ld1b    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400401f        ld1b    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400401f        ld1b    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4004800        ld1b    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4004800        ld1b    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4004800        ld1b    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4005c00        ld1b    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4005c00        ld1b    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4005c00        ld1b    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4004060        ld1b    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4004060        ld1b    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4004060        ld1b    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c40043e0        ld1b    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c40043e0        ld1b    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c40043e0        ld1b    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c4044000        ld1b    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4044000        ld1b    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4044000        ld1b    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c41f4000        ld1b    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c41f4000        ld1b    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c41f4000        ld1b    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c4404000        ld1b    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4404000        ld1b    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4404000        ld1b    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4404000        ld1b    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4404001        ld1b    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4404001        ld1b    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4404001        ld1b    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4404001        ld1b    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440401f        ld1b    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440401f        ld1b    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440401f        ld1b    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440401f        ld1b    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4404800        ld1b    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4404800        ld1b    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4404800        ld1b    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4405c00        ld1b    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4405c00        ld1b    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4405c00        ld1b    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4404060        ld1b    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4404060        ld1b    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4404060        ld1b    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c44043e0        ld1b    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c44043e0        ld1b    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c44043e0        ld1b    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4444000        ld1b    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4444000        ld1b    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4444000        ld1b    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c45f4000        ld1b    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c45f4000        ld1b    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c45f4000        ld1b    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c440c000        ld1b    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440c000        ld1b    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440c000        ld1b    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440c000        ld1b    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440c001        ld1b    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440c001        ld1b    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440c001        ld1b    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440c001        ld1b    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440c01f        ld1b    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440c01f        ld1b    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440c01f        ld1b    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440c01f        ld1b    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440c800        ld1b    \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c440c800        ld1b    \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c440c800        ld1b    \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c440dc00        ld1b    \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c440dc00        ld1b    \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c440dc00        ld1b    \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c440c060        ld1b    \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c440c060        ld1b    \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c440c060        ld1b    \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c440c3e0        ld1b    \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c440c3e0        ld1b    \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c440c3e0        ld1b    \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c444c000        ld1b    \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c444c000        ld1b    \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c444c000        ld1b    \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c45fc000        ld1b    \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c45fc000        ld1b    \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c45fc000        ld1b    \{z0\.d\}, p0/z, \[x0,z31\.d\]
+.*:    84004000        ld1b    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84004000        ld1b    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84004000        ld1b    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84004000        ld1b    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84004001        ld1b    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84004001        ld1b    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84004001        ld1b    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84004001        ld1b    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400401f        ld1b    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400401f        ld1b    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400401f        ld1b    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400401f        ld1b    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84004800        ld1b    \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84004800        ld1b    \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84004800        ld1b    \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84005c00        ld1b    \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84005c00        ld1b    \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84005c00        ld1b    \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84004060        ld1b    \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84004060        ld1b    \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84004060        ld1b    \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    840043e0        ld1b    \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    840043e0        ld1b    \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    840043e0        ld1b    \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    84044000        ld1b    \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84044000        ld1b    \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84044000        ld1b    \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    841f4000        ld1b    \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    841f4000        ld1b    \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    841f4000        ld1b    \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    84404000        ld1b    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84404000        ld1b    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84404000        ld1b    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84404000        ld1b    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84404001        ld1b    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84404001        ld1b    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84404001        ld1b    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84404001        ld1b    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440401f        ld1b    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440401f        ld1b    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440401f        ld1b    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440401f        ld1b    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84404800        ld1b    \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84404800        ld1b    \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84404800        ld1b    \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84405c00        ld1b    \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84405c00        ld1b    \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84405c00        ld1b    \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84404060        ld1b    \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84404060        ld1b    \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84404060        ld1b    \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    844043e0        ld1b    \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    844043e0        ld1b    \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    844043e0        ld1b    \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84444000        ld1b    \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84444000        ld1b    \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84444000        ld1b    \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    845f4000        ld1b    \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    845f4000        ld1b    \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    845f4000        ld1b    \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    a4004000        ld1b    \{z0\.b\}, p0/z, \[x0, x0\]
+.*:    a4004000        ld1b    \{z0\.b\}, p0/z, \[x0, x0\]
+.*:    a4004000        ld1b    \{z0\.b\}, p0/z, \[x0, x0\]
+.*:    a4004000        ld1b    \{z0\.b\}, p0/z, \[x0, x0\]
+.*:    a4004001        ld1b    \{z1\.b\}, p0/z, \[x0, x0\]
+.*:    a4004001        ld1b    \{z1\.b\}, p0/z, \[x0, x0\]
+.*:    a4004001        ld1b    \{z1\.b\}, p0/z, \[x0, x0\]
+.*:    a4004001        ld1b    \{z1\.b\}, p0/z, \[x0, x0\]
+.*:    a400401f        ld1b    \{z31\.b\}, p0/z, \[x0, x0\]
+.*:    a400401f        ld1b    \{z31\.b\}, p0/z, \[x0, x0\]
+.*:    a400401f        ld1b    \{z31\.b\}, p0/z, \[x0, x0\]
+.*:    a400401f        ld1b    \{z31\.b\}, p0/z, \[x0, x0\]
+.*:    a4004800        ld1b    \{z0\.b\}, p2/z, \[x0, x0\]
+.*:    a4004800        ld1b    \{z0\.b\}, p2/z, \[x0, x0\]
+.*:    a4004800        ld1b    \{z0\.b\}, p2/z, \[x0, x0\]
+.*:    a4005c00        ld1b    \{z0\.b\}, p7/z, \[x0, x0\]
+.*:    a4005c00        ld1b    \{z0\.b\}, p7/z, \[x0, x0\]
+.*:    a4005c00        ld1b    \{z0\.b\}, p7/z, \[x0, x0\]
+.*:    a4004060        ld1b    \{z0\.b\}, p0/z, \[x3, x0\]
+.*:    a4004060        ld1b    \{z0\.b\}, p0/z, \[x3, x0\]
+.*:    a4004060        ld1b    \{z0\.b\}, p0/z, \[x3, x0\]
+.*:    a40043e0        ld1b    \{z0\.b\}, p0/z, \[sp, x0\]
+.*:    a40043e0        ld1b    \{z0\.b\}, p0/z, \[sp, x0\]
+.*:    a40043e0        ld1b    \{z0\.b\}, p0/z, \[sp, x0\]
+.*:    a4044000        ld1b    \{z0\.b\}, p0/z, \[x0, x4\]
+.*:    a4044000        ld1b    \{z0\.b\}, p0/z, \[x0, x4\]
+.*:    a4044000        ld1b    \{z0\.b\}, p0/z, \[x0, x4\]
+.*:    a41e4000        ld1b    \{z0\.b\}, p0/z, \[x0, x30\]
+.*:    a41e4000        ld1b    \{z0\.b\}, p0/z, \[x0, x30\]
+.*:    a41e4000        ld1b    \{z0\.b\}, p0/z, \[x0, x30\]
+.*:    a4204000        ld1b    \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a4204000        ld1b    \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a4204000        ld1b    \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a4204000        ld1b    \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a4204001        ld1b    \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a4204001        ld1b    \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a4204001        ld1b    \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a4204001        ld1b    \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a420401f        ld1b    \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a420401f        ld1b    \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a420401f        ld1b    \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a420401f        ld1b    \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a4204800        ld1b    \{z0\.h\}, p2/z, \[x0, x0\]
+.*:    a4204800        ld1b    \{z0\.h\}, p2/z, \[x0, x0\]
+.*:    a4204800        ld1b    \{z0\.h\}, p2/z, \[x0, x0\]
+.*:    a4205c00        ld1b    \{z0\.h\}, p7/z, \[x0, x0\]
+.*:    a4205c00        ld1b    \{z0\.h\}, p7/z, \[x0, x0\]
+.*:    a4205c00        ld1b    \{z0\.h\}, p7/z, \[x0, x0\]
+.*:    a4204060        ld1b    \{z0\.h\}, p0/z, \[x3, x0\]
+.*:    a4204060        ld1b    \{z0\.h\}, p0/z, \[x3, x0\]
+.*:    a4204060        ld1b    \{z0\.h\}, p0/z, \[x3, x0\]
+.*:    a42043e0        ld1b    \{z0\.h\}, p0/z, \[sp, x0\]
+.*:    a42043e0        ld1b    \{z0\.h\}, p0/z, \[sp, x0\]
+.*:    a42043e0        ld1b    \{z0\.h\}, p0/z, \[sp, x0\]
+.*:    a4244000        ld1b    \{z0\.h\}, p0/z, \[x0, x4\]
+.*:    a4244000        ld1b    \{z0\.h\}, p0/z, \[x0, x4\]
+.*:    a4244000        ld1b    \{z0\.h\}, p0/z, \[x0, x4\]
+.*:    a43e4000        ld1b    \{z0\.h\}, p0/z, \[x0, x30\]
+.*:    a43e4000        ld1b    \{z0\.h\}, p0/z, \[x0, x30\]
+.*:    a43e4000        ld1b    \{z0\.h\}, p0/z, \[x0, x30\]
+.*:    a4404000        ld1b    \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a4404000        ld1b    \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a4404000        ld1b    \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a4404000        ld1b    \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a4404001        ld1b    \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a4404001        ld1b    \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a4404001        ld1b    \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a4404001        ld1b    \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a440401f        ld1b    \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a440401f        ld1b    \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a440401f        ld1b    \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a440401f        ld1b    \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a4404800        ld1b    \{z0\.s\}, p2/z, \[x0, x0\]
+.*:    a4404800        ld1b    \{z0\.s\}, p2/z, \[x0, x0\]
+.*:    a4404800        ld1b    \{z0\.s\}, p2/z, \[x0, x0\]
+.*:    a4405c00        ld1b    \{z0\.s\}, p7/z, \[x0, x0\]
+.*:    a4405c00        ld1b    \{z0\.s\}, p7/z, \[x0, x0\]
+.*:    a4405c00        ld1b    \{z0\.s\}, p7/z, \[x0, x0\]
+.*:    a4404060        ld1b    \{z0\.s\}, p0/z, \[x3, x0\]
+.*:    a4404060        ld1b    \{z0\.s\}, p0/z, \[x3, x0\]
+.*:    a4404060        ld1b    \{z0\.s\}, p0/z, \[x3, x0\]
+.*:    a44043e0        ld1b    \{z0\.s\}, p0/z, \[sp, x0\]
+.*:    a44043e0        ld1b    \{z0\.s\}, p0/z, \[sp, x0\]
+.*:    a44043e0        ld1b    \{z0\.s\}, p0/z, \[sp, x0\]
+.*:    a4444000        ld1b    \{z0\.s\}, p0/z, \[x0, x4\]
+.*:    a4444000        ld1b    \{z0\.s\}, p0/z, \[x0, x4\]
+.*:    a4444000        ld1b    \{z0\.s\}, p0/z, \[x0, x4\]
+.*:    a45e4000        ld1b    \{z0\.s\}, p0/z, \[x0, x30\]
+.*:    a45e4000        ld1b    \{z0\.s\}, p0/z, \[x0, x30\]
+.*:    a45e4000        ld1b    \{z0\.s\}, p0/z, \[x0, x30\]
+.*:    a4604000        ld1b    \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a4604000        ld1b    \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a4604000        ld1b    \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a4604000        ld1b    \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a4604001        ld1b    \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a4604001        ld1b    \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a4604001        ld1b    \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a4604001        ld1b    \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a460401f        ld1b    \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a460401f        ld1b    \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a460401f        ld1b    \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a460401f        ld1b    \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a4604800        ld1b    \{z0\.d\}, p2/z, \[x0, x0\]
+.*:    a4604800        ld1b    \{z0\.d\}, p2/z, \[x0, x0\]
+.*:    a4604800        ld1b    \{z0\.d\}, p2/z, \[x0, x0\]
+.*:    a4605c00        ld1b    \{z0\.d\}, p7/z, \[x0, x0\]
+.*:    a4605c00        ld1b    \{z0\.d\}, p7/z, \[x0, x0\]
+.*:    a4605c00        ld1b    \{z0\.d\}, p7/z, \[x0, x0\]
+.*:    a4604060        ld1b    \{z0\.d\}, p0/z, \[x3, x0\]
+.*:    a4604060        ld1b    \{z0\.d\}, p0/z, \[x3, x0\]
+.*:    a4604060        ld1b    \{z0\.d\}, p0/z, \[x3, x0\]
+.*:    a46043e0        ld1b    \{z0\.d\}, p0/z, \[sp, x0\]
+.*:    a46043e0        ld1b    \{z0\.d\}, p0/z, \[sp, x0\]
+.*:    a46043e0        ld1b    \{z0\.d\}, p0/z, \[sp, x0\]
+.*:    a4644000        ld1b    \{z0\.d\}, p0/z, \[x0, x4\]
+.*:    a4644000        ld1b    \{z0\.d\}, p0/z, \[x0, x4\]
+.*:    a4644000        ld1b    \{z0\.d\}, p0/z, \[x0, x4\]
+.*:    a47e4000        ld1b    \{z0\.d\}, p0/z, \[x0, x30\]
+.*:    a47e4000        ld1b    \{z0\.d\}, p0/z, \[x0, x30\]
+.*:    a47e4000        ld1b    \{z0\.d\}, p0/z, \[x0, x30\]
+.*:    c4004000        ld1b    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4004000        ld1b    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4004000        ld1b    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4004000        ld1b    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4004001        ld1b    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4004001        ld1b    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4004001        ld1b    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4004001        ld1b    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400401f        ld1b    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400401f        ld1b    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400401f        ld1b    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400401f        ld1b    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4004800        ld1b    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4004800        ld1b    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4004800        ld1b    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4005c00        ld1b    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4005c00        ld1b    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4005c00        ld1b    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4004060        ld1b    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4004060        ld1b    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4004060        ld1b    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c40043e0        ld1b    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c40043e0        ld1b    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c40043e0        ld1b    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c4044000        ld1b    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4044000        ld1b    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4044000        ld1b    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c41f4000        ld1b    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c41f4000        ld1b    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c41f4000        ld1b    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c4404000        ld1b    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4404000        ld1b    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4404000        ld1b    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4404000        ld1b    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4404001        ld1b    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4404001        ld1b    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4404001        ld1b    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4404001        ld1b    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440401f        ld1b    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440401f        ld1b    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440401f        ld1b    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440401f        ld1b    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4404800        ld1b    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4404800        ld1b    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4404800        ld1b    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4405c00        ld1b    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4405c00        ld1b    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4405c00        ld1b    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4404060        ld1b    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4404060        ld1b    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4404060        ld1b    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c44043e0        ld1b    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c44043e0        ld1b    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c44043e0        ld1b    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4444000        ld1b    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4444000        ld1b    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4444000        ld1b    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c45f4000        ld1b    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c45f4000        ld1b    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c45f4000        ld1b    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c440c000        ld1b    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440c000        ld1b    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440c000        ld1b    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440c000        ld1b    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440c001        ld1b    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440c001        ld1b    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440c001        ld1b    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440c001        ld1b    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440c01f        ld1b    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440c01f        ld1b    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440c01f        ld1b    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440c01f        ld1b    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440c800        ld1b    \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c440c800        ld1b    \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c440c800        ld1b    \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c440dc00        ld1b    \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c440dc00        ld1b    \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c440dc00        ld1b    \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c440c060        ld1b    \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c440c060        ld1b    \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c440c060        ld1b    \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c440c3e0        ld1b    \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c440c3e0        ld1b    \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c440c3e0        ld1b    \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c444c000        ld1b    \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c444c000        ld1b    \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c444c000        ld1b    \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c45fc000        ld1b    \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c45fc000        ld1b    \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c45fc000        ld1b    \{z0\.d\}, p0/z, \[x0, z31\.d\]
 .*:    8420c000        ld1b    \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    8420c000        ld1b    \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    8420c000        ld1b    \{z0\.s\}, p0/z, \[z0\.s\]
@@ -12449,14 +12449,14 @@ Disassembly of section .*:
 .*:    8420c3e0        ld1b    \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    8420c3e0        ld1b    \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    8420c3e0        ld1b    \{z0\.s\}, p0/z, \[z31\.s\]
-.*:    842fc000        ld1b    \{z0\.s\}, p0/z, \[z0\.s,#15\]
-.*:    842fc000        ld1b    \{z0\.s\}, p0/z, \[z0\.s,#15\]
-.*:    8430c000        ld1b    \{z0\.s\}, p0/z, \[z0\.s,#16\]
-.*:    8430c000        ld1b    \{z0\.s\}, p0/z, \[z0\.s,#16\]
-.*:    8431c000        ld1b    \{z0\.s\}, p0/z, \[z0\.s,#17\]
-.*:    8431c000        ld1b    \{z0\.s\}, p0/z, \[z0\.s,#17\]
-.*:    843fc000        ld1b    \{z0\.s\}, p0/z, \[z0\.s,#31\]
-.*:    843fc000        ld1b    \{z0\.s\}, p0/z, \[z0\.s,#31\]
+.*:    842fc000        ld1b    \{z0\.s\}, p0/z, \[z0\.s, #15\]
+.*:    842fc000        ld1b    \{z0\.s\}, p0/z, \[z0\.s, #15\]
+.*:    8430c000        ld1b    \{z0\.s\}, p0/z, \[z0\.s, #16\]
+.*:    8430c000        ld1b    \{z0\.s\}, p0/z, \[z0\.s, #16\]
+.*:    8431c000        ld1b    \{z0\.s\}, p0/z, \[z0\.s, #17\]
+.*:    8431c000        ld1b    \{z0\.s\}, p0/z, \[z0\.s, #17\]
+.*:    843fc000        ld1b    \{z0\.s\}, p0/z, \[z0\.s, #31\]
+.*:    843fc000        ld1b    \{z0\.s\}, p0/z, \[z0\.s, #31\]
 .*:    a400a000        ld1b    \{z0\.b\}, p0/z, \[x0\]
 .*:    a400a000        ld1b    \{z0\.b\}, p0/z, \[x0\]
 .*:    a400a000        ld1b    \{z0\.b\}, p0/z, \[x0\]
@@ -12488,14 +12488,14 @@ Disassembly of section .*:
 .*:    a400a3e0        ld1b    \{z0\.b\}, p0/z, \[sp\]
 .*:    a400a3e0        ld1b    \{z0\.b\}, p0/z, \[sp\]
 .*:    a400a3e0        ld1b    \{z0\.b\}, p0/z, \[sp\]
-.*:    a407a000        ld1b    \{z0\.b\}, p0/z, \[x0,#7,mul vl\]
-.*:    a407a000        ld1b    \{z0\.b\}, p0/z, \[x0,#7,mul vl\]
-.*:    a408a000        ld1b    \{z0\.b\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a408a000        ld1b    \{z0\.b\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a409a000        ld1b    \{z0\.b\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a409a000        ld1b    \{z0\.b\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a40fa000        ld1b    \{z0\.b\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a40fa000        ld1b    \{z0\.b\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a407a000        ld1b    \{z0\.b\}, p0/z, \[x0, #7, mul vl\]
+.*:    a407a000        ld1b    \{z0\.b\}, p0/z, \[x0, #7, mul vl\]
+.*:    a408a000        ld1b    \{z0\.b\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a408a000        ld1b    \{z0\.b\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a409a000        ld1b    \{z0\.b\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a409a000        ld1b    \{z0\.b\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a40fa000        ld1b    \{z0\.b\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a40fa000        ld1b    \{z0\.b\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a420a000        ld1b    \{z0\.h\}, p0/z, \[x0\]
 .*:    a420a000        ld1b    \{z0\.h\}, p0/z, \[x0\]
 .*:    a420a000        ld1b    \{z0\.h\}, p0/z, \[x0\]
@@ -12527,14 +12527,14 @@ Disassembly of section .*:
 .*:    a420a3e0        ld1b    \{z0\.h\}, p0/z, \[sp\]
 .*:    a420a3e0        ld1b    \{z0\.h\}, p0/z, \[sp\]
 .*:    a420a3e0        ld1b    \{z0\.h\}, p0/z, \[sp\]
-.*:    a427a000        ld1b    \{z0\.h\}, p0/z, \[x0,#7,mul vl\]
-.*:    a427a000        ld1b    \{z0\.h\}, p0/z, \[x0,#7,mul vl\]
-.*:    a428a000        ld1b    \{z0\.h\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a428a000        ld1b    \{z0\.h\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a429a000        ld1b    \{z0\.h\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a429a000        ld1b    \{z0\.h\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a42fa000        ld1b    \{z0\.h\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a42fa000        ld1b    \{z0\.h\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a427a000        ld1b    \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
+.*:    a427a000        ld1b    \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
+.*:    a428a000        ld1b    \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a428a000        ld1b    \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a429a000        ld1b    \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a429a000        ld1b    \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a42fa000        ld1b    \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a42fa000        ld1b    \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a440a000        ld1b    \{z0\.s\}, p0/z, \[x0\]
 .*:    a440a000        ld1b    \{z0\.s\}, p0/z, \[x0\]
 .*:    a440a000        ld1b    \{z0\.s\}, p0/z, \[x0\]
@@ -12566,14 +12566,14 @@ Disassembly of section .*:
 .*:    a440a3e0        ld1b    \{z0\.s\}, p0/z, \[sp\]
 .*:    a440a3e0        ld1b    \{z0\.s\}, p0/z, \[sp\]
 .*:    a440a3e0        ld1b    \{z0\.s\}, p0/z, \[sp\]
-.*:    a447a000        ld1b    \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a447a000        ld1b    \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a448a000        ld1b    \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a448a000        ld1b    \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a449a000        ld1b    \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a449a000        ld1b    \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a44fa000        ld1b    \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a44fa000        ld1b    \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a447a000        ld1b    \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a447a000        ld1b    \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a448a000        ld1b    \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a448a000        ld1b    \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a449a000        ld1b    \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a449a000        ld1b    \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a44fa000        ld1b    \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a44fa000        ld1b    \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a460a000        ld1b    \{z0\.d\}, p0/z, \[x0\]
 .*:    a460a000        ld1b    \{z0\.d\}, p0/z, \[x0\]
 .*:    a460a000        ld1b    \{z0\.d\}, p0/z, \[x0\]
@@ -12605,14 +12605,14 @@ Disassembly of section .*:
 .*:    a460a3e0        ld1b    \{z0\.d\}, p0/z, \[sp\]
 .*:    a460a3e0        ld1b    \{z0\.d\}, p0/z, \[sp\]
 .*:    a460a3e0        ld1b    \{z0\.d\}, p0/z, \[sp\]
-.*:    a467a000        ld1b    \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a467a000        ld1b    \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a468a000        ld1b    \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a468a000        ld1b    \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a469a000        ld1b    \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a469a000        ld1b    \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a46fa000        ld1b    \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a46fa000        ld1b    \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a467a000        ld1b    \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a467a000        ld1b    \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a468a000        ld1b    \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a468a000        ld1b    \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a469a000        ld1b    \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a469a000        ld1b    \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a46fa000        ld1b    \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a46fa000        ld1b    \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
 .*:    c420c000        ld1b    \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c420c000        ld1b    \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c420c000        ld1b    \{z0\.d\}, p0/z, \[z0\.d\]
@@ -12637,188 +12637,188 @@ Disassembly of section .*:
 .*:    c420c3e0        ld1b    \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c420c3e0        ld1b    \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c420c3e0        ld1b    \{z0\.d\}, p0/z, \[z31\.d\]
-.*:    c42fc000        ld1b    \{z0\.d\}, p0/z, \[z0\.d,#15\]
-.*:    c42fc000        ld1b    \{z0\.d\}, p0/z, \[z0\.d,#15\]
-.*:    c430c000        ld1b    \{z0\.d\}, p0/z, \[z0\.d,#16\]
-.*:    c430c000        ld1b    \{z0\.d\}, p0/z, \[z0\.d,#16\]
-.*:    c431c000        ld1b    \{z0\.d\}, p0/z, \[z0\.d,#17\]
-.*:    c431c000        ld1b    \{z0\.d\}, p0/z, \[z0\.d,#17\]
-.*:    c43fc000        ld1b    \{z0\.d\}, p0/z, \[z0\.d,#31\]
-.*:    c43fc000        ld1b    \{z0\.d\}, p0/z, \[z0\.d,#31\]
-.*:    a5e04000        ld1d    \{z0\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e04000        ld1d    \{z0\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e04000        ld1d    \{z0\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e04001        ld1d    \{z1\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e04001        ld1d    \{z1\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e04001        ld1d    \{z1\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e0401f        ld1d    \{z31\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e0401f        ld1d    \{z31\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e0401f        ld1d    \{z31\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e04800        ld1d    \{z0\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a5e04800        ld1d    \{z0\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a5e05c00        ld1d    \{z0\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a5e05c00        ld1d    \{z0\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a5e04060        ld1d    \{z0\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a5e04060        ld1d    \{z0\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a5e043e0        ld1d    \{z0\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a5e043e0        ld1d    \{z0\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a5e44000        ld1d    \{z0\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a5e44000        ld1d    \{z0\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a5fe4000        ld1d    \{z0\.d\}, p0/z, \[x0,x30,lsl #3\]
-.*:    a5fe4000        ld1d    \{z0\.d\}, p0/z, \[x0,x30,lsl #3\]
-.*:    c5804000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5804000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5804000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5804000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5804001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5804001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5804001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5804001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c580401f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c580401f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c580401f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c580401f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5804800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5804800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5804800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5805c00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5805c00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5805c00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5804060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c5804060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c5804060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c58043e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c58043e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c58043e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c5844000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c5844000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c5844000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c59f4000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c59f4000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c59f4000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c5c04000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c04000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c04000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c04000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c04001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c04001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c04001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c04001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c0401f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c0401f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c0401f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c0401f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c04800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5c04800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5c04800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5c05c00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5c05c00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5c05c00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5c04060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c5c04060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c5c04060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c5c043e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c5c043e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c5c043e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c5c44000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c5c44000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c5c44000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c5df4000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c5df4000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c5df4000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c5a04000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a04000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a04000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a04001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a04001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a04001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a0401f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a0401f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a0401f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a04800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a04800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a05c00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a05c00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a04060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #3\]
-.*:    c5a04060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #3\]
-.*:    c5a043e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #3\]
-.*:    c5a043e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #3\]
-.*:    c5a44000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #3\]
-.*:    c5a44000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #3\]
-.*:    c5bf4000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #3\]
-.*:    c5bf4000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #3\]
-.*:    c5e04000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e04000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e04000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e04001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e04001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e04001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e0401f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e0401f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e0401f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e04800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e04800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e05c00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e05c00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e04060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #3\]
-.*:    c5e04060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #3\]
-.*:    c5e043e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #3\]
-.*:    c5e043e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #3\]
-.*:    c5e44000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #3\]
-.*:    c5e44000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #3\]
-.*:    c5ff4000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #3\]
-.*:    c5ff4000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #3\]
-.*:    c5c0c000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0c000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0c000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0c000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0c001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0c001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0c001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0c001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0c01f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0c01f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0c01f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0c01f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0c800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c5c0c800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c5c0c800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c5c0dc00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c5c0dc00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c5c0dc00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c5c0c060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c5c0c060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c5c0c060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c5c0c3e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c5c0c3e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c5c0c3e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c5c4c000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c5c4c000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c5c4c000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c5dfc000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c5dfc000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c5dfc000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c5e0c000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0c000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0c000        ld1d    \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0c001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0c001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0c001        ld1d    \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0c01f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0c01f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0c01f        ld1d    \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0c800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0c800        ld1d    \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0dc00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0dc00        ld1d    \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0c060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #3\]
-.*:    c5e0c060        ld1d    \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #3\]
-.*:    c5e0c3e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #3\]
-.*:    c5e0c3e0        ld1d    \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #3\]
-.*:    c5e4c000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #3\]
-.*:    c5e4c000        ld1d    \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #3\]
-.*:    c5ffc000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #3\]
-.*:    c5ffc000        ld1d    \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #3\]
+.*:    c42fc000        ld1b    \{z0\.d\}, p0/z, \[z0\.d, #15\]
+.*:    c42fc000        ld1b    \{z0\.d\}, p0/z, \[z0\.d, #15\]
+.*:    c430c000        ld1b    \{z0\.d\}, p0/z, \[z0\.d, #16\]
+.*:    c430c000        ld1b    \{z0\.d\}, p0/z, \[z0\.d, #16\]
+.*:    c431c000        ld1b    \{z0\.d\}, p0/z, \[z0\.d, #17\]
+.*:    c431c000        ld1b    \{z0\.d\}, p0/z, \[z0\.d, #17\]
+.*:    c43fc000        ld1b    \{z0\.d\}, p0/z, \[z0\.d, #31\]
+.*:    c43fc000        ld1b    \{z0\.d\}, p0/z, \[z0\.d, #31\]
+.*:    a5e04000        ld1d    \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e04000        ld1d    \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e04000        ld1d    \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e04001        ld1d    \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e04001        ld1d    \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e04001        ld1d    \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e0401f        ld1d    \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e0401f        ld1d    \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e0401f        ld1d    \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e04800        ld1d    \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a5e04800        ld1d    \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a5e05c00        ld1d    \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a5e05c00        ld1d    \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a5e04060        ld1d    \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a5e04060        ld1d    \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a5e043e0        ld1d    \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a5e043e0        ld1d    \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a5e44000        ld1d    \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a5e44000        ld1d    \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a5fe4000        ld1d    \{z0\.d\}, p0/z, \[x0, x30, lsl #3\]
+.*:    a5fe4000        ld1d    \{z0\.d\}, p0/z, \[x0, x30, lsl #3\]
+.*:    c5804000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5804000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5804000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5804000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5804001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5804001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5804001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5804001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c580401f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c580401f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c580401f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c580401f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5804800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5804800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5804800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5805c00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5805c00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5805c00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5804060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c5804060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c5804060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c58043e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c58043e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c58043e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c5844000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c5844000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c5844000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c59f4000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c59f4000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c59f4000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c5c04000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c04000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c04000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c04000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c04001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c04001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c04001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c04001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c0401f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c0401f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c0401f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c0401f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c04800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5c04800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5c04800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5c05c00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5c05c00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5c05c00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5c04060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c5c04060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c5c04060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c5c043e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c5c043e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c5c043e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c5c44000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c5c44000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c5c44000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c5df4000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c5df4000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c5df4000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c5a04000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a04000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a04000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a04001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a04001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a04001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a0401f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a0401f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a0401f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a04800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a04800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a05c00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a05c00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a04060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #3\]
+.*:    c5a04060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #3\]
+.*:    c5a043e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #3\]
+.*:    c5a043e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #3\]
+.*:    c5a44000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #3\]
+.*:    c5a44000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #3\]
+.*:    c5bf4000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #3\]
+.*:    c5bf4000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #3\]
+.*:    c5e04000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e04000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e04000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e04001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e04001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e04001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e0401f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e0401f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e0401f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e04800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e04800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e05c00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e05c00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e04060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #3\]
+.*:    c5e04060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #3\]
+.*:    c5e043e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #3\]
+.*:    c5e043e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #3\]
+.*:    c5e44000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #3\]
+.*:    c5e44000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #3\]
+.*:    c5ff4000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #3\]
+.*:    c5ff4000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #3\]
+.*:    c5c0c000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0c000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0c000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0c000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0c001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0c001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0c001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0c001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0c01f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0c01f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0c01f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0c01f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0c800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c5c0c800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c5c0c800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c5c0dc00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c5c0dc00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c5c0dc00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c5c0c060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c5c0c060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c5c0c060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c5c0c3e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c5c0c3e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c5c0c3e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c5c4c000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c5c4c000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c5c4c000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c5dfc000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c5dfc000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c5dfc000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c5e0c000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0c000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0c000        ld1d    \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0c001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0c001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0c001        ld1d    \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0c01f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0c01f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0c01f        ld1d    \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0c800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0c800        ld1d    \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0dc00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0dc00        ld1d    \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0c060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #3\]
+.*:    c5e0c060        ld1d    \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #3\]
+.*:    c5e0c3e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #3\]
+.*:    c5e0c3e0        ld1d    \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #3\]
+.*:    c5e4c000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #3\]
+.*:    c5e4c000        ld1d    \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #3\]
+.*:    c5ffc000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #3\]
+.*:    c5ffc000        ld1d    \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #3\]
 .*:    a5e0a000        ld1d    \{z0\.d\}, p0/z, \[x0\]
 .*:    a5e0a000        ld1d    \{z0\.d\}, p0/z, \[x0\]
 .*:    a5e0a000        ld1d    \{z0\.d\}, p0/z, \[x0\]
@@ -12850,14 +12850,14 @@ Disassembly of section .*:
 .*:    a5e0a3e0        ld1d    \{z0\.d\}, p0/z, \[sp\]
 .*:    a5e0a3e0        ld1d    \{z0\.d\}, p0/z, \[sp\]
 .*:    a5e0a3e0        ld1d    \{z0\.d\}, p0/z, \[sp\]
-.*:    a5e7a000        ld1d    \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a5e7a000        ld1d    \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a5e8a000        ld1d    \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a5e8a000        ld1d    \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a5e9a000        ld1d    \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a5e9a000        ld1d    \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a5efa000        ld1d    \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a5efa000        ld1d    \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a5e7a000        ld1d    \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a5e7a000        ld1d    \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a5e8a000        ld1d    \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a5e8a000        ld1d    \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a5e9a000        ld1d    \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a5e9a000        ld1d    \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a5efa000        ld1d    \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a5efa000        ld1d    \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
 .*:    c5a0c000        ld1d    \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c5a0c000        ld1d    \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c5a0c000        ld1d    \{z0\.d\}, p0/z, \[z0\.d\]
@@ -12882,332 +12882,332 @@ Disassembly of section .*:
 .*:    c5a0c3e0        ld1d    \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c5a0c3e0        ld1d    \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c5a0c3e0        ld1d    \{z0\.d\}, p0/z, \[z31\.d\]
-.*:    c5afc000        ld1d    \{z0\.d\}, p0/z, \[z0\.d,#120\]
-.*:    c5afc000        ld1d    \{z0\.d\}, p0/z, \[z0\.d,#120\]
-.*:    c5b0c000        ld1d    \{z0\.d\}, p0/z, \[z0\.d,#128\]
-.*:    c5b0c000        ld1d    \{z0\.d\}, p0/z, \[z0\.d,#128\]
-.*:    c5b1c000        ld1d    \{z0\.d\}, p0/z, \[z0\.d,#136\]
-.*:    c5b1c000        ld1d    \{z0\.d\}, p0/z, \[z0\.d,#136\]
-.*:    c5bfc000        ld1d    \{z0\.d\}, p0/z, \[z0\.d,#248\]
-.*:    c5bfc000        ld1d    \{z0\.d\}, p0/z, \[z0\.d,#248\]
-.*:    84804000        ld1h    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84804000        ld1h    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84804000        ld1h    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84804000        ld1h    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84804001        ld1h    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84804001        ld1h    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84804001        ld1h    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84804001        ld1h    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480401f        ld1h    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480401f        ld1h    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480401f        ld1h    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480401f        ld1h    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84804800        ld1h    \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84804800        ld1h    \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84804800        ld1h    \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84805c00        ld1h    \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84805c00        ld1h    \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84805c00        ld1h    \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84804060        ld1h    \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84804060        ld1h    \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84804060        ld1h    \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    848043e0        ld1h    \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    848043e0        ld1h    \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    848043e0        ld1h    \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    84844000        ld1h    \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84844000        ld1h    \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84844000        ld1h    \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    849f4000        ld1h    \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    849f4000        ld1h    \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    849f4000        ld1h    \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    84c04000        ld1h    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c04000        ld1h    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c04000        ld1h    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c04000        ld1h    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c04001        ld1h    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c04001        ld1h    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c04001        ld1h    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c04001        ld1h    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0401f        ld1h    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0401f        ld1h    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0401f        ld1h    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0401f        ld1h    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c04800        ld1h    \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84c04800        ld1h    \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84c04800        ld1h    \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84c05c00        ld1h    \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84c05c00        ld1h    \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84c05c00        ld1h    \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84c04060        ld1h    \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84c04060        ld1h    \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84c04060        ld1h    \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84c043e0        ld1h    \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84c043e0        ld1h    \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84c043e0        ld1h    \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84c44000        ld1h    \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84c44000        ld1h    \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84c44000        ld1h    \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84df4000        ld1h    \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    84df4000        ld1h    \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    84df4000        ld1h    \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    84a04000        ld1h    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a04000        ld1h    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a04000        ld1h    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a04001        ld1h    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a04001        ld1h    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a04001        ld1h    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a0401f        ld1h    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a0401f        ld1h    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a0401f        ld1h    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a04800        ld1h    \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a04800        ld1h    \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a05c00        ld1h    \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a05c00        ld1h    \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a04060        ld1h    \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\]
-.*:    84a04060        ld1h    \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\]
-.*:    84a043e0        ld1h    \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\]
-.*:    84a043e0        ld1h    \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\]
-.*:    84a44000        ld1h    \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\]
-.*:    84a44000        ld1h    \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\]
-.*:    84bf4000        ld1h    \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\]
-.*:    84bf4000        ld1h    \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\]
-.*:    84e04000        ld1h    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e04000        ld1h    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e04000        ld1h    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e04001        ld1h    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e04001        ld1h    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e04001        ld1h    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e0401f        ld1h    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e0401f        ld1h    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e0401f        ld1h    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e04800        ld1h    \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e04800        ld1h    \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e05c00        ld1h    \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e05c00        ld1h    \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e04060        ld1h    \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\]
-.*:    84e04060        ld1h    \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\]
-.*:    84e043e0        ld1h    \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\]
-.*:    84e043e0        ld1h    \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\]
-.*:    84e44000        ld1h    \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\]
-.*:    84e44000        ld1h    \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\]
-.*:    84ff4000        ld1h    \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\]
-.*:    84ff4000        ld1h    \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\]
-.*:    a4a04000        ld1h    \{z0\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a04000        ld1h    \{z0\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a04000        ld1h    \{z0\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a04001        ld1h    \{z1\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a04001        ld1h    \{z1\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a04001        ld1h    \{z1\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a0401f        ld1h    \{z31\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a0401f        ld1h    \{z31\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a0401f        ld1h    \{z31\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a04800        ld1h    \{z0\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4a04800        ld1h    \{z0\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4a05c00        ld1h    \{z0\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4a05c00        ld1h    \{z0\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4a04060        ld1h    \{z0\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4a04060        ld1h    \{z0\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4a043e0        ld1h    \{z0\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4a043e0        ld1h    \{z0\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4a44000        ld1h    \{z0\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4a44000        ld1h    \{z0\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4be4000        ld1h    \{z0\.h\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a4be4000        ld1h    \{z0\.h\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a4c04000        ld1h    \{z0\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c04000        ld1h    \{z0\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c04000        ld1h    \{z0\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c04001        ld1h    \{z1\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c04001        ld1h    \{z1\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c04001        ld1h    \{z1\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c0401f        ld1h    \{z31\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c0401f        ld1h    \{z31\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c0401f        ld1h    \{z31\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c04800        ld1h    \{z0\.s\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4c04800        ld1h    \{z0\.s\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4c05c00        ld1h    \{z0\.s\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4c05c00        ld1h    \{z0\.s\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4c04060        ld1h    \{z0\.s\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4c04060        ld1h    \{z0\.s\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4c043e0        ld1h    \{z0\.s\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4c043e0        ld1h    \{z0\.s\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4c44000        ld1h    \{z0\.s\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4c44000        ld1h    \{z0\.s\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4de4000        ld1h    \{z0\.s\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a4de4000        ld1h    \{z0\.s\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a4e04000        ld1h    \{z0\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e04000        ld1h    \{z0\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e04000        ld1h    \{z0\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e04001        ld1h    \{z1\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e04001        ld1h    \{z1\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e04001        ld1h    \{z1\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e0401f        ld1h    \{z31\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e0401f        ld1h    \{z31\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e0401f        ld1h    \{z31\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e04800        ld1h    \{z0\.d\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4e04800        ld1h    \{z0\.d\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4e05c00        ld1h    \{z0\.d\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4e05c00        ld1h    \{z0\.d\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4e04060        ld1h    \{z0\.d\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4e04060        ld1h    \{z0\.d\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4e043e0        ld1h    \{z0\.d\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4e043e0        ld1h    \{z0\.d\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4e44000        ld1h    \{z0\.d\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4e44000        ld1h    \{z0\.d\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4fe4000        ld1h    \{z0\.d\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a4fe4000        ld1h    \{z0\.d\}, p0/z, \[x0,x30,lsl #1\]
-.*:    c4804000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4804000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4804000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4804000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4804001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4804001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4804001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4804001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480401f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480401f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480401f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480401f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4804800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4804800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4804800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4805c00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4805c00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4805c00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4804060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4804060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4804060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c48043e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c48043e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c48043e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c4844000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4844000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4844000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c49f4000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c49f4000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c49f4000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c4c04000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c04000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c04000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c04000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c04001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c04001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c04001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c04001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0401f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0401f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0401f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0401f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c04800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4c04800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4c04800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4c05c00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4c05c00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4c05c00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4c04060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4c04060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4c04060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4c043e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4c043e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4c043e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4c44000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4c44000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4c44000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4df4000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c4df4000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c4df4000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c4a04000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a04000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a04000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a04001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a04001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a04001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a0401f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a0401f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a0401f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a04800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a04800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a05c00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a05c00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a04060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\]
-.*:    c4a04060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\]
-.*:    c4a043e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\]
-.*:    c4a043e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\]
-.*:    c4a44000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\]
-.*:    c4a44000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\]
-.*:    c4bf4000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\]
-.*:    c4bf4000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\]
-.*:    c4e04000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e04000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e04000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e04001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e04001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e04001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e0401f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e0401f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e0401f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e04800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e04800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e05c00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e05c00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e04060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\]
-.*:    c4e04060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\]
-.*:    c4e043e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\]
-.*:    c4e043e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\]
-.*:    c4e44000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\]
-.*:    c4e44000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\]
-.*:    c4ff4000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\]
-.*:    c4ff4000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\]
-.*:    c4c0c000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0c000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0c000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0c000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0c001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0c001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0c001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0c001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0c01f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0c01f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0c01f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0c01f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0c800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4c0c800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4c0c800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4c0dc00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4c0dc00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4c0dc00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4c0c060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c4c0c060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c4c0c060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c4c0c3e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c4c0c3e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c4c0c3e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c4c4c000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c4c4c000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c4c4c000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c4dfc000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c4dfc000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c4dfc000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c4e0c000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0c000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0c000        ld1h    \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0c001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0c001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0c001        ld1h    \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0c01f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0c01f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0c01f        ld1h    \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0c800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0c800        ld1h    \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0dc00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0dc00        ld1h    \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0c060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\]
-.*:    c4e0c060        ld1h    \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\]
-.*:    c4e0c3e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\]
-.*:    c4e0c3e0        ld1h    \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\]
-.*:    c4e4c000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\]
-.*:    c4e4c000        ld1h    \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\]
-.*:    c4ffc000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\]
-.*:    c4ffc000        ld1h    \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\]
+.*:    c5afc000        ld1d    \{z0\.d\}, p0/z, \[z0\.d, #120\]
+.*:    c5afc000        ld1d    \{z0\.d\}, p0/z, \[z0\.d, #120\]
+.*:    c5b0c000        ld1d    \{z0\.d\}, p0/z, \[z0\.d, #128\]
+.*:    c5b0c000        ld1d    \{z0\.d\}, p0/z, \[z0\.d, #128\]
+.*:    c5b1c000        ld1d    \{z0\.d\}, p0/z, \[z0\.d, #136\]
+.*:    c5b1c000        ld1d    \{z0\.d\}, p0/z, \[z0\.d, #136\]
+.*:    c5bfc000        ld1d    \{z0\.d\}, p0/z, \[z0\.d, #248\]
+.*:    c5bfc000        ld1d    \{z0\.d\}, p0/z, \[z0\.d, #248\]
+.*:    84804000        ld1h    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84804000        ld1h    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84804000        ld1h    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84804000        ld1h    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84804001        ld1h    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84804001        ld1h    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84804001        ld1h    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84804001        ld1h    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480401f        ld1h    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480401f        ld1h    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480401f        ld1h    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480401f        ld1h    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84804800        ld1h    \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84804800        ld1h    \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84804800        ld1h    \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84805c00        ld1h    \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84805c00        ld1h    \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84805c00        ld1h    \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84804060        ld1h    \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84804060        ld1h    \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84804060        ld1h    \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    848043e0        ld1h    \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    848043e0        ld1h    \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    848043e0        ld1h    \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    84844000        ld1h    \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84844000        ld1h    \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84844000        ld1h    \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    849f4000        ld1h    \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    849f4000        ld1h    \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    849f4000        ld1h    \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    84c04000        ld1h    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c04000        ld1h    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c04000        ld1h    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c04000        ld1h    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c04001        ld1h    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c04001        ld1h    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c04001        ld1h    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c04001        ld1h    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0401f        ld1h    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0401f        ld1h    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0401f        ld1h    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0401f        ld1h    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c04800        ld1h    \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84c04800        ld1h    \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84c04800        ld1h    \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84c05c00        ld1h    \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84c05c00        ld1h    \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84c05c00        ld1h    \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84c04060        ld1h    \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84c04060        ld1h    \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84c04060        ld1h    \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84c043e0        ld1h    \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84c043e0        ld1h    \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84c043e0        ld1h    \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84c44000        ld1h    \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84c44000        ld1h    \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84c44000        ld1h    \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84df4000        ld1h    \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    84df4000        ld1h    \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    84df4000        ld1h    \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    84a04000        ld1h    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a04000        ld1h    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a04000        ld1h    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a04001        ld1h    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a04001        ld1h    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a04001        ld1h    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a0401f        ld1h    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a0401f        ld1h    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a0401f        ld1h    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a04800        ld1h    \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a04800        ld1h    \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a05c00        ld1h    \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a05c00        ld1h    \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a04060        ld1h    \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
+.*:    84a04060        ld1h    \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
+.*:    84a043e0        ld1h    \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
+.*:    84a043e0        ld1h    \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
+.*:    84a44000        ld1h    \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
+.*:    84a44000        ld1h    \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
+.*:    84bf4000        ld1h    \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
+.*:    84bf4000        ld1h    \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
+.*:    84e04000        ld1h    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e04000        ld1h    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e04000        ld1h    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e04001        ld1h    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e04001        ld1h    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e04001        ld1h    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e0401f        ld1h    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e0401f        ld1h    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e0401f        ld1h    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e04800        ld1h    \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e04800        ld1h    \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e05c00        ld1h    \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e05c00        ld1h    \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e04060        ld1h    \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
+.*:    84e04060        ld1h    \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
+.*:    84e043e0        ld1h    \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
+.*:    84e043e0        ld1h    \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
+.*:    84e44000        ld1h    \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
+.*:    84e44000        ld1h    \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
+.*:    84ff4000        ld1h    \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
+.*:    84ff4000        ld1h    \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
+.*:    a4a04000        ld1h    \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a04000        ld1h    \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a04000        ld1h    \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a04001        ld1h    \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a04001        ld1h    \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a04001        ld1h    \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a0401f        ld1h    \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a0401f        ld1h    \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a0401f        ld1h    \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a04800        ld1h    \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4a04800        ld1h    \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4a05c00        ld1h    \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4a05c00        ld1h    \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4a04060        ld1h    \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4a04060        ld1h    \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4a043e0        ld1h    \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4a043e0        ld1h    \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4a44000        ld1h    \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4a44000        ld1h    \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4be4000        ld1h    \{z0\.h\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a4be4000        ld1h    \{z0\.h\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a4c04000        ld1h    \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c04000        ld1h    \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c04000        ld1h    \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c04001        ld1h    \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c04001        ld1h    \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c04001        ld1h    \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c0401f        ld1h    \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c0401f        ld1h    \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c0401f        ld1h    \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c04800        ld1h    \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4c04800        ld1h    \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4c05c00        ld1h    \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4c05c00        ld1h    \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4c04060        ld1h    \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4c04060        ld1h    \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4c043e0        ld1h    \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4c043e0        ld1h    \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4c44000        ld1h    \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4c44000        ld1h    \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4de4000        ld1h    \{z0\.s\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a4de4000        ld1h    \{z0\.s\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a4e04000        ld1h    \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e04000        ld1h    \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e04000        ld1h    \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e04001        ld1h    \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e04001        ld1h    \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e04001        ld1h    \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e0401f        ld1h    \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e0401f        ld1h    \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e0401f        ld1h    \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e04800        ld1h    \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4e04800        ld1h    \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4e05c00        ld1h    \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4e05c00        ld1h    \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4e04060        ld1h    \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4e04060        ld1h    \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4e043e0        ld1h    \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4e043e0        ld1h    \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4e44000        ld1h    \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4e44000        ld1h    \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4fe4000        ld1h    \{z0\.d\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a4fe4000        ld1h    \{z0\.d\}, p0/z, \[x0, x30, lsl #1\]
+.*:    c4804000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4804000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4804000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4804000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4804001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4804001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4804001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4804001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480401f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480401f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480401f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480401f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4804800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4804800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4804800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4805c00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4805c00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4805c00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4804060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4804060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4804060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c48043e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c48043e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c48043e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c4844000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4844000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4844000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c49f4000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c49f4000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c49f4000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c4c04000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c04000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c04000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c04000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c04001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c04001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c04001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c04001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0401f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0401f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0401f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0401f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c04800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4c04800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4c04800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4c05c00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4c05c00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4c05c00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4c04060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4c04060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4c04060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4c043e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4c043e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4c043e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4c44000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4c44000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4c44000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4df4000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c4df4000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c4df4000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c4a04000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a04000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a04000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a04001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a04001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a04001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a0401f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a0401f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a0401f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a04800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a04800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a05c00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a05c00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a04060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
+.*:    c4a04060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
+.*:    c4a043e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
+.*:    c4a043e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
+.*:    c4a44000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
+.*:    c4a44000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
+.*:    c4bf4000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
+.*:    c4bf4000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
+.*:    c4e04000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e04000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e04000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e04001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e04001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e04001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e0401f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e0401f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e0401f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e04800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e04800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e05c00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e05c00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e04060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
+.*:    c4e04060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
+.*:    c4e043e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
+.*:    c4e043e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
+.*:    c4e44000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
+.*:    c4e44000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
+.*:    c4ff4000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
+.*:    c4ff4000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
+.*:    c4c0c000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0c000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0c000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0c000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0c001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0c001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0c001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0c001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0c01f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0c01f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0c01f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0c01f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0c800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4c0c800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4c0c800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4c0dc00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4c0dc00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4c0dc00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4c0c060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c4c0c060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c4c0c060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c4c0c3e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c4c0c3e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c4c0c3e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c4c4c000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c4c4c000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c4c4c000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c4dfc000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c4dfc000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c4dfc000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c4e0c000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0c000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0c000        ld1h    \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0c001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0c001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0c001        ld1h    \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0c01f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0c01f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0c01f        ld1h    \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0c800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0c800        ld1h    \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0dc00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0dc00        ld1h    \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0c060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
+.*:    c4e0c060        ld1h    \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
+.*:    c4e0c3e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
+.*:    c4e0c3e0        ld1h    \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
+.*:    c4e4c000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
+.*:    c4e4c000        ld1h    \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
+.*:    c4ffc000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
+.*:    c4ffc000        ld1h    \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
 .*:    84a0c000        ld1h    \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    84a0c000        ld1h    \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    84a0c000        ld1h    \{z0\.s\}, p0/z, \[z0\.s\]
@@ -13232,14 +13232,14 @@ Disassembly of section .*:
 .*:    84a0c3e0        ld1h    \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    84a0c3e0        ld1h    \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    84a0c3e0        ld1h    \{z0\.s\}, p0/z, \[z31\.s\]
-.*:    84afc000        ld1h    \{z0\.s\}, p0/z, \[z0\.s,#30\]
-.*:    84afc000        ld1h    \{z0\.s\}, p0/z, \[z0\.s,#30\]
-.*:    84b0c000        ld1h    \{z0\.s\}, p0/z, \[z0\.s,#32\]
-.*:    84b0c000        ld1h    \{z0\.s\}, p0/z, \[z0\.s,#32\]
-.*:    84b1c000        ld1h    \{z0\.s\}, p0/z, \[z0\.s,#34\]
-.*:    84b1c000        ld1h    \{z0\.s\}, p0/z, \[z0\.s,#34\]
-.*:    84bfc000        ld1h    \{z0\.s\}, p0/z, \[z0\.s,#62\]
-.*:    84bfc000        ld1h    \{z0\.s\}, p0/z, \[z0\.s,#62\]
+.*:    84afc000        ld1h    \{z0\.s\}, p0/z, \[z0\.s, #30\]
+.*:    84afc000        ld1h    \{z0\.s\}, p0/z, \[z0\.s, #30\]
+.*:    84b0c000        ld1h    \{z0\.s\}, p0/z, \[z0\.s, #32\]
+.*:    84b0c000        ld1h    \{z0\.s\}, p0/z, \[z0\.s, #32\]
+.*:    84b1c000        ld1h    \{z0\.s\}, p0/z, \[z0\.s, #34\]
+.*:    84b1c000        ld1h    \{z0\.s\}, p0/z, \[z0\.s, #34\]
+.*:    84bfc000        ld1h    \{z0\.s\}, p0/z, \[z0\.s, #62\]
+.*:    84bfc000        ld1h    \{z0\.s\}, p0/z, \[z0\.s, #62\]
 .*:    a4a0a000        ld1h    \{z0\.h\}, p0/z, \[x0\]
 .*:    a4a0a000        ld1h    \{z0\.h\}, p0/z, \[x0\]
 .*:    a4a0a000        ld1h    \{z0\.h\}, p0/z, \[x0\]
@@ -13271,14 +13271,14 @@ Disassembly of section .*:
 .*:    a4a0a3e0        ld1h    \{z0\.h\}, p0/z, \[sp\]
 .*:    a4a0a3e0        ld1h    \{z0\.h\}, p0/z, \[sp\]
 .*:    a4a0a3e0        ld1h    \{z0\.h\}, p0/z, \[sp\]
-.*:    a4a7a000        ld1h    \{z0\.h\}, p0/z, \[x0,#7,mul vl\]
-.*:    a4a7a000        ld1h    \{z0\.h\}, p0/z, \[x0,#7,mul vl\]
-.*:    a4a8a000        ld1h    \{z0\.h\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a4a8a000        ld1h    \{z0\.h\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a4a9a000        ld1h    \{z0\.h\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a4a9a000        ld1h    \{z0\.h\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a4afa000        ld1h    \{z0\.h\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a4afa000        ld1h    \{z0\.h\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a4a7a000        ld1h    \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
+.*:    a4a7a000        ld1h    \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
+.*:    a4a8a000        ld1h    \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a4a8a000        ld1h    \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a4a9a000        ld1h    \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a4a9a000        ld1h    \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a4afa000        ld1h    \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a4afa000        ld1h    \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a4c0a000        ld1h    \{z0\.s\}, p0/z, \[x0\]
 .*:    a4c0a000        ld1h    \{z0\.s\}, p0/z, \[x0\]
 .*:    a4c0a000        ld1h    \{z0\.s\}, p0/z, \[x0\]
@@ -13310,14 +13310,14 @@ Disassembly of section .*:
 .*:    a4c0a3e0        ld1h    \{z0\.s\}, p0/z, \[sp\]
 .*:    a4c0a3e0        ld1h    \{z0\.s\}, p0/z, \[sp\]
 .*:    a4c0a3e0        ld1h    \{z0\.s\}, p0/z, \[sp\]
-.*:    a4c7a000        ld1h    \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a4c7a000        ld1h    \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a4c8a000        ld1h    \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a4c8a000        ld1h    \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a4c9a000        ld1h    \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a4c9a000        ld1h    \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a4cfa000        ld1h    \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a4cfa000        ld1h    \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a4c7a000        ld1h    \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a4c7a000        ld1h    \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a4c8a000        ld1h    \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a4c8a000        ld1h    \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a4c9a000        ld1h    \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a4c9a000        ld1h    \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a4cfa000        ld1h    \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a4cfa000        ld1h    \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a4e0a000        ld1h    \{z0\.d\}, p0/z, \[x0\]
 .*:    a4e0a000        ld1h    \{z0\.d\}, p0/z, \[x0\]
 .*:    a4e0a000        ld1h    \{z0\.d\}, p0/z, \[x0\]
@@ -13349,14 +13349,14 @@ Disassembly of section .*:
 .*:    a4e0a3e0        ld1h    \{z0\.d\}, p0/z, \[sp\]
 .*:    a4e0a3e0        ld1h    \{z0\.d\}, p0/z, \[sp\]
 .*:    a4e0a3e0        ld1h    \{z0\.d\}, p0/z, \[sp\]
-.*:    a4e7a000        ld1h    \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a4e7a000        ld1h    \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a4e8a000        ld1h    \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a4e8a000        ld1h    \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a4e9a000        ld1h    \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a4e9a000        ld1h    \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a4efa000        ld1h    \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a4efa000        ld1h    \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a4e7a000        ld1h    \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a4e7a000        ld1h    \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a4e8a000        ld1h    \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a4e8a000        ld1h    \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a4e9a000        ld1h    \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a4e9a000        ld1h    \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a4efa000        ld1h    \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a4efa000        ld1h    \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
 .*:    c4a0c000        ld1h    \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c4a0c000        ld1h    \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c4a0c000        ld1h    \{z0\.d\}, p0/z, \[z0\.d\]
@@ -13381,14 +13381,14 @@ Disassembly of section .*:
 .*:    c4a0c3e0        ld1h    \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c4a0c3e0        ld1h    \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c4a0c3e0        ld1h    \{z0\.d\}, p0/z, \[z31\.d\]
-.*:    c4afc000        ld1h    \{z0\.d\}, p0/z, \[z0\.d,#30\]
-.*:    c4afc000        ld1h    \{z0\.d\}, p0/z, \[z0\.d,#30\]
-.*:    c4b0c000        ld1h    \{z0\.d\}, p0/z, \[z0\.d,#32\]
-.*:    c4b0c000        ld1h    \{z0\.d\}, p0/z, \[z0\.d,#32\]
-.*:    c4b1c000        ld1h    \{z0\.d\}, p0/z, \[z0\.d,#34\]
-.*:    c4b1c000        ld1h    \{z0\.d\}, p0/z, \[z0\.d,#34\]
-.*:    c4bfc000        ld1h    \{z0\.d\}, p0/z, \[z0\.d,#62\]
-.*:    c4bfc000        ld1h    \{z0\.d\}, p0/z, \[z0\.d,#62\]
+.*:    c4afc000        ld1h    \{z0\.d\}, p0/z, \[z0\.d, #30\]
+.*:    c4afc000        ld1h    \{z0\.d\}, p0/z, \[z0\.d, #30\]
+.*:    c4b0c000        ld1h    \{z0\.d\}, p0/z, \[z0\.d, #32\]
+.*:    c4b0c000        ld1h    \{z0\.d\}, p0/z, \[z0\.d, #32\]
+.*:    c4b1c000        ld1h    \{z0\.d\}, p0/z, \[z0\.d, #34\]
+.*:    c4b1c000        ld1h    \{z0\.d\}, p0/z, \[z0\.d, #34\]
+.*:    c4bfc000        ld1h    \{z0\.d\}, p0/z, \[z0\.d, #62\]
+.*:    c4bfc000        ld1h    \{z0\.d\}, p0/z, \[z0\.d, #62\]
 .*:    84408000        ld1rb   \{z0\.b\}, p0/z, \[x0\]
 .*:    84408000        ld1rb   \{z0\.b\}, p0/z, \[x0\]
 .*:    84408000        ld1rb   \{z0\.b\}, p0/z, \[x0\]
@@ -13413,14 +13413,14 @@ Disassembly of section .*:
 .*:    844083e0        ld1rb   \{z0\.b\}, p0/z, \[sp\]
 .*:    844083e0        ld1rb   \{z0\.b\}, p0/z, \[sp\]
 .*:    844083e0        ld1rb   \{z0\.b\}, p0/z, \[sp\]
-.*:    845f8000        ld1rb   \{z0\.b\}, p0/z, \[x0,#31\]
-.*:    845f8000        ld1rb   \{z0\.b\}, p0/z, \[x0,#31\]
-.*:    84608000        ld1rb   \{z0\.b\}, p0/z, \[x0,#32\]
-.*:    84608000        ld1rb   \{z0\.b\}, p0/z, \[x0,#32\]
-.*:    84618000        ld1rb   \{z0\.b\}, p0/z, \[x0,#33\]
-.*:    84618000        ld1rb   \{z0\.b\}, p0/z, \[x0,#33\]
-.*:    847f8000        ld1rb   \{z0\.b\}, p0/z, \[x0,#63\]
-.*:    847f8000        ld1rb   \{z0\.b\}, p0/z, \[x0,#63\]
+.*:    845f8000        ld1rb   \{z0\.b\}, p0/z, \[x0, #31\]
+.*:    845f8000        ld1rb   \{z0\.b\}, p0/z, \[x0, #31\]
+.*:    84608000        ld1rb   \{z0\.b\}, p0/z, \[x0, #32\]
+.*:    84608000        ld1rb   \{z0\.b\}, p0/z, \[x0, #32\]
+.*:    84618000        ld1rb   \{z0\.b\}, p0/z, \[x0, #33\]
+.*:    84618000        ld1rb   \{z0\.b\}, p0/z, \[x0, #33\]
+.*:    847f8000        ld1rb   \{z0\.b\}, p0/z, \[x0, #63\]
+.*:    847f8000        ld1rb   \{z0\.b\}, p0/z, \[x0, #63\]
 .*:    8440a000        ld1rb   \{z0\.h\}, p0/z, \[x0\]
 .*:    8440a000        ld1rb   \{z0\.h\}, p0/z, \[x0\]
 .*:    8440a000        ld1rb   \{z0\.h\}, p0/z, \[x0\]
@@ -13445,14 +13445,14 @@ Disassembly of section .*:
 .*:    8440a3e0        ld1rb   \{z0\.h\}, p0/z, \[sp\]
 .*:    8440a3e0        ld1rb   \{z0\.h\}, p0/z, \[sp\]
 .*:    8440a3e0        ld1rb   \{z0\.h\}, p0/z, \[sp\]
-.*:    845fa000        ld1rb   \{z0\.h\}, p0/z, \[x0,#31\]
-.*:    845fa000        ld1rb   \{z0\.h\}, p0/z, \[x0,#31\]
-.*:    8460a000        ld1rb   \{z0\.h\}, p0/z, \[x0,#32\]
-.*:    8460a000        ld1rb   \{z0\.h\}, p0/z, \[x0,#32\]
-.*:    8461a000        ld1rb   \{z0\.h\}, p0/z, \[x0,#33\]
-.*:    8461a000        ld1rb   \{z0\.h\}, p0/z, \[x0,#33\]
-.*:    847fa000        ld1rb   \{z0\.h\}, p0/z, \[x0,#63\]
-.*:    847fa000        ld1rb   \{z0\.h\}, p0/z, \[x0,#63\]
+.*:    845fa000        ld1rb   \{z0\.h\}, p0/z, \[x0, #31\]
+.*:    845fa000        ld1rb   \{z0\.h\}, p0/z, \[x0, #31\]
+.*:    8460a000        ld1rb   \{z0\.h\}, p0/z, \[x0, #32\]
+.*:    8460a000        ld1rb   \{z0\.h\}, p0/z, \[x0, #32\]
+.*:    8461a000        ld1rb   \{z0\.h\}, p0/z, \[x0, #33\]
+.*:    8461a000        ld1rb   \{z0\.h\}, p0/z, \[x0, #33\]
+.*:    847fa000        ld1rb   \{z0\.h\}, p0/z, \[x0, #63\]
+.*:    847fa000        ld1rb   \{z0\.h\}, p0/z, \[x0, #63\]
 .*:    8440c000        ld1rb   \{z0\.s\}, p0/z, \[x0\]
 .*:    8440c000        ld1rb   \{z0\.s\}, p0/z, \[x0\]
 .*:    8440c000        ld1rb   \{z0\.s\}, p0/z, \[x0\]
@@ -13477,14 +13477,14 @@ Disassembly of section .*:
 .*:    8440c3e0        ld1rb   \{z0\.s\}, p0/z, \[sp\]
 .*:    8440c3e0        ld1rb   \{z0\.s\}, p0/z, \[sp\]
 .*:    8440c3e0        ld1rb   \{z0\.s\}, p0/z, \[sp\]
-.*:    845fc000        ld1rb   \{z0\.s\}, p0/z, \[x0,#31\]
-.*:    845fc000        ld1rb   \{z0\.s\}, p0/z, \[x0,#31\]
-.*:    8460c000        ld1rb   \{z0\.s\}, p0/z, \[x0,#32\]
-.*:    8460c000        ld1rb   \{z0\.s\}, p0/z, \[x0,#32\]
-.*:    8461c000        ld1rb   \{z0\.s\}, p0/z, \[x0,#33\]
-.*:    8461c000        ld1rb   \{z0\.s\}, p0/z, \[x0,#33\]
-.*:    847fc000        ld1rb   \{z0\.s\}, p0/z, \[x0,#63\]
-.*:    847fc000        ld1rb   \{z0\.s\}, p0/z, \[x0,#63\]
+.*:    845fc000        ld1rb   \{z0\.s\}, p0/z, \[x0, #31\]
+.*:    845fc000        ld1rb   \{z0\.s\}, p0/z, \[x0, #31\]
+.*:    8460c000        ld1rb   \{z0\.s\}, p0/z, \[x0, #32\]
+.*:    8460c000        ld1rb   \{z0\.s\}, p0/z, \[x0, #32\]
+.*:    8461c000        ld1rb   \{z0\.s\}, p0/z, \[x0, #33\]
+.*:    8461c000        ld1rb   \{z0\.s\}, p0/z, \[x0, #33\]
+.*:    847fc000        ld1rb   \{z0\.s\}, p0/z, \[x0, #63\]
+.*:    847fc000        ld1rb   \{z0\.s\}, p0/z, \[x0, #63\]
 .*:    8440e000        ld1rb   \{z0\.d\}, p0/z, \[x0\]
 .*:    8440e000        ld1rb   \{z0\.d\}, p0/z, \[x0\]
 .*:    8440e000        ld1rb   \{z0\.d\}, p0/z, \[x0\]
@@ -13509,14 +13509,14 @@ Disassembly of section .*:
 .*:    8440e3e0        ld1rb   \{z0\.d\}, p0/z, \[sp\]
 .*:    8440e3e0        ld1rb   \{z0\.d\}, p0/z, \[sp\]
 .*:    8440e3e0        ld1rb   \{z0\.d\}, p0/z, \[sp\]
-.*:    845fe000        ld1rb   \{z0\.d\}, p0/z, \[x0,#31\]
-.*:    845fe000        ld1rb   \{z0\.d\}, p0/z, \[x0,#31\]
-.*:    8460e000        ld1rb   \{z0\.d\}, p0/z, \[x0,#32\]
-.*:    8460e000        ld1rb   \{z0\.d\}, p0/z, \[x0,#32\]
-.*:    8461e000        ld1rb   \{z0\.d\}, p0/z, \[x0,#33\]
-.*:    8461e000        ld1rb   \{z0\.d\}, p0/z, \[x0,#33\]
-.*:    847fe000        ld1rb   \{z0\.d\}, p0/z, \[x0,#63\]
-.*:    847fe000        ld1rb   \{z0\.d\}, p0/z, \[x0,#63\]
+.*:    845fe000        ld1rb   \{z0\.d\}, p0/z, \[x0, #31\]
+.*:    845fe000        ld1rb   \{z0\.d\}, p0/z, \[x0, #31\]
+.*:    8460e000        ld1rb   \{z0\.d\}, p0/z, \[x0, #32\]
+.*:    8460e000        ld1rb   \{z0\.d\}, p0/z, \[x0, #32\]
+.*:    8461e000        ld1rb   \{z0\.d\}, p0/z, \[x0, #33\]
+.*:    8461e000        ld1rb   \{z0\.d\}, p0/z, \[x0, #33\]
+.*:    847fe000        ld1rb   \{z0\.d\}, p0/z, \[x0, #63\]
+.*:    847fe000        ld1rb   \{z0\.d\}, p0/z, \[x0, #63\]
 .*:    85c0e000        ld1rd   \{z0\.d\}, p0/z, \[x0\]
 .*:    85c0e000        ld1rd   \{z0\.d\}, p0/z, \[x0\]
 .*:    85c0e000        ld1rd   \{z0\.d\}, p0/z, \[x0\]
@@ -13541,14 +13541,14 @@ Disassembly of section .*:
 .*:    85c0e3e0        ld1rd   \{z0\.d\}, p0/z, \[sp\]
 .*:    85c0e3e0        ld1rd   \{z0\.d\}, p0/z, \[sp\]
 .*:    85c0e3e0        ld1rd   \{z0\.d\}, p0/z, \[sp\]
-.*:    85dfe000        ld1rd   \{z0\.d\}, p0/z, \[x0,#248\]
-.*:    85dfe000        ld1rd   \{z0\.d\}, p0/z, \[x0,#248\]
-.*:    85e0e000        ld1rd   \{z0\.d\}, p0/z, \[x0,#256\]
-.*:    85e0e000        ld1rd   \{z0\.d\}, p0/z, \[x0,#256\]
-.*:    85e1e000        ld1rd   \{z0\.d\}, p0/z, \[x0,#264\]
-.*:    85e1e000        ld1rd   \{z0\.d\}, p0/z, \[x0,#264\]
-.*:    85ffe000        ld1rd   \{z0\.d\}, p0/z, \[x0,#504\]
-.*:    85ffe000        ld1rd   \{z0\.d\}, p0/z, \[x0,#504\]
+.*:    85dfe000        ld1rd   \{z0\.d\}, p0/z, \[x0, #248\]
+.*:    85dfe000        ld1rd   \{z0\.d\}, p0/z, \[x0, #248\]
+.*:    85e0e000        ld1rd   \{z0\.d\}, p0/z, \[x0, #256\]
+.*:    85e0e000        ld1rd   \{z0\.d\}, p0/z, \[x0, #256\]
+.*:    85e1e000        ld1rd   \{z0\.d\}, p0/z, \[x0, #264\]
+.*:    85e1e000        ld1rd   \{z0\.d\}, p0/z, \[x0, #264\]
+.*:    85ffe000        ld1rd   \{z0\.d\}, p0/z, \[x0, #504\]
+.*:    85ffe000        ld1rd   \{z0\.d\}, p0/z, \[x0, #504\]
 .*:    84c0a000        ld1rh   \{z0\.h\}, p0/z, \[x0\]
 .*:    84c0a000        ld1rh   \{z0\.h\}, p0/z, \[x0\]
 .*:    84c0a000        ld1rh   \{z0\.h\}, p0/z, \[x0\]
@@ -13573,14 +13573,14 @@ Disassembly of section .*:
 .*:    84c0a3e0        ld1rh   \{z0\.h\}, p0/z, \[sp\]
 .*:    84c0a3e0        ld1rh   \{z0\.h\}, p0/z, \[sp\]
 .*:    84c0a3e0        ld1rh   \{z0\.h\}, p0/z, \[sp\]
-.*:    84dfa000        ld1rh   \{z0\.h\}, p0/z, \[x0,#62\]
-.*:    84dfa000        ld1rh   \{z0\.h\}, p0/z, \[x0,#62\]
-.*:    84e0a000        ld1rh   \{z0\.h\}, p0/z, \[x0,#64\]
-.*:    84e0a000        ld1rh   \{z0\.h\}, p0/z, \[x0,#64\]
-.*:    84e1a000        ld1rh   \{z0\.h\}, p0/z, \[x0,#66\]
-.*:    84e1a000        ld1rh   \{z0\.h\}, p0/z, \[x0,#66\]
-.*:    84ffa000        ld1rh   \{z0\.h\}, p0/z, \[x0,#126\]
-.*:    84ffa000        ld1rh   \{z0\.h\}, p0/z, \[x0,#126\]
+.*:    84dfa000        ld1rh   \{z0\.h\}, p0/z, \[x0, #62\]
+.*:    84dfa000        ld1rh   \{z0\.h\}, p0/z, \[x0, #62\]
+.*:    84e0a000        ld1rh   \{z0\.h\}, p0/z, \[x0, #64\]
+.*:    84e0a000        ld1rh   \{z0\.h\}, p0/z, \[x0, #64\]
+.*:    84e1a000        ld1rh   \{z0\.h\}, p0/z, \[x0, #66\]
+.*:    84e1a000        ld1rh   \{z0\.h\}, p0/z, \[x0, #66\]
+.*:    84ffa000        ld1rh   \{z0\.h\}, p0/z, \[x0, #126\]
+.*:    84ffa000        ld1rh   \{z0\.h\}, p0/z, \[x0, #126\]
 .*:    84c0c000        ld1rh   \{z0\.s\}, p0/z, \[x0\]
 .*:    84c0c000        ld1rh   \{z0\.s\}, p0/z, \[x0\]
 .*:    84c0c000        ld1rh   \{z0\.s\}, p0/z, \[x0\]
@@ -13605,14 +13605,14 @@ Disassembly of section .*:
 .*:    84c0c3e0        ld1rh   \{z0\.s\}, p0/z, \[sp\]
 .*:    84c0c3e0        ld1rh   \{z0\.s\}, p0/z, \[sp\]
 .*:    84c0c3e0        ld1rh   \{z0\.s\}, p0/z, \[sp\]
-.*:    84dfc000        ld1rh   \{z0\.s\}, p0/z, \[x0,#62\]
-.*:    84dfc000        ld1rh   \{z0\.s\}, p0/z, \[x0,#62\]
-.*:    84e0c000        ld1rh   \{z0\.s\}, p0/z, \[x0,#64\]
-.*:    84e0c000        ld1rh   \{z0\.s\}, p0/z, \[x0,#64\]
-.*:    84e1c000        ld1rh   \{z0\.s\}, p0/z, \[x0,#66\]
-.*:    84e1c000        ld1rh   \{z0\.s\}, p0/z, \[x0,#66\]
-.*:    84ffc000        ld1rh   \{z0\.s\}, p0/z, \[x0,#126\]
-.*:    84ffc000        ld1rh   \{z0\.s\}, p0/z, \[x0,#126\]
+.*:    84dfc000        ld1rh   \{z0\.s\}, p0/z, \[x0, #62\]
+.*:    84dfc000        ld1rh   \{z0\.s\}, p0/z, \[x0, #62\]
+.*:    84e0c000        ld1rh   \{z0\.s\}, p0/z, \[x0, #64\]
+.*:    84e0c000        ld1rh   \{z0\.s\}, p0/z, \[x0, #64\]
+.*:    84e1c000        ld1rh   \{z0\.s\}, p0/z, \[x0, #66\]
+.*:    84e1c000        ld1rh   \{z0\.s\}, p0/z, \[x0, #66\]
+.*:    84ffc000        ld1rh   \{z0\.s\}, p0/z, \[x0, #126\]
+.*:    84ffc000        ld1rh   \{z0\.s\}, p0/z, \[x0, #126\]
 .*:    84c0e000        ld1rh   \{z0\.d\}, p0/z, \[x0\]
 .*:    84c0e000        ld1rh   \{z0\.d\}, p0/z, \[x0\]
 .*:    84c0e000        ld1rh   \{z0\.d\}, p0/z, \[x0\]
@@ -13637,14 +13637,14 @@ Disassembly of section .*:
 .*:    84c0e3e0        ld1rh   \{z0\.d\}, p0/z, \[sp\]
 .*:    84c0e3e0        ld1rh   \{z0\.d\}, p0/z, \[sp\]
 .*:    84c0e3e0        ld1rh   \{z0\.d\}, p0/z, \[sp\]
-.*:    84dfe000        ld1rh   \{z0\.d\}, p0/z, \[x0,#62\]
-.*:    84dfe000        ld1rh   \{z0\.d\}, p0/z, \[x0,#62\]
-.*:    84e0e000        ld1rh   \{z0\.d\}, p0/z, \[x0,#64\]
-.*:    84e0e000        ld1rh   \{z0\.d\}, p0/z, \[x0,#64\]
-.*:    84e1e000        ld1rh   \{z0\.d\}, p0/z, \[x0,#66\]
-.*:    84e1e000        ld1rh   \{z0\.d\}, p0/z, \[x0,#66\]
-.*:    84ffe000        ld1rh   \{z0\.d\}, p0/z, \[x0,#126\]
-.*:    84ffe000        ld1rh   \{z0\.d\}, p0/z, \[x0,#126\]
+.*:    84dfe000        ld1rh   \{z0\.d\}, p0/z, \[x0, #62\]
+.*:    84dfe000        ld1rh   \{z0\.d\}, p0/z, \[x0, #62\]
+.*:    84e0e000        ld1rh   \{z0\.d\}, p0/z, \[x0, #64\]
+.*:    84e0e000        ld1rh   \{z0\.d\}, p0/z, \[x0, #64\]
+.*:    84e1e000        ld1rh   \{z0\.d\}, p0/z, \[x0, #66\]
+.*:    84e1e000        ld1rh   \{z0\.d\}, p0/z, \[x0, #66\]
+.*:    84ffe000        ld1rh   \{z0\.d\}, p0/z, \[x0, #126\]
+.*:    84ffe000        ld1rh   \{z0\.d\}, p0/z, \[x0, #126\]
 .*:    85c08000        ld1rsb  \{z0\.d\}, p0/z, \[x0\]
 .*:    85c08000        ld1rsb  \{z0\.d\}, p0/z, \[x0\]
 .*:    85c08000        ld1rsb  \{z0\.d\}, p0/z, \[x0\]
@@ -13669,14 +13669,14 @@ Disassembly of section .*:
 .*:    85c083e0        ld1rsb  \{z0\.d\}, p0/z, \[sp\]
 .*:    85c083e0        ld1rsb  \{z0\.d\}, p0/z, \[sp\]
 .*:    85c083e0        ld1rsb  \{z0\.d\}, p0/z, \[sp\]
-.*:    85df8000        ld1rsb  \{z0\.d\}, p0/z, \[x0,#31\]
-.*:    85df8000        ld1rsb  \{z0\.d\}, p0/z, \[x0,#31\]
-.*:    85e08000        ld1rsb  \{z0\.d\}, p0/z, \[x0,#32\]
-.*:    85e08000        ld1rsb  \{z0\.d\}, p0/z, \[x0,#32\]
-.*:    85e18000        ld1rsb  \{z0\.d\}, p0/z, \[x0,#33\]
-.*:    85e18000        ld1rsb  \{z0\.d\}, p0/z, \[x0,#33\]
-.*:    85ff8000        ld1rsb  \{z0\.d\}, p0/z, \[x0,#63\]
-.*:    85ff8000        ld1rsb  \{z0\.d\}, p0/z, \[x0,#63\]
+.*:    85df8000        ld1rsb  \{z0\.d\}, p0/z, \[x0, #31\]
+.*:    85df8000        ld1rsb  \{z0\.d\}, p0/z, \[x0, #31\]
+.*:    85e08000        ld1rsb  \{z0\.d\}, p0/z, \[x0, #32\]
+.*:    85e08000        ld1rsb  \{z0\.d\}, p0/z, \[x0, #32\]
+.*:    85e18000        ld1rsb  \{z0\.d\}, p0/z, \[x0, #33\]
+.*:    85e18000        ld1rsb  \{z0\.d\}, p0/z, \[x0, #33\]
+.*:    85ff8000        ld1rsb  \{z0\.d\}, p0/z, \[x0, #63\]
+.*:    85ff8000        ld1rsb  \{z0\.d\}, p0/z, \[x0, #63\]
 .*:    85c0a000        ld1rsb  \{z0\.s\}, p0/z, \[x0\]
 .*:    85c0a000        ld1rsb  \{z0\.s\}, p0/z, \[x0\]
 .*:    85c0a000        ld1rsb  \{z0\.s\}, p0/z, \[x0\]
@@ -13701,14 +13701,14 @@ Disassembly of section .*:
 .*:    85c0a3e0        ld1rsb  \{z0\.s\}, p0/z, \[sp\]
 .*:    85c0a3e0        ld1rsb  \{z0\.s\}, p0/z, \[sp\]
 .*:    85c0a3e0        ld1rsb  \{z0\.s\}, p0/z, \[sp\]
-.*:    85dfa000        ld1rsb  \{z0\.s\}, p0/z, \[x0,#31\]
-.*:    85dfa000        ld1rsb  \{z0\.s\}, p0/z, \[x0,#31\]
-.*:    85e0a000        ld1rsb  \{z0\.s\}, p0/z, \[x0,#32\]
-.*:    85e0a000        ld1rsb  \{z0\.s\}, p0/z, \[x0,#32\]
-.*:    85e1a000        ld1rsb  \{z0\.s\}, p0/z, \[x0,#33\]
-.*:    85e1a000        ld1rsb  \{z0\.s\}, p0/z, \[x0,#33\]
-.*:    85ffa000        ld1rsb  \{z0\.s\}, p0/z, \[x0,#63\]
-.*:    85ffa000        ld1rsb  \{z0\.s\}, p0/z, \[x0,#63\]
+.*:    85dfa000        ld1rsb  \{z0\.s\}, p0/z, \[x0, #31\]
+.*:    85dfa000        ld1rsb  \{z0\.s\}, p0/z, \[x0, #31\]
+.*:    85e0a000        ld1rsb  \{z0\.s\}, p0/z, \[x0, #32\]
+.*:    85e0a000        ld1rsb  \{z0\.s\}, p0/z, \[x0, #32\]
+.*:    85e1a000        ld1rsb  \{z0\.s\}, p0/z, \[x0, #33\]
+.*:    85e1a000        ld1rsb  \{z0\.s\}, p0/z, \[x0, #33\]
+.*:    85ffa000        ld1rsb  \{z0\.s\}, p0/z, \[x0, #63\]
+.*:    85ffa000        ld1rsb  \{z0\.s\}, p0/z, \[x0, #63\]
 .*:    85c0c000        ld1rsb  \{z0\.h\}, p0/z, \[x0\]
 .*:    85c0c000        ld1rsb  \{z0\.h\}, p0/z, \[x0\]
 .*:    85c0c000        ld1rsb  \{z0\.h\}, p0/z, \[x0\]
@@ -13733,14 +13733,14 @@ Disassembly of section .*:
 .*:    85c0c3e0        ld1rsb  \{z0\.h\}, p0/z, \[sp\]
 .*:    85c0c3e0        ld1rsb  \{z0\.h\}, p0/z, \[sp\]
 .*:    85c0c3e0        ld1rsb  \{z0\.h\}, p0/z, \[sp\]
-.*:    85dfc000        ld1rsb  \{z0\.h\}, p0/z, \[x0,#31\]
-.*:    85dfc000        ld1rsb  \{z0\.h\}, p0/z, \[x0,#31\]
-.*:    85e0c000        ld1rsb  \{z0\.h\}, p0/z, \[x0,#32\]
-.*:    85e0c000        ld1rsb  \{z0\.h\}, p0/z, \[x0,#32\]
-.*:    85e1c000        ld1rsb  \{z0\.h\}, p0/z, \[x0,#33\]
-.*:    85e1c000        ld1rsb  \{z0\.h\}, p0/z, \[x0,#33\]
-.*:    85ffc000        ld1rsb  \{z0\.h\}, p0/z, \[x0,#63\]
-.*:    85ffc000        ld1rsb  \{z0\.h\}, p0/z, \[x0,#63\]
+.*:    85dfc000        ld1rsb  \{z0\.h\}, p0/z, \[x0, #31\]
+.*:    85dfc000        ld1rsb  \{z0\.h\}, p0/z, \[x0, #31\]
+.*:    85e0c000        ld1rsb  \{z0\.h\}, p0/z, \[x0, #32\]
+.*:    85e0c000        ld1rsb  \{z0\.h\}, p0/z, \[x0, #32\]
+.*:    85e1c000        ld1rsb  \{z0\.h\}, p0/z, \[x0, #33\]
+.*:    85e1c000        ld1rsb  \{z0\.h\}, p0/z, \[x0, #33\]
+.*:    85ffc000        ld1rsb  \{z0\.h\}, p0/z, \[x0, #63\]
+.*:    85ffc000        ld1rsb  \{z0\.h\}, p0/z, \[x0, #63\]
 .*:    85408000        ld1rsh  \{z0\.d\}, p0/z, \[x0\]
 .*:    85408000        ld1rsh  \{z0\.d\}, p0/z, \[x0\]
 .*:    85408000        ld1rsh  \{z0\.d\}, p0/z, \[x0\]
@@ -13765,14 +13765,14 @@ Disassembly of section .*:
 .*:    854083e0        ld1rsh  \{z0\.d\}, p0/z, \[sp\]
 .*:    854083e0        ld1rsh  \{z0\.d\}, p0/z, \[sp\]
 .*:    854083e0        ld1rsh  \{z0\.d\}, p0/z, \[sp\]
-.*:    855f8000        ld1rsh  \{z0\.d\}, p0/z, \[x0,#62\]
-.*:    855f8000        ld1rsh  \{z0\.d\}, p0/z, \[x0,#62\]
-.*:    85608000        ld1rsh  \{z0\.d\}, p0/z, \[x0,#64\]
-.*:    85608000        ld1rsh  \{z0\.d\}, p0/z, \[x0,#64\]
-.*:    85618000        ld1rsh  \{z0\.d\}, p0/z, \[x0,#66\]
-.*:    85618000        ld1rsh  \{z0\.d\}, p0/z, \[x0,#66\]
-.*:    857f8000        ld1rsh  \{z0\.d\}, p0/z, \[x0,#126\]
-.*:    857f8000        ld1rsh  \{z0\.d\}, p0/z, \[x0,#126\]
+.*:    855f8000        ld1rsh  \{z0\.d\}, p0/z, \[x0, #62\]
+.*:    855f8000        ld1rsh  \{z0\.d\}, p0/z, \[x0, #62\]
+.*:    85608000        ld1rsh  \{z0\.d\}, p0/z, \[x0, #64\]
+.*:    85608000        ld1rsh  \{z0\.d\}, p0/z, \[x0, #64\]
+.*:    85618000        ld1rsh  \{z0\.d\}, p0/z, \[x0, #66\]
+.*:    85618000        ld1rsh  \{z0\.d\}, p0/z, \[x0, #66\]
+.*:    857f8000        ld1rsh  \{z0\.d\}, p0/z, \[x0, #126\]
+.*:    857f8000        ld1rsh  \{z0\.d\}, p0/z, \[x0, #126\]
 .*:    8540a000        ld1rsh  \{z0\.s\}, p0/z, \[x0\]
 .*:    8540a000        ld1rsh  \{z0\.s\}, p0/z, \[x0\]
 .*:    8540a000        ld1rsh  \{z0\.s\}, p0/z, \[x0\]
@@ -13797,14 +13797,14 @@ Disassembly of section .*:
 .*:    8540a3e0        ld1rsh  \{z0\.s\}, p0/z, \[sp\]
 .*:    8540a3e0        ld1rsh  \{z0\.s\}, p0/z, \[sp\]
 .*:    8540a3e0        ld1rsh  \{z0\.s\}, p0/z, \[sp\]
-.*:    855fa000        ld1rsh  \{z0\.s\}, p0/z, \[x0,#62\]
-.*:    855fa000        ld1rsh  \{z0\.s\}, p0/z, \[x0,#62\]
-.*:    8560a000        ld1rsh  \{z0\.s\}, p0/z, \[x0,#64\]
-.*:    8560a000        ld1rsh  \{z0\.s\}, p0/z, \[x0,#64\]
-.*:    8561a000        ld1rsh  \{z0\.s\}, p0/z, \[x0,#66\]
-.*:    8561a000        ld1rsh  \{z0\.s\}, p0/z, \[x0,#66\]
-.*:    857fa000        ld1rsh  \{z0\.s\}, p0/z, \[x0,#126\]
-.*:    857fa000        ld1rsh  \{z0\.s\}, p0/z, \[x0,#126\]
+.*:    855fa000        ld1rsh  \{z0\.s\}, p0/z, \[x0, #62\]
+.*:    855fa000        ld1rsh  \{z0\.s\}, p0/z, \[x0, #62\]
+.*:    8560a000        ld1rsh  \{z0\.s\}, p0/z, \[x0, #64\]
+.*:    8560a000        ld1rsh  \{z0\.s\}, p0/z, \[x0, #64\]
+.*:    8561a000        ld1rsh  \{z0\.s\}, p0/z, \[x0, #66\]
+.*:    8561a000        ld1rsh  \{z0\.s\}, p0/z, \[x0, #66\]
+.*:    857fa000        ld1rsh  \{z0\.s\}, p0/z, \[x0, #126\]
+.*:    857fa000        ld1rsh  \{z0\.s\}, p0/z, \[x0, #126\]
 .*:    84c08000        ld1rsw  \{z0\.d\}, p0/z, \[x0\]
 .*:    84c08000        ld1rsw  \{z0\.d\}, p0/z, \[x0\]
 .*:    84c08000        ld1rsw  \{z0\.d\}, p0/z, \[x0\]
@@ -13829,14 +13829,14 @@ Disassembly of section .*:
 .*:    84c083e0        ld1rsw  \{z0\.d\}, p0/z, \[sp\]
 .*:    84c083e0        ld1rsw  \{z0\.d\}, p0/z, \[sp\]
 .*:    84c083e0        ld1rsw  \{z0\.d\}, p0/z, \[sp\]
-.*:    84df8000        ld1rsw  \{z0\.d\}, p0/z, \[x0,#124\]
-.*:    84df8000        ld1rsw  \{z0\.d\}, p0/z, \[x0,#124\]
-.*:    84e08000        ld1rsw  \{z0\.d\}, p0/z, \[x0,#128\]
-.*:    84e08000        ld1rsw  \{z0\.d\}, p0/z, \[x0,#128\]
-.*:    84e18000        ld1rsw  \{z0\.d\}, p0/z, \[x0,#132\]
-.*:    84e18000        ld1rsw  \{z0\.d\}, p0/z, \[x0,#132\]
-.*:    84ff8000        ld1rsw  \{z0\.d\}, p0/z, \[x0,#252\]
-.*:    84ff8000        ld1rsw  \{z0\.d\}, p0/z, \[x0,#252\]
+.*:    84df8000        ld1rsw  \{z0\.d\}, p0/z, \[x0, #124\]
+.*:    84df8000        ld1rsw  \{z0\.d\}, p0/z, \[x0, #124\]
+.*:    84e08000        ld1rsw  \{z0\.d\}, p0/z, \[x0, #128\]
+.*:    84e08000        ld1rsw  \{z0\.d\}, p0/z, \[x0, #128\]
+.*:    84e18000        ld1rsw  \{z0\.d\}, p0/z, \[x0, #132\]
+.*:    84e18000        ld1rsw  \{z0\.d\}, p0/z, \[x0, #132\]
+.*:    84ff8000        ld1rsw  \{z0\.d\}, p0/z, \[x0, #252\]
+.*:    84ff8000        ld1rsw  \{z0\.d\}, p0/z, \[x0, #252\]
 .*:    8540c000        ld1rw   \{z0\.s\}, p0/z, \[x0\]
 .*:    8540c000        ld1rw   \{z0\.s\}, p0/z, \[x0\]
 .*:    8540c000        ld1rw   \{z0\.s\}, p0/z, \[x0\]
@@ -13861,14 +13861,14 @@ Disassembly of section .*:
 .*:    8540c3e0        ld1rw   \{z0\.s\}, p0/z, \[sp\]
 .*:    8540c3e0        ld1rw   \{z0\.s\}, p0/z, \[sp\]
 .*:    8540c3e0        ld1rw   \{z0\.s\}, p0/z, \[sp\]
-.*:    855fc000        ld1rw   \{z0\.s\}, p0/z, \[x0,#124\]
-.*:    855fc000        ld1rw   \{z0\.s\}, p0/z, \[x0,#124\]
-.*:    8560c000        ld1rw   \{z0\.s\}, p0/z, \[x0,#128\]
-.*:    8560c000        ld1rw   \{z0\.s\}, p0/z, \[x0,#128\]
-.*:    8561c000        ld1rw   \{z0\.s\}, p0/z, \[x0,#132\]
-.*:    8561c000        ld1rw   \{z0\.s\}, p0/z, \[x0,#132\]
-.*:    857fc000        ld1rw   \{z0\.s\}, p0/z, \[x0,#252\]
-.*:    857fc000        ld1rw   \{z0\.s\}, p0/z, \[x0,#252\]
+.*:    855fc000        ld1rw   \{z0\.s\}, p0/z, \[x0, #124\]
+.*:    855fc000        ld1rw   \{z0\.s\}, p0/z, \[x0, #124\]
+.*:    8560c000        ld1rw   \{z0\.s\}, p0/z, \[x0, #128\]
+.*:    8560c000        ld1rw   \{z0\.s\}, p0/z, \[x0, #128\]
+.*:    8561c000        ld1rw   \{z0\.s\}, p0/z, \[x0, #132\]
+.*:    8561c000        ld1rw   \{z0\.s\}, p0/z, \[x0, #132\]
+.*:    857fc000        ld1rw   \{z0\.s\}, p0/z, \[x0, #252\]
+.*:    857fc000        ld1rw   \{z0\.s\}, p0/z, \[x0, #252\]
 .*:    8540e000        ld1rw   \{z0\.d\}, p0/z, \[x0\]
 .*:    8540e000        ld1rw   \{z0\.d\}, p0/z, \[x0\]
 .*:    8540e000        ld1rw   \{z0\.d\}, p0/z, \[x0\]
@@ -13893,254 +13893,254 @@ Disassembly of section .*:
 .*:    8540e3e0        ld1rw   \{z0\.d\}, p0/z, \[sp\]
 .*:    8540e3e0        ld1rw   \{z0\.d\}, p0/z, \[sp\]
 .*:    8540e3e0        ld1rw   \{z0\.d\}, p0/z, \[sp\]
-.*:    855fe000        ld1rw   \{z0\.d\}, p0/z, \[x0,#124\]
-.*:    855fe000        ld1rw   \{z0\.d\}, p0/z, \[x0,#124\]
-.*:    8560e000        ld1rw   \{z0\.d\}, p0/z, \[x0,#128\]
-.*:    8560e000        ld1rw   \{z0\.d\}, p0/z, \[x0,#128\]
-.*:    8561e000        ld1rw   \{z0\.d\}, p0/z, \[x0,#132\]
-.*:    8561e000        ld1rw   \{z0\.d\}, p0/z, \[x0,#132\]
-.*:    857fe000        ld1rw   \{z0\.d\}, p0/z, \[x0,#252\]
-.*:    857fe000        ld1rw   \{z0\.d\}, p0/z, \[x0,#252\]
-.*:    84000000        ld1sb   \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84000000        ld1sb   \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84000000        ld1sb   \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84000000        ld1sb   \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84000001        ld1sb   \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84000001        ld1sb   \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84000001        ld1sb   \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84000001        ld1sb   \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400001f        ld1sb   \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400001f        ld1sb   \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400001f        ld1sb   \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400001f        ld1sb   \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84000800        ld1sb   \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84000800        ld1sb   \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84000800        ld1sb   \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84001c00        ld1sb   \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84001c00        ld1sb   \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84001c00        ld1sb   \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84000060        ld1sb   \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84000060        ld1sb   \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84000060        ld1sb   \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    840003e0        ld1sb   \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    840003e0        ld1sb   \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    840003e0        ld1sb   \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    84040000        ld1sb   \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84040000        ld1sb   \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84040000        ld1sb   \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    841f0000        ld1sb   \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    841f0000        ld1sb   \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    841f0000        ld1sb   \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    84400000        ld1sb   \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84400000        ld1sb   \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84400000        ld1sb   \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84400000        ld1sb   \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84400001        ld1sb   \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84400001        ld1sb   \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84400001        ld1sb   \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84400001        ld1sb   \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440001f        ld1sb   \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440001f        ld1sb   \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440001f        ld1sb   \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440001f        ld1sb   \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84400800        ld1sb   \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84400800        ld1sb   \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84400800        ld1sb   \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84401c00        ld1sb   \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84401c00        ld1sb   \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84401c00        ld1sb   \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84400060        ld1sb   \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84400060        ld1sb   \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84400060        ld1sb   \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    844003e0        ld1sb   \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    844003e0        ld1sb   \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    844003e0        ld1sb   \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84440000        ld1sb   \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84440000        ld1sb   \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84440000        ld1sb   \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    845f0000        ld1sb   \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    845f0000        ld1sb   \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    845f0000        ld1sb   \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    a5804000        ld1sb   \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a5804000        ld1sb   \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a5804000        ld1sb   \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a5804000        ld1sb   \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a5804001        ld1sb   \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a5804001        ld1sb   \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a5804001        ld1sb   \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a5804001        ld1sb   \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a580401f        ld1sb   \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a580401f        ld1sb   \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a580401f        ld1sb   \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a580401f        ld1sb   \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a5804800        ld1sb   \{z0\.d\}, p2/z, \[x0,x0\]
-.*:    a5804800        ld1sb   \{z0\.d\}, p2/z, \[x0,x0\]
-.*:    a5804800        ld1sb   \{z0\.d\}, p2/z, \[x0,x0\]
-.*:    a5805c00        ld1sb   \{z0\.d\}, p7/z, \[x0,x0\]
-.*:    a5805c00        ld1sb   \{z0\.d\}, p7/z, \[x0,x0\]
-.*:    a5805c00        ld1sb   \{z0\.d\}, p7/z, \[x0,x0\]
-.*:    a5804060        ld1sb   \{z0\.d\}, p0/z, \[x3,x0\]
-.*:    a5804060        ld1sb   \{z0\.d\}, p0/z, \[x3,x0\]
-.*:    a5804060        ld1sb   \{z0\.d\}, p0/z, \[x3,x0\]
-.*:    a58043e0        ld1sb   \{z0\.d\}, p0/z, \[sp,x0\]
-.*:    a58043e0        ld1sb   \{z0\.d\}, p0/z, \[sp,x0\]
-.*:    a58043e0        ld1sb   \{z0\.d\}, p0/z, \[sp,x0\]
-.*:    a5844000        ld1sb   \{z0\.d\}, p0/z, \[x0,x4\]
-.*:    a5844000        ld1sb   \{z0\.d\}, p0/z, \[x0,x4\]
-.*:    a5844000        ld1sb   \{z0\.d\}, p0/z, \[x0,x4\]
-.*:    a59e4000        ld1sb   \{z0\.d\}, p0/z, \[x0,x30\]
-.*:    a59e4000        ld1sb   \{z0\.d\}, p0/z, \[x0,x30\]
-.*:    a59e4000        ld1sb   \{z0\.d\}, p0/z, \[x0,x30\]
-.*:    a5a04000        ld1sb   \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a5a04000        ld1sb   \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a5a04000        ld1sb   \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a5a04000        ld1sb   \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a5a04001        ld1sb   \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a5a04001        ld1sb   \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a5a04001        ld1sb   \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a5a04001        ld1sb   \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a5a0401f        ld1sb   \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a5a0401f        ld1sb   \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a5a0401f        ld1sb   \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a5a0401f        ld1sb   \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a5a04800        ld1sb   \{z0\.s\}, p2/z, \[x0,x0\]
-.*:    a5a04800        ld1sb   \{z0\.s\}, p2/z, \[x0,x0\]
-.*:    a5a04800        ld1sb   \{z0\.s\}, p2/z, \[x0,x0\]
-.*:    a5a05c00        ld1sb   \{z0\.s\}, p7/z, \[x0,x0\]
-.*:    a5a05c00        ld1sb   \{z0\.s\}, p7/z, \[x0,x0\]
-.*:    a5a05c00        ld1sb   \{z0\.s\}, p7/z, \[x0,x0\]
-.*:    a5a04060        ld1sb   \{z0\.s\}, p0/z, \[x3,x0\]
-.*:    a5a04060        ld1sb   \{z0\.s\}, p0/z, \[x3,x0\]
-.*:    a5a04060        ld1sb   \{z0\.s\}, p0/z, \[x3,x0\]
-.*:    a5a043e0        ld1sb   \{z0\.s\}, p0/z, \[sp,x0\]
-.*:    a5a043e0        ld1sb   \{z0\.s\}, p0/z, \[sp,x0\]
-.*:    a5a043e0        ld1sb   \{z0\.s\}, p0/z, \[sp,x0\]
-.*:    a5a44000        ld1sb   \{z0\.s\}, p0/z, \[x0,x4\]
-.*:    a5a44000        ld1sb   \{z0\.s\}, p0/z, \[x0,x4\]
-.*:    a5a44000        ld1sb   \{z0\.s\}, p0/z, \[x0,x4\]
-.*:    a5be4000        ld1sb   \{z0\.s\}, p0/z, \[x0,x30\]
-.*:    a5be4000        ld1sb   \{z0\.s\}, p0/z, \[x0,x30\]
-.*:    a5be4000        ld1sb   \{z0\.s\}, p0/z, \[x0,x30\]
-.*:    a5c04000        ld1sb   \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a5c04000        ld1sb   \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a5c04000        ld1sb   \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a5c04000        ld1sb   \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a5c04001        ld1sb   \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a5c04001        ld1sb   \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a5c04001        ld1sb   \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a5c04001        ld1sb   \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a5c0401f        ld1sb   \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a5c0401f        ld1sb   \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a5c0401f        ld1sb   \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a5c0401f        ld1sb   \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a5c04800        ld1sb   \{z0\.h\}, p2/z, \[x0,x0\]
-.*:    a5c04800        ld1sb   \{z0\.h\}, p2/z, \[x0,x0\]
-.*:    a5c04800        ld1sb   \{z0\.h\}, p2/z, \[x0,x0\]
-.*:    a5c05c00        ld1sb   \{z0\.h\}, p7/z, \[x0,x0\]
-.*:    a5c05c00        ld1sb   \{z0\.h\}, p7/z, \[x0,x0\]
-.*:    a5c05c00        ld1sb   \{z0\.h\}, p7/z, \[x0,x0\]
-.*:    a5c04060        ld1sb   \{z0\.h\}, p0/z, \[x3,x0\]
-.*:    a5c04060        ld1sb   \{z0\.h\}, p0/z, \[x3,x0\]
-.*:    a5c04060        ld1sb   \{z0\.h\}, p0/z, \[x3,x0\]
-.*:    a5c043e0        ld1sb   \{z0\.h\}, p0/z, \[sp,x0\]
-.*:    a5c043e0        ld1sb   \{z0\.h\}, p0/z, \[sp,x0\]
-.*:    a5c043e0        ld1sb   \{z0\.h\}, p0/z, \[sp,x0\]
-.*:    a5c44000        ld1sb   \{z0\.h\}, p0/z, \[x0,x4\]
-.*:    a5c44000        ld1sb   \{z0\.h\}, p0/z, \[x0,x4\]
-.*:    a5c44000        ld1sb   \{z0\.h\}, p0/z, \[x0,x4\]
-.*:    a5de4000        ld1sb   \{z0\.h\}, p0/z, \[x0,x30\]
-.*:    a5de4000        ld1sb   \{z0\.h\}, p0/z, \[x0,x30\]
-.*:    a5de4000        ld1sb   \{z0\.h\}, p0/z, \[x0,x30\]
-.*:    c4000000        ld1sb   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4000000        ld1sb   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4000000        ld1sb   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4000000        ld1sb   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4000001        ld1sb   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4000001        ld1sb   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4000001        ld1sb   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4000001        ld1sb   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400001f        ld1sb   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400001f        ld1sb   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400001f        ld1sb   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400001f        ld1sb   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4000800        ld1sb   \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4000800        ld1sb   \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4000800        ld1sb   \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4001c00        ld1sb   \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4001c00        ld1sb   \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4001c00        ld1sb   \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4000060        ld1sb   \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4000060        ld1sb   \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4000060        ld1sb   \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c40003e0        ld1sb   \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c40003e0        ld1sb   \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c40003e0        ld1sb   \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c4040000        ld1sb   \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4040000        ld1sb   \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4040000        ld1sb   \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c41f0000        ld1sb   \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c41f0000        ld1sb   \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c41f0000        ld1sb   \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c4400000        ld1sb   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4400000        ld1sb   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4400000        ld1sb   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4400000        ld1sb   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4400001        ld1sb   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4400001        ld1sb   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4400001        ld1sb   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4400001        ld1sb   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440001f        ld1sb   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440001f        ld1sb   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440001f        ld1sb   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440001f        ld1sb   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4400800        ld1sb   \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4400800        ld1sb   \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4400800        ld1sb   \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4401c00        ld1sb   \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4401c00        ld1sb   \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4401c00        ld1sb   \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4400060        ld1sb   \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4400060        ld1sb   \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4400060        ld1sb   \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c44003e0        ld1sb   \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c44003e0        ld1sb   \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c44003e0        ld1sb   \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4440000        ld1sb   \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4440000        ld1sb   \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4440000        ld1sb   \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c45f0000        ld1sb   \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c45f0000        ld1sb   \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c45f0000        ld1sb   \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c4408000        ld1sb   \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4408000        ld1sb   \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4408000        ld1sb   \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4408000        ld1sb   \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4408001        ld1sb   \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4408001        ld1sb   \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4408001        ld1sb   \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4408001        ld1sb   \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440801f        ld1sb   \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440801f        ld1sb   \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440801f        ld1sb   \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440801f        ld1sb   \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4408800        ld1sb   \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4408800        ld1sb   \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4408800        ld1sb   \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4409c00        ld1sb   \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4409c00        ld1sb   \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4409c00        ld1sb   \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4408060        ld1sb   \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c4408060        ld1sb   \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c4408060        ld1sb   \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c44083e0        ld1sb   \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c44083e0        ld1sb   \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c44083e0        ld1sb   \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c4448000        ld1sb   \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c4448000        ld1sb   \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c4448000        ld1sb   \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c45f8000        ld1sb   \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c45f8000        ld1sb   \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c45f8000        ld1sb   \{z0\.d\}, p0/z, \[x0,z31\.d\]
+.*:    855fe000        ld1rw   \{z0\.d\}, p0/z, \[x0, #124\]
+.*:    855fe000        ld1rw   \{z0\.d\}, p0/z, \[x0, #124\]
+.*:    8560e000        ld1rw   \{z0\.d\}, p0/z, \[x0, #128\]
+.*:    8560e000        ld1rw   \{z0\.d\}, p0/z, \[x0, #128\]
+.*:    8561e000        ld1rw   \{z0\.d\}, p0/z, \[x0, #132\]
+.*:    8561e000        ld1rw   \{z0\.d\}, p0/z, \[x0, #132\]
+.*:    857fe000        ld1rw   \{z0\.d\}, p0/z, \[x0, #252\]
+.*:    857fe000        ld1rw   \{z0\.d\}, p0/z, \[x0, #252\]
+.*:    84000000        ld1sb   \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84000000        ld1sb   \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84000000        ld1sb   \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84000000        ld1sb   \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84000001        ld1sb   \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84000001        ld1sb   \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84000001        ld1sb   \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84000001        ld1sb   \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400001f        ld1sb   \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400001f        ld1sb   \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400001f        ld1sb   \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400001f        ld1sb   \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84000800        ld1sb   \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84000800        ld1sb   \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84000800        ld1sb   \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84001c00        ld1sb   \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84001c00        ld1sb   \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84001c00        ld1sb   \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84000060        ld1sb   \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84000060        ld1sb   \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84000060        ld1sb   \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    840003e0        ld1sb   \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    840003e0        ld1sb   \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    840003e0        ld1sb   \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    84040000        ld1sb   \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84040000        ld1sb   \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84040000        ld1sb   \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    841f0000        ld1sb   \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    841f0000        ld1sb   \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    841f0000        ld1sb   \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    84400000        ld1sb   \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84400000        ld1sb   \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84400000        ld1sb   \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84400000        ld1sb   \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84400001        ld1sb   \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84400001        ld1sb   \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84400001        ld1sb   \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84400001        ld1sb   \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440001f        ld1sb   \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440001f        ld1sb   \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440001f        ld1sb   \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440001f        ld1sb   \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84400800        ld1sb   \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84400800        ld1sb   \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84400800        ld1sb   \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84401c00        ld1sb   \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84401c00        ld1sb   \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84401c00        ld1sb   \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84400060        ld1sb   \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84400060        ld1sb   \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84400060        ld1sb   \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    844003e0        ld1sb   \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    844003e0        ld1sb   \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    844003e0        ld1sb   \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84440000        ld1sb   \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84440000        ld1sb   \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84440000        ld1sb   \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    845f0000        ld1sb   \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    845f0000        ld1sb   \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    845f0000        ld1sb   \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    a5804000        ld1sb   \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a5804000        ld1sb   \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a5804000        ld1sb   \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a5804000        ld1sb   \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a5804001        ld1sb   \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a5804001        ld1sb   \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a5804001        ld1sb   \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a5804001        ld1sb   \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a580401f        ld1sb   \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a580401f        ld1sb   \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a580401f        ld1sb   \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a580401f        ld1sb   \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a5804800        ld1sb   \{z0\.d\}, p2/z, \[x0, x0\]
+.*:    a5804800        ld1sb   \{z0\.d\}, p2/z, \[x0, x0\]
+.*:    a5804800        ld1sb   \{z0\.d\}, p2/z, \[x0, x0\]
+.*:    a5805c00        ld1sb   \{z0\.d\}, p7/z, \[x0, x0\]
+.*:    a5805c00        ld1sb   \{z0\.d\}, p7/z, \[x0, x0\]
+.*:    a5805c00        ld1sb   \{z0\.d\}, p7/z, \[x0, x0\]
+.*:    a5804060        ld1sb   \{z0\.d\}, p0/z, \[x3, x0\]
+.*:    a5804060        ld1sb   \{z0\.d\}, p0/z, \[x3, x0\]
+.*:    a5804060        ld1sb   \{z0\.d\}, p0/z, \[x3, x0\]
+.*:    a58043e0        ld1sb   \{z0\.d\}, p0/z, \[sp, x0\]
+.*:    a58043e0        ld1sb   \{z0\.d\}, p0/z, \[sp, x0\]
+.*:    a58043e0        ld1sb   \{z0\.d\}, p0/z, \[sp, x0\]
+.*:    a5844000        ld1sb   \{z0\.d\}, p0/z, \[x0, x4\]
+.*:    a5844000        ld1sb   \{z0\.d\}, p0/z, \[x0, x4\]
+.*:    a5844000        ld1sb   \{z0\.d\}, p0/z, \[x0, x4\]
+.*:    a59e4000        ld1sb   \{z0\.d\}, p0/z, \[x0, x30\]
+.*:    a59e4000        ld1sb   \{z0\.d\}, p0/z, \[x0, x30\]
+.*:    a59e4000        ld1sb   \{z0\.d\}, p0/z, \[x0, x30\]
+.*:    a5a04000        ld1sb   \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a5a04000        ld1sb   \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a5a04000        ld1sb   \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a5a04000        ld1sb   \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a5a04001        ld1sb   \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a5a04001        ld1sb   \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a5a04001        ld1sb   \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a5a04001        ld1sb   \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a5a0401f        ld1sb   \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a5a0401f        ld1sb   \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a5a0401f        ld1sb   \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a5a0401f        ld1sb   \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a5a04800        ld1sb   \{z0\.s\}, p2/z, \[x0, x0\]
+.*:    a5a04800        ld1sb   \{z0\.s\}, p2/z, \[x0, x0\]
+.*:    a5a04800        ld1sb   \{z0\.s\}, p2/z, \[x0, x0\]
+.*:    a5a05c00        ld1sb   \{z0\.s\}, p7/z, \[x0, x0\]
+.*:    a5a05c00        ld1sb   \{z0\.s\}, p7/z, \[x0, x0\]
+.*:    a5a05c00        ld1sb   \{z0\.s\}, p7/z, \[x0, x0\]
+.*:    a5a04060        ld1sb   \{z0\.s\}, p0/z, \[x3, x0\]
+.*:    a5a04060        ld1sb   \{z0\.s\}, p0/z, \[x3, x0\]
+.*:    a5a04060        ld1sb   \{z0\.s\}, p0/z, \[x3, x0\]
+.*:    a5a043e0        ld1sb   \{z0\.s\}, p0/z, \[sp, x0\]
+.*:    a5a043e0        ld1sb   \{z0\.s\}, p0/z, \[sp, x0\]
+.*:    a5a043e0        ld1sb   \{z0\.s\}, p0/z, \[sp, x0\]
+.*:    a5a44000        ld1sb   \{z0\.s\}, p0/z, \[x0, x4\]
+.*:    a5a44000        ld1sb   \{z0\.s\}, p0/z, \[x0, x4\]
+.*:    a5a44000        ld1sb   \{z0\.s\}, p0/z, \[x0, x4\]
+.*:    a5be4000        ld1sb   \{z0\.s\}, p0/z, \[x0, x30\]
+.*:    a5be4000        ld1sb   \{z0\.s\}, p0/z, \[x0, x30\]
+.*:    a5be4000        ld1sb   \{z0\.s\}, p0/z, \[x0, x30\]
+.*:    a5c04000        ld1sb   \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a5c04000        ld1sb   \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a5c04000        ld1sb   \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a5c04000        ld1sb   \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a5c04001        ld1sb   \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a5c04001        ld1sb   \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a5c04001        ld1sb   \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a5c04001        ld1sb   \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a5c0401f        ld1sb   \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a5c0401f        ld1sb   \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a5c0401f        ld1sb   \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a5c0401f        ld1sb   \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a5c04800        ld1sb   \{z0\.h\}, p2/z, \[x0, x0\]
+.*:    a5c04800        ld1sb   \{z0\.h\}, p2/z, \[x0, x0\]
+.*:    a5c04800        ld1sb   \{z0\.h\}, p2/z, \[x0, x0\]
+.*:    a5c05c00        ld1sb   \{z0\.h\}, p7/z, \[x0, x0\]
+.*:    a5c05c00        ld1sb   \{z0\.h\}, p7/z, \[x0, x0\]
+.*:    a5c05c00        ld1sb   \{z0\.h\}, p7/z, \[x0, x0\]
+.*:    a5c04060        ld1sb   \{z0\.h\}, p0/z, \[x3, x0\]
+.*:    a5c04060        ld1sb   \{z0\.h\}, p0/z, \[x3, x0\]
+.*:    a5c04060        ld1sb   \{z0\.h\}, p0/z, \[x3, x0\]
+.*:    a5c043e0        ld1sb   \{z0\.h\}, p0/z, \[sp, x0\]
+.*:    a5c043e0        ld1sb   \{z0\.h\}, p0/z, \[sp, x0\]
+.*:    a5c043e0        ld1sb   \{z0\.h\}, p0/z, \[sp, x0\]
+.*:    a5c44000        ld1sb   \{z0\.h\}, p0/z, \[x0, x4\]
+.*:    a5c44000        ld1sb   \{z0\.h\}, p0/z, \[x0, x4\]
+.*:    a5c44000        ld1sb   \{z0\.h\}, p0/z, \[x0, x4\]
+.*:    a5de4000        ld1sb   \{z0\.h\}, p0/z, \[x0, x30\]
+.*:    a5de4000        ld1sb   \{z0\.h\}, p0/z, \[x0, x30\]
+.*:    a5de4000        ld1sb   \{z0\.h\}, p0/z, \[x0, x30\]
+.*:    c4000000        ld1sb   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4000000        ld1sb   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4000000        ld1sb   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4000000        ld1sb   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4000001        ld1sb   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4000001        ld1sb   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4000001        ld1sb   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4000001        ld1sb   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400001f        ld1sb   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400001f        ld1sb   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400001f        ld1sb   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400001f        ld1sb   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4000800        ld1sb   \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4000800        ld1sb   \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4000800        ld1sb   \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4001c00        ld1sb   \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4001c00        ld1sb   \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4001c00        ld1sb   \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4000060        ld1sb   \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4000060        ld1sb   \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4000060        ld1sb   \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c40003e0        ld1sb   \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c40003e0        ld1sb   \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c40003e0        ld1sb   \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c4040000        ld1sb   \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4040000        ld1sb   \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4040000        ld1sb   \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c41f0000        ld1sb   \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c41f0000        ld1sb   \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c41f0000        ld1sb   \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c4400000        ld1sb   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4400000        ld1sb   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4400000        ld1sb   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4400000        ld1sb   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4400001        ld1sb   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4400001        ld1sb   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4400001        ld1sb   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4400001        ld1sb   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440001f        ld1sb   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440001f        ld1sb   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440001f        ld1sb   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440001f        ld1sb   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4400800        ld1sb   \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4400800        ld1sb   \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4400800        ld1sb   \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4401c00        ld1sb   \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4401c00        ld1sb   \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4401c00        ld1sb   \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4400060        ld1sb   \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4400060        ld1sb   \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4400060        ld1sb   \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c44003e0        ld1sb   \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c44003e0        ld1sb   \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c44003e0        ld1sb   \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4440000        ld1sb   \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4440000        ld1sb   \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4440000        ld1sb   \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c45f0000        ld1sb   \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c45f0000        ld1sb   \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c45f0000        ld1sb   \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c4408000        ld1sb   \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4408000        ld1sb   \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4408000        ld1sb   \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4408000        ld1sb   \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4408001        ld1sb   \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4408001        ld1sb   \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4408001        ld1sb   \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4408001        ld1sb   \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440801f        ld1sb   \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440801f        ld1sb   \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440801f        ld1sb   \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440801f        ld1sb   \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4408800        ld1sb   \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4408800        ld1sb   \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4408800        ld1sb   \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4409c00        ld1sb   \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4409c00        ld1sb   \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4409c00        ld1sb   \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4408060        ld1sb   \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c4408060        ld1sb   \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c4408060        ld1sb   \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c44083e0        ld1sb   \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c44083e0        ld1sb   \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c44083e0        ld1sb   \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c4448000        ld1sb   \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c4448000        ld1sb   \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c4448000        ld1sb   \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c45f8000        ld1sb   \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c45f8000        ld1sb   \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c45f8000        ld1sb   \{z0\.d\}, p0/z, \[x0, z31\.d\]
 .*:    84208000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    84208000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    84208000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s\]
@@ -14165,14 +14165,14 @@ Disassembly of section .*:
 .*:    842083e0        ld1sb   \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    842083e0        ld1sb   \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    842083e0        ld1sb   \{z0\.s\}, p0/z, \[z31\.s\]
-.*:    842f8000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s,#15\]
-.*:    842f8000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s,#15\]
-.*:    84308000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s,#16\]
-.*:    84308000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s,#16\]
-.*:    84318000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s,#17\]
-.*:    84318000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s,#17\]
-.*:    843f8000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s,#31\]
-.*:    843f8000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s,#31\]
+.*:    842f8000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s, #15\]
+.*:    842f8000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s, #15\]
+.*:    84308000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s, #16\]
+.*:    84308000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s, #16\]
+.*:    84318000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s, #17\]
+.*:    84318000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s, #17\]
+.*:    843f8000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s, #31\]
+.*:    843f8000        ld1sb   \{z0\.s\}, p0/z, \[z0\.s, #31\]
 .*:    a580a000        ld1sb   \{z0\.d\}, p0/z, \[x0\]
 .*:    a580a000        ld1sb   \{z0\.d\}, p0/z, \[x0\]
 .*:    a580a000        ld1sb   \{z0\.d\}, p0/z, \[x0\]
@@ -14204,14 +14204,14 @@ Disassembly of section .*:
 .*:    a580a3e0        ld1sb   \{z0\.d\}, p0/z, \[sp\]
 .*:    a580a3e0        ld1sb   \{z0\.d\}, p0/z, \[sp\]
 .*:    a580a3e0        ld1sb   \{z0\.d\}, p0/z, \[sp\]
-.*:    a587a000        ld1sb   \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a587a000        ld1sb   \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a588a000        ld1sb   \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a588a000        ld1sb   \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a589a000        ld1sb   \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a589a000        ld1sb   \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a58fa000        ld1sb   \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a58fa000        ld1sb   \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a587a000        ld1sb   \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a587a000        ld1sb   \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a588a000        ld1sb   \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a588a000        ld1sb   \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a589a000        ld1sb   \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a589a000        ld1sb   \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a58fa000        ld1sb   \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a58fa000        ld1sb   \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a5a0a000        ld1sb   \{z0\.s\}, p0/z, \[x0\]
 .*:    a5a0a000        ld1sb   \{z0\.s\}, p0/z, \[x0\]
 .*:    a5a0a000        ld1sb   \{z0\.s\}, p0/z, \[x0\]
@@ -14243,14 +14243,14 @@ Disassembly of section .*:
 .*:    a5a0a3e0        ld1sb   \{z0\.s\}, p0/z, \[sp\]
 .*:    a5a0a3e0        ld1sb   \{z0\.s\}, p0/z, \[sp\]
 .*:    a5a0a3e0        ld1sb   \{z0\.s\}, p0/z, \[sp\]
-.*:    a5a7a000        ld1sb   \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a5a7a000        ld1sb   \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a5a8a000        ld1sb   \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a5a8a000        ld1sb   \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a5a9a000        ld1sb   \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a5a9a000        ld1sb   \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a5afa000        ld1sb   \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a5afa000        ld1sb   \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a5a7a000        ld1sb   \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a5a7a000        ld1sb   \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a5a8a000        ld1sb   \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a5a8a000        ld1sb   \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a5a9a000        ld1sb   \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a5a9a000        ld1sb   \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a5afa000        ld1sb   \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a5afa000        ld1sb   \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a5c0a000        ld1sb   \{z0\.h\}, p0/z, \[x0\]
 .*:    a5c0a000        ld1sb   \{z0\.h\}, p0/z, \[x0\]
 .*:    a5c0a000        ld1sb   \{z0\.h\}, p0/z, \[x0\]
@@ -14282,14 +14282,14 @@ Disassembly of section .*:
 .*:    a5c0a3e0        ld1sb   \{z0\.h\}, p0/z, \[sp\]
 .*:    a5c0a3e0        ld1sb   \{z0\.h\}, p0/z, \[sp\]
 .*:    a5c0a3e0        ld1sb   \{z0\.h\}, p0/z, \[sp\]
-.*:    a5c7a000        ld1sb   \{z0\.h\}, p0/z, \[x0,#7,mul vl\]
-.*:    a5c7a000        ld1sb   \{z0\.h\}, p0/z, \[x0,#7,mul vl\]
-.*:    a5c8a000        ld1sb   \{z0\.h\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a5c8a000        ld1sb   \{z0\.h\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a5c9a000        ld1sb   \{z0\.h\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a5c9a000        ld1sb   \{z0\.h\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a5cfa000        ld1sb   \{z0\.h\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a5cfa000        ld1sb   \{z0\.h\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a5c7a000        ld1sb   \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
+.*:    a5c7a000        ld1sb   \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
+.*:    a5c8a000        ld1sb   \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a5c8a000        ld1sb   \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a5c9a000        ld1sb   \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a5c9a000        ld1sb   \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a5cfa000        ld1sb   \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a5cfa000        ld1sb   \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
 .*:    c4208000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c4208000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c4208000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d\]
@@ -14314,311 +14314,311 @@ Disassembly of section .*:
 .*:    c42083e0        ld1sb   \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c42083e0        ld1sb   \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c42083e0        ld1sb   \{z0\.d\}, p0/z, \[z31\.d\]
-.*:    c42f8000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d,#15\]
-.*:    c42f8000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d,#15\]
-.*:    c4308000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d,#16\]
-.*:    c4308000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d,#16\]
-.*:    c4318000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d,#17\]
-.*:    c4318000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d,#17\]
-.*:    c43f8000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d,#31\]
-.*:    c43f8000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d,#31\]
-.*:    84800000        ld1sh   \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84800000        ld1sh   \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84800000        ld1sh   \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84800000        ld1sh   \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84800001        ld1sh   \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84800001        ld1sh   \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84800001        ld1sh   \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84800001        ld1sh   \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480001f        ld1sh   \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480001f        ld1sh   \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480001f        ld1sh   \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480001f        ld1sh   \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84800800        ld1sh   \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84800800        ld1sh   \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84800800        ld1sh   \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84801c00        ld1sh   \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84801c00        ld1sh   \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84801c00        ld1sh   \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84800060        ld1sh   \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84800060        ld1sh   \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84800060        ld1sh   \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    848003e0        ld1sh   \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    848003e0        ld1sh   \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    848003e0        ld1sh   \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    84840000        ld1sh   \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84840000        ld1sh   \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84840000        ld1sh   \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    849f0000        ld1sh   \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    849f0000        ld1sh   \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    849f0000        ld1sh   \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    84c00000        ld1sh   \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c00000        ld1sh   \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c00000        ld1sh   \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c00000        ld1sh   \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c00001        ld1sh   \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c00001        ld1sh   \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c00001        ld1sh   \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c00001        ld1sh   \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0001f        ld1sh   \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0001f        ld1sh   \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0001f        ld1sh   \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0001f        ld1sh   \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c00800        ld1sh   \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84c00800        ld1sh   \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84c00800        ld1sh   \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84c01c00        ld1sh   \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84c01c00        ld1sh   \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84c01c00        ld1sh   \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84c00060        ld1sh   \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84c00060        ld1sh   \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84c00060        ld1sh   \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84c003e0        ld1sh   \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84c003e0        ld1sh   \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84c003e0        ld1sh   \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84c40000        ld1sh   \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84c40000        ld1sh   \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84c40000        ld1sh   \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84df0000        ld1sh   \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    84df0000        ld1sh   \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    84df0000        ld1sh   \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    84a00000        ld1sh   \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a00000        ld1sh   \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a00000        ld1sh   \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a00001        ld1sh   \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a00001        ld1sh   \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a00001        ld1sh   \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a0001f        ld1sh   \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a0001f        ld1sh   \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a0001f        ld1sh   \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a00800        ld1sh   \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a00800        ld1sh   \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a01c00        ld1sh   \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a01c00        ld1sh   \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a00060        ld1sh   \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\]
-.*:    84a00060        ld1sh   \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\]
-.*:    84a003e0        ld1sh   \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\]
-.*:    84a003e0        ld1sh   \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\]
-.*:    84a40000        ld1sh   \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\]
-.*:    84a40000        ld1sh   \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\]
-.*:    84bf0000        ld1sh   \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\]
-.*:    84bf0000        ld1sh   \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\]
-.*:    84e00000        ld1sh   \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e00000        ld1sh   \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e00000        ld1sh   \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e00001        ld1sh   \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e00001        ld1sh   \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e00001        ld1sh   \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e0001f        ld1sh   \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e0001f        ld1sh   \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e0001f        ld1sh   \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e00800        ld1sh   \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e00800        ld1sh   \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e01c00        ld1sh   \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e01c00        ld1sh   \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e00060        ld1sh   \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\]
-.*:    84e00060        ld1sh   \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\]
-.*:    84e003e0        ld1sh   \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\]
-.*:    84e003e0        ld1sh   \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\]
-.*:    84e40000        ld1sh   \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\]
-.*:    84e40000        ld1sh   \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\]
-.*:    84ff0000        ld1sh   \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\]
-.*:    84ff0000        ld1sh   \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\]
-.*:    a5004000        ld1sh   \{z0\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5004000        ld1sh   \{z0\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5004000        ld1sh   \{z0\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5004001        ld1sh   \{z1\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5004001        ld1sh   \{z1\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5004001        ld1sh   \{z1\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a500401f        ld1sh   \{z31\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a500401f        ld1sh   \{z31\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a500401f        ld1sh   \{z31\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5004800        ld1sh   \{z0\.d\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a5004800        ld1sh   \{z0\.d\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a5005c00        ld1sh   \{z0\.d\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a5005c00        ld1sh   \{z0\.d\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a5004060        ld1sh   \{z0\.d\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a5004060        ld1sh   \{z0\.d\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a50043e0        ld1sh   \{z0\.d\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a50043e0        ld1sh   \{z0\.d\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a5044000        ld1sh   \{z0\.d\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a5044000        ld1sh   \{z0\.d\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a51e4000        ld1sh   \{z0\.d\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a51e4000        ld1sh   \{z0\.d\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a5204000        ld1sh   \{z0\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5204000        ld1sh   \{z0\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5204000        ld1sh   \{z0\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5204001        ld1sh   \{z1\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5204001        ld1sh   \{z1\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5204001        ld1sh   \{z1\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a520401f        ld1sh   \{z31\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a520401f        ld1sh   \{z31\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a520401f        ld1sh   \{z31\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5204800        ld1sh   \{z0\.s\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a5204800        ld1sh   \{z0\.s\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a5205c00        ld1sh   \{z0\.s\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a5205c00        ld1sh   \{z0\.s\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a5204060        ld1sh   \{z0\.s\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a5204060        ld1sh   \{z0\.s\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a52043e0        ld1sh   \{z0\.s\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a52043e0        ld1sh   \{z0\.s\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a5244000        ld1sh   \{z0\.s\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a5244000        ld1sh   \{z0\.s\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a53e4000        ld1sh   \{z0\.s\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a53e4000        ld1sh   \{z0\.s\}, p0/z, \[x0,x30,lsl #1\]
-.*:    c4800000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4800000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4800000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4800000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4800001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4800001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4800001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4800001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480001f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480001f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480001f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480001f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4800800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4800800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4800800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4801c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4801c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4801c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4800060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4800060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4800060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c48003e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c48003e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c48003e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c4840000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4840000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4840000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c49f0000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c49f0000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c49f0000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c4c00000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c00000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c00000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c00000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c00001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c00001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c00001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c00001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0001f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0001f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0001f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0001f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c00800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4c00800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4c00800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4c01c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4c01c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4c01c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4c00060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4c00060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4c00060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4c003e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4c003e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4c003e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4c40000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4c40000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4c40000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4df0000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c4df0000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c4df0000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c4a00000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a00000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a00000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a00001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a00001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a00001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a0001f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a0001f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a0001f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a00800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a00800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a01c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a01c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a00060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\]
-.*:    c4a00060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\]
-.*:    c4a003e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\]
-.*:    c4a003e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\]
-.*:    c4a40000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\]
-.*:    c4a40000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\]
-.*:    c4bf0000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\]
-.*:    c4bf0000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\]
-.*:    c4e00000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e00000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e00000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e00001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e00001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e00001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e0001f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e0001f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e0001f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e00800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e00800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e01c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e01c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e00060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\]
-.*:    c4e00060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\]
-.*:    c4e003e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\]
-.*:    c4e003e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\]
-.*:    c4e40000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\]
-.*:    c4e40000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\]
-.*:    c4ff0000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\]
-.*:    c4ff0000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\]
-.*:    c4c08000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c08000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c08000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c08000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c08001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c08001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c08001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c08001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0801f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0801f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0801f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0801f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c08800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4c08800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4c08800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4c09c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4c09c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4c09c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4c08060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c4c08060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c4c08060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c4c083e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c4c083e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c4c083e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c4c48000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c4c48000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c4c48000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c4df8000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c4df8000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c4df8000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c4e08000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e08000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e08000        ld1sh   \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e08001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e08001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e08001        ld1sh   \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0801f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0801f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0801f        ld1sh   \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e08800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e08800        ld1sh   \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e09c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e09c00        ld1sh   \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e08060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\]
-.*:    c4e08060        ld1sh   \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\]
-.*:    c4e083e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\]
-.*:    c4e083e0        ld1sh   \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\]
-.*:    c4e48000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\]
-.*:    c4e48000        ld1sh   \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\]
-.*:    c4ff8000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\]
-.*:    c4ff8000        ld1sh   \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\]
+.*:    c42f8000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d, #15\]
+.*:    c42f8000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d, #15\]
+.*:    c4308000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d, #16\]
+.*:    c4308000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d, #16\]
+.*:    c4318000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d, #17\]
+.*:    c4318000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d, #17\]
+.*:    c43f8000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d, #31\]
+.*:    c43f8000        ld1sb   \{z0\.d\}, p0/z, \[z0\.d, #31\]
+.*:    84800000        ld1sh   \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84800000        ld1sh   \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84800000        ld1sh   \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84800000        ld1sh   \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84800001        ld1sh   \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84800001        ld1sh   \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84800001        ld1sh   \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84800001        ld1sh   \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480001f        ld1sh   \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480001f        ld1sh   \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480001f        ld1sh   \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480001f        ld1sh   \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84800800        ld1sh   \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84800800        ld1sh   \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84800800        ld1sh   \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84801c00        ld1sh   \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84801c00        ld1sh   \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84801c00        ld1sh   \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84800060        ld1sh   \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84800060        ld1sh   \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84800060        ld1sh   \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    848003e0        ld1sh   \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    848003e0        ld1sh   \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    848003e0        ld1sh   \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    84840000        ld1sh   \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84840000        ld1sh   \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84840000        ld1sh   \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    849f0000        ld1sh   \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    849f0000        ld1sh   \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    849f0000        ld1sh   \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    84c00000        ld1sh   \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c00000        ld1sh   \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c00000        ld1sh   \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c00000        ld1sh   \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c00001        ld1sh   \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c00001        ld1sh   \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c00001        ld1sh   \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c00001        ld1sh   \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0001f        ld1sh   \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0001f        ld1sh   \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0001f        ld1sh   \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0001f        ld1sh   \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c00800        ld1sh   \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84c00800        ld1sh   \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84c00800        ld1sh   \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84c01c00        ld1sh   \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84c01c00        ld1sh   \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84c01c00        ld1sh   \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84c00060        ld1sh   \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84c00060        ld1sh   \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84c00060        ld1sh   \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84c003e0        ld1sh   \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84c003e0        ld1sh   \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84c003e0        ld1sh   \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84c40000        ld1sh   \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84c40000        ld1sh   \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84c40000        ld1sh   \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84df0000        ld1sh   \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    84df0000        ld1sh   \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    84df0000        ld1sh   \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    84a00000        ld1sh   \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a00000        ld1sh   \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a00000        ld1sh   \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a00001        ld1sh   \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a00001        ld1sh   \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a00001        ld1sh   \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a0001f        ld1sh   \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a0001f        ld1sh   \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a0001f        ld1sh   \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a00800        ld1sh   \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a00800        ld1sh   \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a01c00        ld1sh   \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a01c00        ld1sh   \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a00060        ld1sh   \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
+.*:    84a00060        ld1sh   \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
+.*:    84a003e0        ld1sh   \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
+.*:    84a003e0        ld1sh   \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
+.*:    84a40000        ld1sh   \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
+.*:    84a40000        ld1sh   \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
+.*:    84bf0000        ld1sh   \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
+.*:    84bf0000        ld1sh   \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
+.*:    84e00000        ld1sh   \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e00000        ld1sh   \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e00000        ld1sh   \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e00001        ld1sh   \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e00001        ld1sh   \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e00001        ld1sh   \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e0001f        ld1sh   \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e0001f        ld1sh   \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e0001f        ld1sh   \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e00800        ld1sh   \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e00800        ld1sh   \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e01c00        ld1sh   \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e01c00        ld1sh   \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e00060        ld1sh   \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
+.*:    84e00060        ld1sh   \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
+.*:    84e003e0        ld1sh   \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
+.*:    84e003e0        ld1sh   \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
+.*:    84e40000        ld1sh   \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
+.*:    84e40000        ld1sh   \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
+.*:    84ff0000        ld1sh   \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
+.*:    84ff0000        ld1sh   \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
+.*:    a5004000        ld1sh   \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5004000        ld1sh   \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5004000        ld1sh   \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5004001        ld1sh   \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5004001        ld1sh   \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5004001        ld1sh   \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a500401f        ld1sh   \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a500401f        ld1sh   \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a500401f        ld1sh   \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5004800        ld1sh   \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a5004800        ld1sh   \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a5005c00        ld1sh   \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a5005c00        ld1sh   \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a5004060        ld1sh   \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a5004060        ld1sh   \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a50043e0        ld1sh   \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a50043e0        ld1sh   \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a5044000        ld1sh   \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a5044000        ld1sh   \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a51e4000        ld1sh   \{z0\.d\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a51e4000        ld1sh   \{z0\.d\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a5204000        ld1sh   \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5204000        ld1sh   \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5204000        ld1sh   \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5204001        ld1sh   \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5204001        ld1sh   \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5204001        ld1sh   \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a520401f        ld1sh   \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a520401f        ld1sh   \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a520401f        ld1sh   \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5204800        ld1sh   \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a5204800        ld1sh   \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a5205c00        ld1sh   \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a5205c00        ld1sh   \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a5204060        ld1sh   \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a5204060        ld1sh   \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a52043e0        ld1sh   \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a52043e0        ld1sh   \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a5244000        ld1sh   \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a5244000        ld1sh   \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a53e4000        ld1sh   \{z0\.s\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a53e4000        ld1sh   \{z0\.s\}, p0/z, \[x0, x30, lsl #1\]
+.*:    c4800000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4800000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4800000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4800000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4800001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4800001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4800001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4800001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480001f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480001f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480001f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480001f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4800800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4800800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4800800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4801c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4801c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4801c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4800060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4800060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4800060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c48003e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c48003e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c48003e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c4840000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4840000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4840000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c49f0000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c49f0000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c49f0000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c4c00000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c00000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c00000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c00000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c00001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c00001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c00001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c00001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0001f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0001f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0001f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0001f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c00800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4c00800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4c00800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4c01c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4c01c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4c01c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4c00060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4c00060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4c00060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4c003e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4c003e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4c003e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4c40000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4c40000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4c40000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4df0000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c4df0000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c4df0000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c4a00000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a00000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a00000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a00001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a00001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a00001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a0001f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a0001f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a0001f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a00800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a00800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a01c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a01c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a00060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
+.*:    c4a00060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
+.*:    c4a003e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
+.*:    c4a003e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
+.*:    c4a40000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
+.*:    c4a40000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
+.*:    c4bf0000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
+.*:    c4bf0000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
+.*:    c4e00000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e00000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e00000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e00001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e00001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e00001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e0001f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e0001f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e0001f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e00800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e00800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e01c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e01c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e00060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
+.*:    c4e00060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
+.*:    c4e003e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
+.*:    c4e003e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
+.*:    c4e40000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
+.*:    c4e40000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
+.*:    c4ff0000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
+.*:    c4ff0000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
+.*:    c4c08000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c08000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c08000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c08000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c08001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c08001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c08001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c08001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0801f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0801f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0801f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0801f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c08800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4c08800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4c08800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4c09c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4c09c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4c09c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4c08060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c4c08060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c4c08060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c4c083e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c4c083e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c4c083e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c4c48000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c4c48000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c4c48000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c4df8000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c4df8000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c4df8000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c4e08000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e08000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e08000        ld1sh   \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e08001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e08001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e08001        ld1sh   \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0801f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0801f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0801f        ld1sh   \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e08800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e08800        ld1sh   \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e09c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e09c00        ld1sh   \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e08060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
+.*:    c4e08060        ld1sh   \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
+.*:    c4e083e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
+.*:    c4e083e0        ld1sh   \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
+.*:    c4e48000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
+.*:    c4e48000        ld1sh   \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
+.*:    c4ff8000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
+.*:    c4ff8000        ld1sh   \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
 .*:    84a08000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    84a08000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    84a08000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s\]
@@ -14643,14 +14643,14 @@ Disassembly of section .*:
 .*:    84a083e0        ld1sh   \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    84a083e0        ld1sh   \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    84a083e0        ld1sh   \{z0\.s\}, p0/z, \[z31\.s\]
-.*:    84af8000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s,#30\]
-.*:    84af8000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s,#30\]
-.*:    84b08000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s,#32\]
-.*:    84b08000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s,#32\]
-.*:    84b18000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s,#34\]
-.*:    84b18000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s,#34\]
-.*:    84bf8000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s,#62\]
-.*:    84bf8000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s,#62\]
+.*:    84af8000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s, #30\]
+.*:    84af8000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s, #30\]
+.*:    84b08000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s, #32\]
+.*:    84b08000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s, #32\]
+.*:    84b18000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s, #34\]
+.*:    84b18000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s, #34\]
+.*:    84bf8000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s, #62\]
+.*:    84bf8000        ld1sh   \{z0\.s\}, p0/z, \[z0\.s, #62\]
 .*:    a500a000        ld1sh   \{z0\.d\}, p0/z, \[x0\]
 .*:    a500a000        ld1sh   \{z0\.d\}, p0/z, \[x0\]
 .*:    a500a000        ld1sh   \{z0\.d\}, p0/z, \[x0\]
@@ -14682,14 +14682,14 @@ Disassembly of section .*:
 .*:    a500a3e0        ld1sh   \{z0\.d\}, p0/z, \[sp\]
 .*:    a500a3e0        ld1sh   \{z0\.d\}, p0/z, \[sp\]
 .*:    a500a3e0        ld1sh   \{z0\.d\}, p0/z, \[sp\]
-.*:    a507a000        ld1sh   \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a507a000        ld1sh   \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a508a000        ld1sh   \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a508a000        ld1sh   \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a509a000        ld1sh   \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a509a000        ld1sh   \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a50fa000        ld1sh   \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a50fa000        ld1sh   \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a507a000        ld1sh   \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a507a000        ld1sh   \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a508a000        ld1sh   \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a508a000        ld1sh   \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a509a000        ld1sh   \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a509a000        ld1sh   \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a50fa000        ld1sh   \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a50fa000        ld1sh   \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a520a000        ld1sh   \{z0\.s\}, p0/z, \[x0\]
 .*:    a520a000        ld1sh   \{z0\.s\}, p0/z, \[x0\]
 .*:    a520a000        ld1sh   \{z0\.s\}, p0/z, \[x0\]
@@ -14721,14 +14721,14 @@ Disassembly of section .*:
 .*:    a520a3e0        ld1sh   \{z0\.s\}, p0/z, \[sp\]
 .*:    a520a3e0        ld1sh   \{z0\.s\}, p0/z, \[sp\]
 .*:    a520a3e0        ld1sh   \{z0\.s\}, p0/z, \[sp\]
-.*:    a527a000        ld1sh   \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a527a000        ld1sh   \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a528a000        ld1sh   \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a528a000        ld1sh   \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a529a000        ld1sh   \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a529a000        ld1sh   \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a52fa000        ld1sh   \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a52fa000        ld1sh   \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a527a000        ld1sh   \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a527a000        ld1sh   \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a528a000        ld1sh   \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a528a000        ld1sh   \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a529a000        ld1sh   \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a529a000        ld1sh   \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a52fa000        ld1sh   \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a52fa000        ld1sh   \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
 .*:    c4a08000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c4a08000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c4a08000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d\]
@@ -14753,188 +14753,188 @@ Disassembly of section .*:
 .*:    c4a083e0        ld1sh   \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c4a083e0        ld1sh   \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c4a083e0        ld1sh   \{z0\.d\}, p0/z, \[z31\.d\]
-.*:    c4af8000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d,#30\]
-.*:    c4af8000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d,#30\]
-.*:    c4b08000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d,#32\]
-.*:    c4b08000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d,#32\]
-.*:    c4b18000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d,#34\]
-.*:    c4b18000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d,#34\]
-.*:    c4bf8000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d,#62\]
-.*:    c4bf8000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d,#62\]
-.*:    a4804000        ld1sw   \{z0\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a4804000        ld1sw   \{z0\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a4804000        ld1sw   \{z0\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a4804001        ld1sw   \{z1\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a4804001        ld1sw   \{z1\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a4804001        ld1sw   \{z1\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a480401f        ld1sw   \{z31\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a480401f        ld1sw   \{z31\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a480401f        ld1sw   \{z31\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a4804800        ld1sw   \{z0\.d\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a4804800        ld1sw   \{z0\.d\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a4805c00        ld1sw   \{z0\.d\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a4805c00        ld1sw   \{z0\.d\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a4804060        ld1sw   \{z0\.d\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a4804060        ld1sw   \{z0\.d\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a48043e0        ld1sw   \{z0\.d\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a48043e0        ld1sw   \{z0\.d\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a4844000        ld1sw   \{z0\.d\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a4844000        ld1sw   \{z0\.d\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a49e4000        ld1sw   \{z0\.d\}, p0/z, \[x0,x30,lsl #2\]
-.*:    a49e4000        ld1sw   \{z0\.d\}, p0/z, \[x0,x30,lsl #2\]
-.*:    c5000000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5000000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5000000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5000000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5000001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5000001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5000001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5000001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500001f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500001f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500001f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500001f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5000800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5000800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5000800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5001c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5001c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5001c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5000060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c5000060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c5000060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c50003e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c50003e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c50003e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c5040000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c5040000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c5040000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c51f0000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c51f0000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c51f0000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c5400000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5400000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5400000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5400000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5400001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5400001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5400001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5400001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540001f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540001f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540001f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540001f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5400800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5400800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5400800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5401c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5401c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5401c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5400060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c5400060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c5400060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c54003e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c54003e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c54003e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c5440000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c5440000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c5440000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c55f0000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c55f0000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c55f0000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c5200000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5200000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5200000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5200001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5200001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5200001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c520001f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c520001f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c520001f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5200800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5200800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5201c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5201c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5200060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\]
-.*:    c5200060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\]
-.*:    c52003e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\]
-.*:    c52003e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\]
-.*:    c5240000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\]
-.*:    c5240000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\]
-.*:    c53f0000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\]
-.*:    c53f0000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\]
-.*:    c5600000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5600000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5600000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5600001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5600001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5600001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c560001f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c560001f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c560001f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5600800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5600800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5601c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5601c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5600060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\]
-.*:    c5600060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\]
-.*:    c56003e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\]
-.*:    c56003e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\]
-.*:    c5640000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\]
-.*:    c5640000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\]
-.*:    c57f0000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\]
-.*:    c57f0000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\]
-.*:    c5408000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5408000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5408000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5408000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5408001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5408001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5408001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5408001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540801f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540801f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540801f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540801f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5408800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c5408800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c5408800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c5409c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c5409c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c5409c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c5408060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c5408060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c5408060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c54083e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c54083e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c54083e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c5448000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c5448000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c5448000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c55f8000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c55f8000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c55f8000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c5608000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c5608000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c5608000        ld1sw   \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c5608001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c5608001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c5608001        ld1sw   \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560801f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560801f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560801f        ld1sw   \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c5608800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\]
-.*:    c5608800        ld1sw   \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\]
-.*:    c5609c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\]
-.*:    c5609c00        ld1sw   \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\]
-.*:    c5608060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\]
-.*:    c5608060        ld1sw   \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\]
-.*:    c56083e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\]
-.*:    c56083e0        ld1sw   \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\]
-.*:    c5648000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\]
-.*:    c5648000        ld1sw   \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\]
-.*:    c57f8000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\]
-.*:    c57f8000        ld1sw   \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\]
+.*:    c4af8000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d, #30\]
+.*:    c4af8000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d, #30\]
+.*:    c4b08000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d, #32\]
+.*:    c4b08000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d, #32\]
+.*:    c4b18000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d, #34\]
+.*:    c4b18000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d, #34\]
+.*:    c4bf8000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d, #62\]
+.*:    c4bf8000        ld1sh   \{z0\.d\}, p0/z, \[z0\.d, #62\]
+.*:    a4804000        ld1sw   \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a4804000        ld1sw   \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a4804000        ld1sw   \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a4804001        ld1sw   \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a4804001        ld1sw   \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a4804001        ld1sw   \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a480401f        ld1sw   \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a480401f        ld1sw   \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a480401f        ld1sw   \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a4804800        ld1sw   \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a4804800        ld1sw   \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a4805c00        ld1sw   \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a4805c00        ld1sw   \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a4804060        ld1sw   \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a4804060        ld1sw   \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a48043e0        ld1sw   \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a48043e0        ld1sw   \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a4844000        ld1sw   \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a4844000        ld1sw   \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a49e4000        ld1sw   \{z0\.d\}, p0/z, \[x0, x30, lsl #2\]
+.*:    a49e4000        ld1sw   \{z0\.d\}, p0/z, \[x0, x30, lsl #2\]
+.*:    c5000000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5000000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5000000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5000000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5000001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5000001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5000001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5000001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500001f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500001f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500001f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500001f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5000800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5000800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5000800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5001c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5001c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5001c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5000060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c5000060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c5000060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c50003e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c50003e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c50003e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c5040000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c5040000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c5040000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c51f0000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c51f0000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c51f0000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c5400000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5400000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5400000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5400000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5400001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5400001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5400001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5400001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540001f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540001f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540001f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540001f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5400800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5400800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5400800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5401c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5401c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5401c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5400060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c5400060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c5400060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c54003e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c54003e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c54003e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c5440000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c5440000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c5440000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c55f0000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c55f0000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c55f0000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c5200000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5200000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5200000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5200001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5200001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5200001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c520001f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c520001f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c520001f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5200800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5200800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5201c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5201c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5200060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
+.*:    c5200060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
+.*:    c52003e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
+.*:    c52003e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
+.*:    c5240000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
+.*:    c5240000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
+.*:    c53f0000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
+.*:    c53f0000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
+.*:    c5600000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5600000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5600000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5600001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5600001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5600001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c560001f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c560001f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c560001f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5600800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5600800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5601c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5601c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5600060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
+.*:    c5600060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
+.*:    c56003e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
+.*:    c56003e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
+.*:    c5640000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
+.*:    c5640000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
+.*:    c57f0000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
+.*:    c57f0000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
+.*:    c5408000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5408000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5408000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5408000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5408001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5408001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5408001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5408001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540801f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540801f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540801f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540801f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5408800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c5408800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c5408800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c5409c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c5409c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c5409c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c5408060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c5408060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c5408060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c54083e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c54083e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c54083e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c5448000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c5448000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c5448000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c55f8000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c55f8000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c55f8000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c5608000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c5608000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c5608000        ld1sw   \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c5608001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c5608001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c5608001        ld1sw   \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560801f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560801f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560801f        ld1sw   \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c5608800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
+.*:    c5608800        ld1sw   \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
+.*:    c5609c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
+.*:    c5609c00        ld1sw   \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
+.*:    c5608060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
+.*:    c5608060        ld1sw   \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
+.*:    c56083e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
+.*:    c56083e0        ld1sw   \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
+.*:    c5648000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
+.*:    c5648000        ld1sw   \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
+.*:    c57f8000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
+.*:    c57f8000        ld1sw   \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
 .*:    a480a000        ld1sw   \{z0\.d\}, p0/z, \[x0\]
 .*:    a480a000        ld1sw   \{z0\.d\}, p0/z, \[x0\]
 .*:    a480a000        ld1sw   \{z0\.d\}, p0/z, \[x0\]
@@ -14966,14 +14966,14 @@ Disassembly of section .*:
 .*:    a480a3e0        ld1sw   \{z0\.d\}, p0/z, \[sp\]
 .*:    a480a3e0        ld1sw   \{z0\.d\}, p0/z, \[sp\]
 .*:    a480a3e0        ld1sw   \{z0\.d\}, p0/z, \[sp\]
-.*:    a487a000        ld1sw   \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a487a000        ld1sw   \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a488a000        ld1sw   \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a488a000        ld1sw   \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a489a000        ld1sw   \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a489a000        ld1sw   \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a48fa000        ld1sw   \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a48fa000        ld1sw   \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a487a000        ld1sw   \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a487a000        ld1sw   \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a488a000        ld1sw   \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a488a000        ld1sw   \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a489a000        ld1sw   \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a489a000        ld1sw   \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a48fa000        ld1sw   \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a48fa000        ld1sw   \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
 .*:    c5208000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c5208000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c5208000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d\]
@@ -14998,311 +14998,311 @@ Disassembly of section .*:
 .*:    c52083e0        ld1sw   \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c52083e0        ld1sw   \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c52083e0        ld1sw   \{z0\.d\}, p0/z, \[z31\.d\]
-.*:    c52f8000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d,#60\]
-.*:    c52f8000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d,#60\]
-.*:    c5308000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d,#64\]
-.*:    c5308000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d,#64\]
-.*:    c5318000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d,#68\]
-.*:    c5318000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d,#68\]
-.*:    c53f8000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d,#124\]
-.*:    c53f8000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d,#124\]
-.*:    85004000        ld1w    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85004000        ld1w    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85004000        ld1w    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85004000        ld1w    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85004001        ld1w    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85004001        ld1w    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85004001        ld1w    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85004001        ld1w    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8500401f        ld1w    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8500401f        ld1w    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8500401f        ld1w    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8500401f        ld1w    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85004800        ld1w    \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    85004800        ld1w    \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    85004800        ld1w    \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    85005c00        ld1w    \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    85005c00        ld1w    \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    85005c00        ld1w    \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    85004060        ld1w    \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    85004060        ld1w    \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    85004060        ld1w    \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    850043e0        ld1w    \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    850043e0        ld1w    \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    850043e0        ld1w    \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    85044000        ld1w    \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    85044000        ld1w    \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    85044000        ld1w    \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    851f4000        ld1w    \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    851f4000        ld1w    \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    851f4000        ld1w    \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    85404000        ld1w    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85404000        ld1w    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85404000        ld1w    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85404000        ld1w    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85404001        ld1w    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85404001        ld1w    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85404001        ld1w    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85404001        ld1w    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8540401f        ld1w    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8540401f        ld1w    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8540401f        ld1w    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8540401f        ld1w    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85404800        ld1w    \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    85404800        ld1w    \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    85404800        ld1w    \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    85405c00        ld1w    \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    85405c00        ld1w    \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    85405c00        ld1w    \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    85404060        ld1w    \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    85404060        ld1w    \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    85404060        ld1w    \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    854043e0        ld1w    \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    854043e0        ld1w    \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    854043e0        ld1w    \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    85444000        ld1w    \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    85444000        ld1w    \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    85444000        ld1w    \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    855f4000        ld1w    \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    855f4000        ld1w    \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    855f4000        ld1w    \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    85204000        ld1w    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    85204000        ld1w    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    85204000        ld1w    \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    85204001        ld1w    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    85204001        ld1w    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    85204001        ld1w    \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    8520401f        ld1w    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    8520401f        ld1w    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    8520401f        ld1w    \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    85204800        ld1w    \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #2\]
-.*:    85204800        ld1w    \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #2\]
-.*:    85205c00        ld1w    \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #2\]
-.*:    85205c00        ld1w    \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #2\]
-.*:    85204060        ld1w    \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #2\]
-.*:    85204060        ld1w    \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #2\]
-.*:    852043e0        ld1w    \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #2\]
-.*:    852043e0        ld1w    \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #2\]
-.*:    85244000        ld1w    \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #2\]
-.*:    85244000        ld1w    \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #2\]
-.*:    853f4000        ld1w    \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #2\]
-.*:    853f4000        ld1w    \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #2\]
-.*:    85604000        ld1w    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    85604000        ld1w    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    85604000        ld1w    \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    85604001        ld1w    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    85604001        ld1w    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    85604001        ld1w    \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    8560401f        ld1w    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    8560401f        ld1w    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    8560401f        ld1w    \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    85604800        ld1w    \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #2\]
-.*:    85604800        ld1w    \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #2\]
-.*:    85605c00        ld1w    \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #2\]
-.*:    85605c00        ld1w    \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #2\]
-.*:    85604060        ld1w    \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #2\]
-.*:    85604060        ld1w    \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #2\]
-.*:    856043e0        ld1w    \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #2\]
-.*:    856043e0        ld1w    \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #2\]
-.*:    85644000        ld1w    \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #2\]
-.*:    85644000        ld1w    \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #2\]
-.*:    857f4000        ld1w    \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #2\]
-.*:    857f4000        ld1w    \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #2\]
-.*:    a5404000        ld1w    \{z0\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5404000        ld1w    \{z0\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5404000        ld1w    \{z0\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5404001        ld1w    \{z1\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5404001        ld1w    \{z1\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5404001        ld1w    \{z1\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a540401f        ld1w    \{z31\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a540401f        ld1w    \{z31\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a540401f        ld1w    \{z31\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5404800        ld1w    \{z0\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a5404800        ld1w    \{z0\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a5405c00        ld1w    \{z0\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a5405c00        ld1w    \{z0\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a5404060        ld1w    \{z0\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a5404060        ld1w    \{z0\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a54043e0        ld1w    \{z0\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a54043e0        ld1w    \{z0\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a5444000        ld1w    \{z0\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a5444000        ld1w    \{z0\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a55e4000        ld1w    \{z0\.s\}, p0/z, \[x0,x30,lsl #2\]
-.*:    a55e4000        ld1w    \{z0\.s\}, p0/z, \[x0,x30,lsl #2\]
-.*:    a5604000        ld1w    \{z0\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5604000        ld1w    \{z0\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5604000        ld1w    \{z0\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5604001        ld1w    \{z1\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5604001        ld1w    \{z1\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5604001        ld1w    \{z1\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a560401f        ld1w    \{z31\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a560401f        ld1w    \{z31\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a560401f        ld1w    \{z31\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5604800        ld1w    \{z0\.d\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a5604800        ld1w    \{z0\.d\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a5605c00        ld1w    \{z0\.d\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a5605c00        ld1w    \{z0\.d\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a5604060        ld1w    \{z0\.d\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a5604060        ld1w    \{z0\.d\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a56043e0        ld1w    \{z0\.d\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a56043e0        ld1w    \{z0\.d\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a5644000        ld1w    \{z0\.d\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a5644000        ld1w    \{z0\.d\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a57e4000        ld1w    \{z0\.d\}, p0/z, \[x0,x30,lsl #2\]
-.*:    a57e4000        ld1w    \{z0\.d\}, p0/z, \[x0,x30,lsl #2\]
-.*:    c5004000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5004000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5004000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5004000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5004001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5004001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5004001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5004001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500401f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500401f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500401f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500401f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5004800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5004800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5004800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5005c00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5005c00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5005c00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5004060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c5004060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c5004060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c50043e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c50043e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c50043e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c5044000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c5044000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c5044000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c51f4000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c51f4000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c51f4000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c5404000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5404000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5404000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5404000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5404001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5404001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5404001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5404001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540401f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540401f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540401f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540401f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5404800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5404800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5404800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5405c00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5405c00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5405c00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5404060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c5404060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c5404060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c54043e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c54043e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c54043e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c5444000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c5444000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c5444000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c55f4000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c55f4000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c55f4000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c5204000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5204000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5204000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5204001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5204001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5204001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c520401f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c520401f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c520401f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5204800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5204800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5205c00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5205c00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5204060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\]
-.*:    c5204060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\]
-.*:    c52043e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\]
-.*:    c52043e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\]
-.*:    c5244000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\]
-.*:    c5244000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\]
-.*:    c53f4000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\]
-.*:    c53f4000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\]
-.*:    c5604000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5604000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5604000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5604001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5604001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5604001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c560401f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c560401f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c560401f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5604800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5604800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5605c00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5605c00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5604060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\]
-.*:    c5604060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\]
-.*:    c56043e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\]
-.*:    c56043e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\]
-.*:    c5644000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\]
-.*:    c5644000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\]
-.*:    c57f4000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\]
-.*:    c57f4000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\]
-.*:    c540c000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540c000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540c000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540c000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540c001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540c001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540c001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540c001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540c01f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540c01f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540c01f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540c01f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540c800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c540c800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c540c800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c540dc00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c540dc00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c540dc00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c540c060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c540c060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c540c060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c540c3e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c540c3e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c540c3e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c544c000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c544c000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c544c000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c55fc000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c55fc000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c55fc000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c560c000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560c000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560c000        ld1w    \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560c001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560c001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560c001        ld1w    \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560c01f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560c01f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560c01f        ld1w    \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560c800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\]
-.*:    c560c800        ld1w    \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\]
-.*:    c560dc00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\]
-.*:    c560dc00        ld1w    \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\]
-.*:    c560c060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\]
-.*:    c560c060        ld1w    \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\]
-.*:    c560c3e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\]
-.*:    c560c3e0        ld1w    \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\]
-.*:    c564c000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\]
-.*:    c564c000        ld1w    \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\]
-.*:    c57fc000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\]
-.*:    c57fc000        ld1w    \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\]
+.*:    c52f8000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d, #60\]
+.*:    c52f8000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d, #60\]
+.*:    c5308000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d, #64\]
+.*:    c5308000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d, #64\]
+.*:    c5318000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d, #68\]
+.*:    c5318000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d, #68\]
+.*:    c53f8000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d, #124\]
+.*:    c53f8000        ld1sw   \{z0\.d\}, p0/z, \[z0\.d, #124\]
+.*:    85004000        ld1w    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85004000        ld1w    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85004000        ld1w    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85004000        ld1w    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85004001        ld1w    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85004001        ld1w    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85004001        ld1w    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85004001        ld1w    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8500401f        ld1w    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8500401f        ld1w    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8500401f        ld1w    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8500401f        ld1w    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85004800        ld1w    \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    85004800        ld1w    \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    85004800        ld1w    \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    85005c00        ld1w    \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    85005c00        ld1w    \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    85005c00        ld1w    \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    85004060        ld1w    \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    85004060        ld1w    \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    85004060        ld1w    \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    850043e0        ld1w    \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    850043e0        ld1w    \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    850043e0        ld1w    \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    85044000        ld1w    \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    85044000        ld1w    \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    85044000        ld1w    \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    851f4000        ld1w    \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    851f4000        ld1w    \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    851f4000        ld1w    \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    85404000        ld1w    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85404000        ld1w    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85404000        ld1w    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85404000        ld1w    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85404001        ld1w    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85404001        ld1w    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85404001        ld1w    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85404001        ld1w    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8540401f        ld1w    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8540401f        ld1w    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8540401f        ld1w    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8540401f        ld1w    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85404800        ld1w    \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    85404800        ld1w    \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    85404800        ld1w    \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    85405c00        ld1w    \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    85405c00        ld1w    \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    85405c00        ld1w    \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    85404060        ld1w    \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    85404060        ld1w    \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    85404060        ld1w    \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    854043e0        ld1w    \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    854043e0        ld1w    \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    854043e0        ld1w    \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    85444000        ld1w    \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    85444000        ld1w    \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    85444000        ld1w    \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    855f4000        ld1w    \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    855f4000        ld1w    \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    855f4000        ld1w    \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    85204000        ld1w    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    85204000        ld1w    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    85204000        ld1w    \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    85204001        ld1w    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    85204001        ld1w    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    85204001        ld1w    \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    8520401f        ld1w    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    8520401f        ld1w    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    8520401f        ld1w    \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    85204800        ld1w    \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #2\]
+.*:    85204800        ld1w    \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #2\]
+.*:    85205c00        ld1w    \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #2\]
+.*:    85205c00        ld1w    \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #2\]
+.*:    85204060        ld1w    \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #2\]
+.*:    85204060        ld1w    \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #2\]
+.*:    852043e0        ld1w    \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #2\]
+.*:    852043e0        ld1w    \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #2\]
+.*:    85244000        ld1w    \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #2\]
+.*:    85244000        ld1w    \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #2\]
+.*:    853f4000        ld1w    \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #2\]
+.*:    853f4000        ld1w    \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #2\]
+.*:    85604000        ld1w    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    85604000        ld1w    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    85604000        ld1w    \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    85604001        ld1w    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    85604001        ld1w    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    85604001        ld1w    \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    8560401f        ld1w    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    8560401f        ld1w    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    8560401f        ld1w    \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    85604800        ld1w    \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #2\]
+.*:    85604800        ld1w    \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #2\]
+.*:    85605c00        ld1w    \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #2\]
+.*:    85605c00        ld1w    \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #2\]
+.*:    85604060        ld1w    \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #2\]
+.*:    85604060        ld1w    \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #2\]
+.*:    856043e0        ld1w    \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #2\]
+.*:    856043e0        ld1w    \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #2\]
+.*:    85644000        ld1w    \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #2\]
+.*:    85644000        ld1w    \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #2\]
+.*:    857f4000        ld1w    \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #2\]
+.*:    857f4000        ld1w    \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #2\]
+.*:    a5404000        ld1w    \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5404000        ld1w    \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5404000        ld1w    \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5404001        ld1w    \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5404001        ld1w    \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5404001        ld1w    \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a540401f        ld1w    \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a540401f        ld1w    \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a540401f        ld1w    \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5404800        ld1w    \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a5404800        ld1w    \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a5405c00        ld1w    \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a5405c00        ld1w    \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a5404060        ld1w    \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a5404060        ld1w    \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a54043e0        ld1w    \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a54043e0        ld1w    \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a5444000        ld1w    \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a5444000        ld1w    \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a55e4000        ld1w    \{z0\.s\}, p0/z, \[x0, x30, lsl #2\]
+.*:    a55e4000        ld1w    \{z0\.s\}, p0/z, \[x0, x30, lsl #2\]
+.*:    a5604000        ld1w    \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5604000        ld1w    \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5604000        ld1w    \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5604001        ld1w    \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5604001        ld1w    \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5604001        ld1w    \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a560401f        ld1w    \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a560401f        ld1w    \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a560401f        ld1w    \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5604800        ld1w    \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a5604800        ld1w    \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a5605c00        ld1w    \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a5605c00        ld1w    \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a5604060        ld1w    \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a5604060        ld1w    \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a56043e0        ld1w    \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a56043e0        ld1w    \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a5644000        ld1w    \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a5644000        ld1w    \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a57e4000        ld1w    \{z0\.d\}, p0/z, \[x0, x30, lsl #2\]
+.*:    a57e4000        ld1w    \{z0\.d\}, p0/z, \[x0, x30, lsl #2\]
+.*:    c5004000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5004000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5004000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5004000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5004001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5004001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5004001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5004001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500401f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500401f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500401f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500401f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5004800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5004800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5004800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5005c00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5005c00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5005c00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5004060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c5004060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c5004060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c50043e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c50043e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c50043e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c5044000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c5044000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c5044000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c51f4000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c51f4000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c51f4000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c5404000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5404000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5404000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5404000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5404001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5404001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5404001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5404001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540401f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540401f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540401f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540401f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5404800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5404800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5404800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5405c00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5405c00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5405c00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5404060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c5404060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c5404060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c54043e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c54043e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c54043e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c5444000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c5444000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c5444000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c55f4000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c55f4000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c55f4000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c5204000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5204000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5204000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5204001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5204001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5204001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c520401f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c520401f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c520401f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5204800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5204800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5205c00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5205c00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5204060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
+.*:    c5204060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
+.*:    c52043e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
+.*:    c52043e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
+.*:    c5244000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
+.*:    c5244000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
+.*:    c53f4000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
+.*:    c53f4000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
+.*:    c5604000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5604000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5604000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5604001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5604001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5604001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c560401f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c560401f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c560401f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5604800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5604800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5605c00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5605c00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5604060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
+.*:    c5604060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
+.*:    c56043e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
+.*:    c56043e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
+.*:    c5644000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
+.*:    c5644000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
+.*:    c57f4000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
+.*:    c57f4000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
+.*:    c540c000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540c000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540c000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540c000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540c001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540c001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540c001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540c001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540c01f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540c01f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540c01f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540c01f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540c800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c540c800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c540c800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c540dc00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c540dc00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c540dc00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c540c060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c540c060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c540c060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c540c3e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c540c3e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c540c3e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c544c000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c544c000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c544c000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c55fc000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c55fc000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c55fc000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c560c000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560c000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560c000        ld1w    \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560c001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560c001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560c001        ld1w    \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560c01f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560c01f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560c01f        ld1w    \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560c800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
+.*:    c560c800        ld1w    \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
+.*:    c560dc00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
+.*:    c560dc00        ld1w    \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
+.*:    c560c060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
+.*:    c560c060        ld1w    \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
+.*:    c560c3e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
+.*:    c560c3e0        ld1w    \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
+.*:    c564c000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
+.*:    c564c000        ld1w    \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
+.*:    c57fc000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
+.*:    c57fc000        ld1w    \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
 .*:    8520c000        ld1w    \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    8520c000        ld1w    \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    8520c000        ld1w    \{z0\.s\}, p0/z, \[z0\.s\]
@@ -15327,14 +15327,14 @@ Disassembly of section .*:
 .*:    8520c3e0        ld1w    \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    8520c3e0        ld1w    \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    8520c3e0        ld1w    \{z0\.s\}, p0/z, \[z31\.s\]
-.*:    852fc000        ld1w    \{z0\.s\}, p0/z, \[z0\.s,#60\]
-.*:    852fc000        ld1w    \{z0\.s\}, p0/z, \[z0\.s,#60\]
-.*:    8530c000        ld1w    \{z0\.s\}, p0/z, \[z0\.s,#64\]
-.*:    8530c000        ld1w    \{z0\.s\}, p0/z, \[z0\.s,#64\]
-.*:    8531c000        ld1w    \{z0\.s\}, p0/z, \[z0\.s,#68\]
-.*:    8531c000        ld1w    \{z0\.s\}, p0/z, \[z0\.s,#68\]
-.*:    853fc000        ld1w    \{z0\.s\}, p0/z, \[z0\.s,#124\]
-.*:    853fc000        ld1w    \{z0\.s\}, p0/z, \[z0\.s,#124\]
+.*:    852fc000        ld1w    \{z0\.s\}, p0/z, \[z0\.s, #60\]
+.*:    852fc000        ld1w    \{z0\.s\}, p0/z, \[z0\.s, #60\]
+.*:    8530c000        ld1w    \{z0\.s\}, p0/z, \[z0\.s, #64\]
+.*:    8530c000        ld1w    \{z0\.s\}, p0/z, \[z0\.s, #64\]
+.*:    8531c000        ld1w    \{z0\.s\}, p0/z, \[z0\.s, #68\]
+.*:    8531c000        ld1w    \{z0\.s\}, p0/z, \[z0\.s, #68\]
+.*:    853fc000        ld1w    \{z0\.s\}, p0/z, \[z0\.s, #124\]
+.*:    853fc000        ld1w    \{z0\.s\}, p0/z, \[z0\.s, #124\]
 .*:    a540a000        ld1w    \{z0\.s\}, p0/z, \[x0\]
 .*:    a540a000        ld1w    \{z0\.s\}, p0/z, \[x0\]
 .*:    a540a000        ld1w    \{z0\.s\}, p0/z, \[x0\]
@@ -15366,14 +15366,14 @@ Disassembly of section .*:
 .*:    a540a3e0        ld1w    \{z0\.s\}, p0/z, \[sp\]
 .*:    a540a3e0        ld1w    \{z0\.s\}, p0/z, \[sp\]
 .*:    a540a3e0        ld1w    \{z0\.s\}, p0/z, \[sp\]
-.*:    a547a000        ld1w    \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a547a000        ld1w    \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a548a000        ld1w    \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a548a000        ld1w    \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a549a000        ld1w    \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a549a000        ld1w    \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a54fa000        ld1w    \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a54fa000        ld1w    \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a547a000        ld1w    \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a547a000        ld1w    \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a548a000        ld1w    \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a548a000        ld1w    \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a549a000        ld1w    \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a549a000        ld1w    \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a54fa000        ld1w    \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a54fa000        ld1w    \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a560a000        ld1w    \{z0\.d\}, p0/z, \[x0\]
 .*:    a560a000        ld1w    \{z0\.d\}, p0/z, \[x0\]
 .*:    a560a000        ld1w    \{z0\.d\}, p0/z, \[x0\]
@@ -15405,14 +15405,14 @@ Disassembly of section .*:
 .*:    a560a3e0        ld1w    \{z0\.d\}, p0/z, \[sp\]
 .*:    a560a3e0        ld1w    \{z0\.d\}, p0/z, \[sp\]
 .*:    a560a3e0        ld1w    \{z0\.d\}, p0/z, \[sp\]
-.*:    a567a000        ld1w    \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a567a000        ld1w    \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a568a000        ld1w    \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a568a000        ld1w    \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a569a000        ld1w    \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a569a000        ld1w    \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a56fa000        ld1w    \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a56fa000        ld1w    \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a567a000        ld1w    \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a567a000        ld1w    \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a568a000        ld1w    \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a568a000        ld1w    \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a569a000        ld1w    \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a569a000        ld1w    \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a56fa000        ld1w    \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a56fa000        ld1w    \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
 .*:    c520c000        ld1w    \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c520c000        ld1w    \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c520c000        ld1w    \{z0\.d\}, p0/z, \[z0\.d\]
@@ -15437,57 +15437,57 @@ Disassembly of section .*:
 .*:    c520c3e0        ld1w    \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c520c3e0        ld1w    \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c520c3e0        ld1w    \{z0\.d\}, p0/z, \[z31\.d\]
-.*:    c52fc000        ld1w    \{z0\.d\}, p0/z, \[z0\.d,#60\]
-.*:    c52fc000        ld1w    \{z0\.d\}, p0/z, \[z0\.d,#60\]
-.*:    c530c000        ld1w    \{z0\.d\}, p0/z, \[z0\.d,#64\]
-.*:    c530c000        ld1w    \{z0\.d\}, p0/z, \[z0\.d,#64\]
-.*:    c531c000        ld1w    \{z0\.d\}, p0/z, \[z0\.d,#68\]
-.*:    c531c000        ld1w    \{z0\.d\}, p0/z, \[z0\.d,#68\]
-.*:    c53fc000        ld1w    \{z0\.d\}, p0/z, \[z0\.d,#124\]
-.*:    c53fc000        ld1w    \{z0\.d\}, p0/z, \[z0\.d,#124\]
-.*:    a420c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x0\]
-.*:    a420c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x0\]
-.*:    a420c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x0\]
-.*:    a420c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x0\]
-.*:    a420c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x0\]
-.*:    a420c001        ld2b    \{z1\.b, z2\.b\}, p0/z, \[x0,x0\]
-.*:    a420c001        ld2b    \{z1\.b, z2\.b\}, p0/z, \[x0,x0\]
-.*:    a420c001        ld2b    \{z1\.b, z2\.b\}, p0/z, \[x0,x0\]
-.*:    a420c001        ld2b    \{z1\.b, z2\.b\}, p0/z, \[x0,x0\]
-.*:    a420c001        ld2b    \{z1\.b, z2\.b\}, p0/z, \[x0,x0\]
-.*:    a420c01f        ld2b    \{z31\.b, z0\.b\}, p0/z, \[x0,x0\]
-.*:    a420c01f        ld2b    \{z31\.b, z0\.b\}, p0/z, \[x0,x0\]
-.*:    a420c01f        ld2b    \{z31\.b, z0\.b\}, p0/z, \[x0,x0\]
-.*:    a420c800        ld2b    \{z0\.b, z1\.b\}, p2/z, \[x0,x0\]
-.*:    a420c800        ld2b    \{z0\.b, z1\.b\}, p2/z, \[x0,x0\]
-.*:    a420c800        ld2b    \{z0\.b, z1\.b\}, p2/z, \[x0,x0\]
-.*:    a420c800        ld2b    \{z0\.b, z1\.b\}, p2/z, \[x0,x0\]
-.*:    a420c800        ld2b    \{z0\.b, z1\.b\}, p2/z, \[x0,x0\]
-.*:    a420dc00        ld2b    \{z0\.b, z1\.b\}, p7/z, \[x0,x0\]
-.*:    a420dc00        ld2b    \{z0\.b, z1\.b\}, p7/z, \[x0,x0\]
-.*:    a420dc00        ld2b    \{z0\.b, z1\.b\}, p7/z, \[x0,x0\]
-.*:    a420dc00        ld2b    \{z0\.b, z1\.b\}, p7/z, \[x0,x0\]
-.*:    a420dc00        ld2b    \{z0\.b, z1\.b\}, p7/z, \[x0,x0\]
-.*:    a420c060        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x3,x0\]
-.*:    a420c060        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x3,x0\]
-.*:    a420c060        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x3,x0\]
-.*:    a420c060        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x3,x0\]
-.*:    a420c060        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x3,x0\]
-.*:    a420c3e0        ld2b    \{z0\.b, z1\.b\}, p0/z, \[sp,x0\]
-.*:    a420c3e0        ld2b    \{z0\.b, z1\.b\}, p0/z, \[sp,x0\]
-.*:    a420c3e0        ld2b    \{z0\.b, z1\.b\}, p0/z, \[sp,x0\]
-.*:    a420c3e0        ld2b    \{z0\.b, z1\.b\}, p0/z, \[sp,x0\]
-.*:    a420c3e0        ld2b    \{z0\.b, z1\.b\}, p0/z, \[sp,x0\]
-.*:    a424c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x4\]
-.*:    a424c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x4\]
-.*:    a424c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x4\]
-.*:    a424c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x4\]
-.*:    a424c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x4\]
-.*:    a43ec000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x30\]
-.*:    a43ec000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x30\]
-.*:    a43ec000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x30\]
-.*:    a43ec000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x30\]
-.*:    a43ec000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,x30\]
+.*:    c52fc000        ld1w    \{z0\.d\}, p0/z, \[z0\.d, #60\]
+.*:    c52fc000        ld1w    \{z0\.d\}, p0/z, \[z0\.d, #60\]
+.*:    c530c000        ld1w    \{z0\.d\}, p0/z, \[z0\.d, #64\]
+.*:    c530c000        ld1w    \{z0\.d\}, p0/z, \[z0\.d, #64\]
+.*:    c531c000        ld1w    \{z0\.d\}, p0/z, \[z0\.d, #68\]
+.*:    c531c000        ld1w    \{z0\.d\}, p0/z, \[z0\.d, #68\]
+.*:    c53fc000        ld1w    \{z0\.d\}, p0/z, \[z0\.d, #124\]
+.*:    c53fc000        ld1w    \{z0\.d\}, p0/z, \[z0\.d, #124\]
+.*:    a420c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x0\]
+.*:    a420c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x0\]
+.*:    a420c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x0\]
+.*:    a420c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x0\]
+.*:    a420c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x0\]
+.*:    a420c001        ld2b    \{z1\.b, z2\.b\}, p0/z, \[x0, x0\]
+.*:    a420c001        ld2b    \{z1\.b, z2\.b\}, p0/z, \[x0, x0\]
+.*:    a420c001        ld2b    \{z1\.b, z2\.b\}, p0/z, \[x0, x0\]
+.*:    a420c001        ld2b    \{z1\.b, z2\.b\}, p0/z, \[x0, x0\]
+.*:    a420c001        ld2b    \{z1\.b, z2\.b\}, p0/z, \[x0, x0\]
+.*:    a420c01f        ld2b    \{z31\.b, z0\.b\}, p0/z, \[x0, x0\]
+.*:    a420c01f        ld2b    \{z31\.b, z0\.b\}, p0/z, \[x0, x0\]
+.*:    a420c01f        ld2b    \{z31\.b, z0\.b\}, p0/z, \[x0, x0\]
+.*:    a420c800        ld2b    \{z0\.b, z1\.b\}, p2/z, \[x0, x0\]
+.*:    a420c800        ld2b    \{z0\.b, z1\.b\}, p2/z, \[x0, x0\]
+.*:    a420c800        ld2b    \{z0\.b, z1\.b\}, p2/z, \[x0, x0\]
+.*:    a420c800        ld2b    \{z0\.b, z1\.b\}, p2/z, \[x0, x0\]
+.*:    a420c800        ld2b    \{z0\.b, z1\.b\}, p2/z, \[x0, x0\]
+.*:    a420dc00        ld2b    \{z0\.b, z1\.b\}, p7/z, \[x0, x0\]
+.*:    a420dc00        ld2b    \{z0\.b, z1\.b\}, p7/z, \[x0, x0\]
+.*:    a420dc00        ld2b    \{z0\.b, z1\.b\}, p7/z, \[x0, x0\]
+.*:    a420dc00        ld2b    \{z0\.b, z1\.b\}, p7/z, \[x0, x0\]
+.*:    a420dc00        ld2b    \{z0\.b, z1\.b\}, p7/z, \[x0, x0\]
+.*:    a420c060        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x3, x0\]
+.*:    a420c060        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x3, x0\]
+.*:    a420c060        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x3, x0\]
+.*:    a420c060        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x3, x0\]
+.*:    a420c060        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x3, x0\]
+.*:    a420c3e0        ld2b    \{z0\.b, z1\.b\}, p0/z, \[sp, x0\]
+.*:    a420c3e0        ld2b    \{z0\.b, z1\.b\}, p0/z, \[sp, x0\]
+.*:    a420c3e0        ld2b    \{z0\.b, z1\.b\}, p0/z, \[sp, x0\]
+.*:    a420c3e0        ld2b    \{z0\.b, z1\.b\}, p0/z, \[sp, x0\]
+.*:    a420c3e0        ld2b    \{z0\.b, z1\.b\}, p0/z, \[sp, x0\]
+.*:    a424c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x4\]
+.*:    a424c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x4\]
+.*:    a424c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x4\]
+.*:    a424c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x4\]
+.*:    a424c000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x4\]
+.*:    a43ec000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x30\]
+.*:    a43ec000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x30\]
+.*:    a43ec000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x30\]
+.*:    a43ec000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x30\]
+.*:    a43ec000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, x30\]
 .*:    a420e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0\]
 .*:    a420e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0\]
 .*:    a420e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0\]
@@ -15534,44 +15534,44 @@ Disassembly of section .*:
 .*:    a420e3e0        ld2b    \{z0\.b, z1\.b\}, p0/z, \[sp\]
 .*:    a420e3e0        ld2b    \{z0\.b, z1\.b\}, p0/z, \[sp\]
 .*:    a420e3e0        ld2b    \{z0\.b, z1\.b\}, p0/z, \[sp\]
-.*:    a427e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,#14,mul vl\]
-.*:    a427e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,#14,mul vl\]
-.*:    a427e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,#14,mul vl\]
-.*:    a428e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,#-16,mul vl\]
-.*:    a428e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,#-16,mul vl\]
-.*:    a428e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,#-16,mul vl\]
-.*:    a429e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,#-14,mul vl\]
-.*:    a429e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,#-14,mul vl\]
-.*:    a429e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,#-14,mul vl\]
-.*:    a42fe000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,#-2,mul vl\]
-.*:    a42fe000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,#-2,mul vl\]
-.*:    a42fe000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0,#-2,mul vl\]
-.*:    a5a0c000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5a0c000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5a0c000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5a0c001        ld2d    \{z1\.d, z2\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5a0c001        ld2d    \{z1\.d, z2\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5a0c001        ld2d    \{z1\.d, z2\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5a0c01f        ld2d    \{z31\.d, z0\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5a0c01f        ld2d    \{z31\.d, z0\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5a0c800        ld2d    \{z0\.d, z1\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a5a0c800        ld2d    \{z0\.d, z1\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a5a0c800        ld2d    \{z0\.d, z1\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a5a0dc00        ld2d    \{z0\.d, z1\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a5a0dc00        ld2d    \{z0\.d, z1\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a5a0dc00        ld2d    \{z0\.d, z1\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a5a0c060        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a5a0c060        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a5a0c060        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a5a0c3e0        ld2d    \{z0\.d, z1\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a5a0c3e0        ld2d    \{z0\.d, z1\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a5a0c3e0        ld2d    \{z0\.d, z1\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a5a4c000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a5a4c000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a5a4c000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a5bec000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,x30,lsl #3\]
-.*:    a5bec000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,x30,lsl #3\]
-.*:    a5bec000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,x30,lsl #3\]
+.*:    a427e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, #14, mul vl\]
+.*:    a427e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, #14, mul vl\]
+.*:    a427e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, #14, mul vl\]
+.*:    a428e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, #-16, mul vl\]
+.*:    a428e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, #-16, mul vl\]
+.*:    a428e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, #-16, mul vl\]
+.*:    a429e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, #-14, mul vl\]
+.*:    a429e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, #-14, mul vl\]
+.*:    a429e000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, #-14, mul vl\]
+.*:    a42fe000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, #-2, mul vl\]
+.*:    a42fe000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, #-2, mul vl\]
+.*:    a42fe000        ld2b    \{z0\.b, z1\.b\}, p0/z, \[x0, #-2, mul vl\]
+.*:    a5a0c000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5a0c000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5a0c000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5a0c001        ld2d    \{z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5a0c001        ld2d    \{z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5a0c001        ld2d    \{z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5a0c01f        ld2d    \{z31\.d, z0\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5a0c01f        ld2d    \{z31\.d, z0\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5a0c800        ld2d    \{z0\.d, z1\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a5a0c800        ld2d    \{z0\.d, z1\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a5a0c800        ld2d    \{z0\.d, z1\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a5a0dc00        ld2d    \{z0\.d, z1\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a5a0dc00        ld2d    \{z0\.d, z1\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a5a0dc00        ld2d    \{z0\.d, z1\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a5a0c060        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a5a0c060        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a5a0c060        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a5a0c3e0        ld2d    \{z0\.d, z1\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a5a0c3e0        ld2d    \{z0\.d, z1\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a5a0c3e0        ld2d    \{z0\.d, z1\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a5a4c000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a5a4c000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a5a4c000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a5bec000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, x30, lsl #3\]
+.*:    a5bec000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, x30, lsl #3\]
+.*:    a5bec000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, x30, lsl #3\]
 .*:    a5a0e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0\]
 .*:    a5a0e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0\]
 .*:    a5a0e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0\]
@@ -15618,44 +15618,44 @@ Disassembly of section .*:
 .*:    a5a0e3e0        ld2d    \{z0\.d, z1\.d\}, p0/z, \[sp\]
 .*:    a5a0e3e0        ld2d    \{z0\.d, z1\.d\}, p0/z, \[sp\]
 .*:    a5a0e3e0        ld2d    \{z0\.d, z1\.d\}, p0/z, \[sp\]
-.*:    a5a7e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,#14,mul vl\]
-.*:    a5a7e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,#14,mul vl\]
-.*:    a5a7e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,#14,mul vl\]
-.*:    a5a8e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,#-16,mul vl\]
-.*:    a5a8e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,#-16,mul vl\]
-.*:    a5a8e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,#-16,mul vl\]
-.*:    a5a9e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,#-14,mul vl\]
-.*:    a5a9e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,#-14,mul vl\]
-.*:    a5a9e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,#-14,mul vl\]
-.*:    a5afe000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,#-2,mul vl\]
-.*:    a5afe000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,#-2,mul vl\]
-.*:    a5afe000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0,#-2,mul vl\]
-.*:    a4a0c000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a0c000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a0c000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a0c001        ld2h    \{z1\.h, z2\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a0c001        ld2h    \{z1\.h, z2\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a0c001        ld2h    \{z1\.h, z2\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a0c01f        ld2h    \{z31\.h, z0\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a0c01f        ld2h    \{z31\.h, z0\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a0c800        ld2h    \{z0\.h, z1\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4a0c800        ld2h    \{z0\.h, z1\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4a0c800        ld2h    \{z0\.h, z1\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4a0dc00        ld2h    \{z0\.h, z1\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4a0dc00        ld2h    \{z0\.h, z1\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4a0dc00        ld2h    \{z0\.h, z1\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4a0c060        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4a0c060        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4a0c060        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4a0c3e0        ld2h    \{z0\.h, z1\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4a0c3e0        ld2h    \{z0\.h, z1\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4a0c3e0        ld2h    \{z0\.h, z1\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4a4c000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4a4c000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4a4c000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4bec000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a4bec000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a4bec000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,x30,lsl #1\]
+.*:    a5a7e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, #14, mul vl\]
+.*:    a5a7e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, #14, mul vl\]
+.*:    a5a7e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, #14, mul vl\]
+.*:    a5a8e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, #-16, mul vl\]
+.*:    a5a8e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, #-16, mul vl\]
+.*:    a5a8e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, #-16, mul vl\]
+.*:    a5a9e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, #-14, mul vl\]
+.*:    a5a9e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, #-14, mul vl\]
+.*:    a5a9e000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, #-14, mul vl\]
+.*:    a5afe000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, #-2, mul vl\]
+.*:    a5afe000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, #-2, mul vl\]
+.*:    a5afe000        ld2d    \{z0\.d, z1\.d\}, p0/z, \[x0, #-2, mul vl\]
+.*:    a4a0c000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a0c000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a0c000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a0c001        ld2h    \{z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a0c001        ld2h    \{z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a0c001        ld2h    \{z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a0c01f        ld2h    \{z31\.h, z0\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a0c01f        ld2h    \{z31\.h, z0\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a0c800        ld2h    \{z0\.h, z1\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4a0c800        ld2h    \{z0\.h, z1\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4a0c800        ld2h    \{z0\.h, z1\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4a0dc00        ld2h    \{z0\.h, z1\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4a0dc00        ld2h    \{z0\.h, z1\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4a0dc00        ld2h    \{z0\.h, z1\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4a0c060        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4a0c060        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4a0c060        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4a0c3e0        ld2h    \{z0\.h, z1\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4a0c3e0        ld2h    \{z0\.h, z1\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4a0c3e0        ld2h    \{z0\.h, z1\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4a4c000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4a4c000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4a4c000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4bec000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a4bec000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a4bec000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, x30, lsl #1\]
 .*:    a4a0e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0\]
 .*:    a4a0e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0\]
 .*:    a4a0e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0\]
@@ -15702,44 +15702,44 @@ Disassembly of section .*:
 .*:    a4a0e3e0        ld2h    \{z0\.h, z1\.h\}, p0/z, \[sp\]
 .*:    a4a0e3e0        ld2h    \{z0\.h, z1\.h\}, p0/z, \[sp\]
 .*:    a4a0e3e0        ld2h    \{z0\.h, z1\.h\}, p0/z, \[sp\]
-.*:    a4a7e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,#14,mul vl\]
-.*:    a4a7e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,#14,mul vl\]
-.*:    a4a7e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,#14,mul vl\]
-.*:    a4a8e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,#-16,mul vl\]
-.*:    a4a8e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,#-16,mul vl\]
-.*:    a4a8e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,#-16,mul vl\]
-.*:    a4a9e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,#-14,mul vl\]
-.*:    a4a9e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,#-14,mul vl\]
-.*:    a4a9e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,#-14,mul vl\]
-.*:    a4afe000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,#-2,mul vl\]
-.*:    a4afe000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,#-2,mul vl\]
-.*:    a4afe000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0,#-2,mul vl\]
-.*:    a520c000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a520c000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a520c000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a520c001        ld2w    \{z1\.s, z2\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a520c001        ld2w    \{z1\.s, z2\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a520c001        ld2w    \{z1\.s, z2\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a520c01f        ld2w    \{z31\.s, z0\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a520c01f        ld2w    \{z31\.s, z0\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a520c800        ld2w    \{z0\.s, z1\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a520c800        ld2w    \{z0\.s, z1\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a520c800        ld2w    \{z0\.s, z1\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a520dc00        ld2w    \{z0\.s, z1\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a520dc00        ld2w    \{z0\.s, z1\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a520dc00        ld2w    \{z0\.s, z1\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a520c060        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a520c060        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a520c060        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a520c3e0        ld2w    \{z0\.s, z1\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a520c3e0        ld2w    \{z0\.s, z1\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a520c3e0        ld2w    \{z0\.s, z1\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a524c000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a524c000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a524c000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a53ec000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,x30,lsl #2\]
-.*:    a53ec000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,x30,lsl #2\]
-.*:    a53ec000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,x30,lsl #2\]
+.*:    a4a7e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, #14, mul vl\]
+.*:    a4a7e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, #14, mul vl\]
+.*:    a4a7e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, #14, mul vl\]
+.*:    a4a8e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, #-16, mul vl\]
+.*:    a4a8e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, #-16, mul vl\]
+.*:    a4a8e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, #-16, mul vl\]
+.*:    a4a9e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, #-14, mul vl\]
+.*:    a4a9e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, #-14, mul vl\]
+.*:    a4a9e000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, #-14, mul vl\]
+.*:    a4afe000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, #-2, mul vl\]
+.*:    a4afe000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, #-2, mul vl\]
+.*:    a4afe000        ld2h    \{z0\.h, z1\.h\}, p0/z, \[x0, #-2, mul vl\]
+.*:    a520c000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a520c000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a520c000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a520c001        ld2w    \{z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a520c001        ld2w    \{z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a520c001        ld2w    \{z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a520c01f        ld2w    \{z31\.s, z0\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a520c01f        ld2w    \{z31\.s, z0\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a520c800        ld2w    \{z0\.s, z1\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a520c800        ld2w    \{z0\.s, z1\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a520c800        ld2w    \{z0\.s, z1\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a520dc00        ld2w    \{z0\.s, z1\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a520dc00        ld2w    \{z0\.s, z1\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a520dc00        ld2w    \{z0\.s, z1\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a520c060        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a520c060        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a520c060        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a520c3e0        ld2w    \{z0\.s, z1\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a520c3e0        ld2w    \{z0\.s, z1\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a520c3e0        ld2w    \{z0\.s, z1\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a524c000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a524c000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a524c000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a53ec000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, x30, lsl #2\]
+.*:    a53ec000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, x30, lsl #2\]
+.*:    a53ec000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, x30, lsl #2\]
 .*:    a520e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0\]
 .*:    a520e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0\]
 .*:    a520e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0\]
@@ -15786,61 +15786,61 @@ Disassembly of section .*:
 .*:    a520e3e0        ld2w    \{z0\.s, z1\.s\}, p0/z, \[sp\]
 .*:    a520e3e0        ld2w    \{z0\.s, z1\.s\}, p0/z, \[sp\]
 .*:    a520e3e0        ld2w    \{z0\.s, z1\.s\}, p0/z, \[sp\]
-.*:    a527e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,#14,mul vl\]
-.*:    a527e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,#14,mul vl\]
-.*:    a527e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,#14,mul vl\]
-.*:    a528e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,#-16,mul vl\]
-.*:    a528e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,#-16,mul vl\]
-.*:    a528e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,#-16,mul vl\]
-.*:    a529e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,#-14,mul vl\]
-.*:    a529e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,#-14,mul vl\]
-.*:    a529e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,#-14,mul vl\]
-.*:    a52fe000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,#-2,mul vl\]
-.*:    a52fe000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,#-2,mul vl\]
-.*:    a52fe000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0,#-2,mul vl\]
-.*:    a440c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x0\]
-.*:    a440c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x0\]
-.*:    a440c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x0\]
-.*:    a440c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x0\]
-.*:    a440c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x0\]
-.*:    a440c001        ld3b    \{z1\.b-z3\.b\}, p0/z, \[x0,x0\]
-.*:    a440c001        ld3b    \{z1\.b-z3\.b\}, p0/z, \[x0,x0\]
-.*:    a440c001        ld3b    \{z1\.b-z3\.b\}, p0/z, \[x0,x0\]
-.*:    a440c001        ld3b    \{z1\.b-z3\.b\}, p0/z, \[x0,x0\]
-.*:    a440c001        ld3b    \{z1\.b-z3\.b\}, p0/z, \[x0,x0\]
-.*:    a440c01f        ld3b    \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0,x0\]
-.*:    a440c01f        ld3b    \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0,x0\]
-.*:    a440c01f        ld3b    \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0,x0\]
-.*:    a440c800        ld3b    \{z0\.b-z2\.b\}, p2/z, \[x0,x0\]
-.*:    a440c800        ld3b    \{z0\.b-z2\.b\}, p2/z, \[x0,x0\]
-.*:    a440c800        ld3b    \{z0\.b-z2\.b\}, p2/z, \[x0,x0\]
-.*:    a440c800        ld3b    \{z0\.b-z2\.b\}, p2/z, \[x0,x0\]
-.*:    a440c800        ld3b    \{z0\.b-z2\.b\}, p2/z, \[x0,x0\]
-.*:    a440dc00        ld3b    \{z0\.b-z2\.b\}, p7/z, \[x0,x0\]
-.*:    a440dc00        ld3b    \{z0\.b-z2\.b\}, p7/z, \[x0,x0\]
-.*:    a440dc00        ld3b    \{z0\.b-z2\.b\}, p7/z, \[x0,x0\]
-.*:    a440dc00        ld3b    \{z0\.b-z2\.b\}, p7/z, \[x0,x0\]
-.*:    a440dc00        ld3b    \{z0\.b-z2\.b\}, p7/z, \[x0,x0\]
-.*:    a440c060        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x3,x0\]
-.*:    a440c060        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x3,x0\]
-.*:    a440c060        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x3,x0\]
-.*:    a440c060        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x3,x0\]
-.*:    a440c060        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x3,x0\]
-.*:    a440c3e0        ld3b    \{z0\.b-z2\.b\}, p0/z, \[sp,x0\]
-.*:    a440c3e0        ld3b    \{z0\.b-z2\.b\}, p0/z, \[sp,x0\]
-.*:    a440c3e0        ld3b    \{z0\.b-z2\.b\}, p0/z, \[sp,x0\]
-.*:    a440c3e0        ld3b    \{z0\.b-z2\.b\}, p0/z, \[sp,x0\]
-.*:    a440c3e0        ld3b    \{z0\.b-z2\.b\}, p0/z, \[sp,x0\]
-.*:    a444c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x4\]
-.*:    a444c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x4\]
-.*:    a444c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x4\]
-.*:    a444c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x4\]
-.*:    a444c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x4\]
-.*:    a45ec000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x30\]
-.*:    a45ec000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x30\]
-.*:    a45ec000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x30\]
-.*:    a45ec000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x30\]
-.*:    a45ec000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,x30\]
+.*:    a527e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, #14, mul vl\]
+.*:    a527e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, #14, mul vl\]
+.*:    a527e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, #14, mul vl\]
+.*:    a528e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, #-16, mul vl\]
+.*:    a528e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, #-16, mul vl\]
+.*:    a528e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, #-16, mul vl\]
+.*:    a529e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, #-14, mul vl\]
+.*:    a529e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, #-14, mul vl\]
+.*:    a529e000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, #-14, mul vl\]
+.*:    a52fe000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, #-2, mul vl\]
+.*:    a52fe000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, #-2, mul vl\]
+.*:    a52fe000        ld2w    \{z0\.s, z1\.s\}, p0/z, \[x0, #-2, mul vl\]
+.*:    a440c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x0\]
+.*:    a440c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x0\]
+.*:    a440c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x0\]
+.*:    a440c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x0\]
+.*:    a440c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x0\]
+.*:    a440c001        ld3b    \{z1\.b-z3\.b\}, p0/z, \[x0, x0\]
+.*:    a440c001        ld3b    \{z1\.b-z3\.b\}, p0/z, \[x0, x0\]
+.*:    a440c001        ld3b    \{z1\.b-z3\.b\}, p0/z, \[x0, x0\]
+.*:    a440c001        ld3b    \{z1\.b-z3\.b\}, p0/z, \[x0, x0\]
+.*:    a440c001        ld3b    \{z1\.b-z3\.b\}, p0/z, \[x0, x0\]
+.*:    a440c01f        ld3b    \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0, x0\]
+.*:    a440c01f        ld3b    \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0, x0\]
+.*:    a440c01f        ld3b    \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0, x0\]
+.*:    a440c800        ld3b    \{z0\.b-z2\.b\}, p2/z, \[x0, x0\]
+.*:    a440c800        ld3b    \{z0\.b-z2\.b\}, p2/z, \[x0, x0\]
+.*:    a440c800        ld3b    \{z0\.b-z2\.b\}, p2/z, \[x0, x0\]
+.*:    a440c800        ld3b    \{z0\.b-z2\.b\}, p2/z, \[x0, x0\]
+.*:    a440c800        ld3b    \{z0\.b-z2\.b\}, p2/z, \[x0, x0\]
+.*:    a440dc00        ld3b    \{z0\.b-z2\.b\}, p7/z, \[x0, x0\]
+.*:    a440dc00        ld3b    \{z0\.b-z2\.b\}, p7/z, \[x0, x0\]
+.*:    a440dc00        ld3b    \{z0\.b-z2\.b\}, p7/z, \[x0, x0\]
+.*:    a440dc00        ld3b    \{z0\.b-z2\.b\}, p7/z, \[x0, x0\]
+.*:    a440dc00        ld3b    \{z0\.b-z2\.b\}, p7/z, \[x0, x0\]
+.*:    a440c060        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x3, x0\]
+.*:    a440c060        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x3, x0\]
+.*:    a440c060        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x3, x0\]
+.*:    a440c060        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x3, x0\]
+.*:    a440c060        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x3, x0\]
+.*:    a440c3e0        ld3b    \{z0\.b-z2\.b\}, p0/z, \[sp, x0\]
+.*:    a440c3e0        ld3b    \{z0\.b-z2\.b\}, p0/z, \[sp, x0\]
+.*:    a440c3e0        ld3b    \{z0\.b-z2\.b\}, p0/z, \[sp, x0\]
+.*:    a440c3e0        ld3b    \{z0\.b-z2\.b\}, p0/z, \[sp, x0\]
+.*:    a440c3e0        ld3b    \{z0\.b-z2\.b\}, p0/z, \[sp, x0\]
+.*:    a444c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x4\]
+.*:    a444c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x4\]
+.*:    a444c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x4\]
+.*:    a444c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x4\]
+.*:    a444c000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x4\]
+.*:    a45ec000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x30\]
+.*:    a45ec000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x30\]
+.*:    a45ec000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x30\]
+.*:    a45ec000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x30\]
+.*:    a45ec000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, x30\]
 .*:    a440e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0\]
 .*:    a440e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0\]
 .*:    a440e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0\]
@@ -15887,44 +15887,44 @@ Disassembly of section .*:
 .*:    a440e3e0        ld3b    \{z0\.b-z2\.b\}, p0/z, \[sp\]
 .*:    a440e3e0        ld3b    \{z0\.b-z2\.b\}, p0/z, \[sp\]
 .*:    a440e3e0        ld3b    \{z0\.b-z2\.b\}, p0/z, \[sp\]
-.*:    a447e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,#21,mul vl\]
-.*:    a447e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,#21,mul vl\]
-.*:    a447e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,#21,mul vl\]
-.*:    a448e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,#-24,mul vl\]
-.*:    a448e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,#-24,mul vl\]
-.*:    a448e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,#-24,mul vl\]
-.*:    a449e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,#-21,mul vl\]
-.*:    a449e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,#-21,mul vl\]
-.*:    a449e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,#-21,mul vl\]
-.*:    a44fe000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,#-3,mul vl\]
-.*:    a44fe000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,#-3,mul vl\]
-.*:    a44fe000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0,#-3,mul vl\]
-.*:    a5c0c000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5c0c000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5c0c000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5c0c001        ld3d    \{z1\.d-z3\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5c0c001        ld3d    \{z1\.d-z3\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5c0c001        ld3d    \{z1\.d-z3\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5c0c01f        ld3d    \{z31\.d, z0\.d, z1\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5c0c01f        ld3d    \{z31\.d, z0\.d, z1\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5c0c800        ld3d    \{z0\.d-z2\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a5c0c800        ld3d    \{z0\.d-z2\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a5c0c800        ld3d    \{z0\.d-z2\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a5c0dc00        ld3d    \{z0\.d-z2\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a5c0dc00        ld3d    \{z0\.d-z2\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a5c0dc00        ld3d    \{z0\.d-z2\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a5c0c060        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a5c0c060        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a5c0c060        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a5c0c3e0        ld3d    \{z0\.d-z2\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a5c0c3e0        ld3d    \{z0\.d-z2\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a5c0c3e0        ld3d    \{z0\.d-z2\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a5c4c000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a5c4c000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a5c4c000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a5dec000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,x30,lsl #3\]
-.*:    a5dec000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,x30,lsl #3\]
-.*:    a5dec000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,x30,lsl #3\]
+.*:    a447e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, #21, mul vl\]
+.*:    a447e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, #21, mul vl\]
+.*:    a447e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, #21, mul vl\]
+.*:    a448e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, #-24, mul vl\]
+.*:    a448e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, #-24, mul vl\]
+.*:    a448e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, #-24, mul vl\]
+.*:    a449e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, #-21, mul vl\]
+.*:    a449e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, #-21, mul vl\]
+.*:    a449e000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, #-21, mul vl\]
+.*:    a44fe000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, #-3, mul vl\]
+.*:    a44fe000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, #-3, mul vl\]
+.*:    a44fe000        ld3b    \{z0\.b-z2\.b\}, p0/z, \[x0, #-3, mul vl\]
+.*:    a5c0c000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5c0c000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5c0c000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5c0c001        ld3d    \{z1\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5c0c001        ld3d    \{z1\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5c0c001        ld3d    \{z1\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5c0c01f        ld3d    \{z31\.d, z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5c0c01f        ld3d    \{z31\.d, z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5c0c800        ld3d    \{z0\.d-z2\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a5c0c800        ld3d    \{z0\.d-z2\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a5c0c800        ld3d    \{z0\.d-z2\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a5c0dc00        ld3d    \{z0\.d-z2\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a5c0dc00        ld3d    \{z0\.d-z2\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a5c0dc00        ld3d    \{z0\.d-z2\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a5c0c060        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a5c0c060        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a5c0c060        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a5c0c3e0        ld3d    \{z0\.d-z2\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a5c0c3e0        ld3d    \{z0\.d-z2\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a5c0c3e0        ld3d    \{z0\.d-z2\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a5c4c000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a5c4c000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a5c4c000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a5dec000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, x30, lsl #3\]
+.*:    a5dec000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, x30, lsl #3\]
+.*:    a5dec000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, x30, lsl #3\]
 .*:    a5c0e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0\]
 .*:    a5c0e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0\]
 .*:    a5c0e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0\]
@@ -15971,44 +15971,44 @@ Disassembly of section .*:
 .*:    a5c0e3e0        ld3d    \{z0\.d-z2\.d\}, p0/z, \[sp\]
 .*:    a5c0e3e0        ld3d    \{z0\.d-z2\.d\}, p0/z, \[sp\]
 .*:    a5c0e3e0        ld3d    \{z0\.d-z2\.d\}, p0/z, \[sp\]
-.*:    a5c7e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,#21,mul vl\]
-.*:    a5c7e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,#21,mul vl\]
-.*:    a5c7e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,#21,mul vl\]
-.*:    a5c8e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,#-24,mul vl\]
-.*:    a5c8e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,#-24,mul vl\]
-.*:    a5c8e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,#-24,mul vl\]
-.*:    a5c9e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,#-21,mul vl\]
-.*:    a5c9e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,#-21,mul vl\]
-.*:    a5c9e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,#-21,mul vl\]
-.*:    a5cfe000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,#-3,mul vl\]
-.*:    a5cfe000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,#-3,mul vl\]
-.*:    a5cfe000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0,#-3,mul vl\]
-.*:    a4c0c000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c0c000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c0c000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c0c001        ld3h    \{z1\.h-z3\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c0c001        ld3h    \{z1\.h-z3\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c0c001        ld3h    \{z1\.h-z3\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c0c01f        ld3h    \{z31\.h, z0\.h, z1\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c0c01f        ld3h    \{z31\.h, z0\.h, z1\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c0c800        ld3h    \{z0\.h-z2\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4c0c800        ld3h    \{z0\.h-z2\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4c0c800        ld3h    \{z0\.h-z2\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4c0dc00        ld3h    \{z0\.h-z2\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4c0dc00        ld3h    \{z0\.h-z2\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4c0dc00        ld3h    \{z0\.h-z2\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4c0c060        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4c0c060        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4c0c060        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4c0c3e0        ld3h    \{z0\.h-z2\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4c0c3e0        ld3h    \{z0\.h-z2\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4c0c3e0        ld3h    \{z0\.h-z2\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4c4c000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4c4c000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4c4c000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4dec000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a4dec000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a4dec000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,x30,lsl #1\]
+.*:    a5c7e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, #21, mul vl\]
+.*:    a5c7e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, #21, mul vl\]
+.*:    a5c7e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, #21, mul vl\]
+.*:    a5c8e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, #-24, mul vl\]
+.*:    a5c8e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, #-24, mul vl\]
+.*:    a5c8e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, #-24, mul vl\]
+.*:    a5c9e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, #-21, mul vl\]
+.*:    a5c9e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, #-21, mul vl\]
+.*:    a5c9e000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, #-21, mul vl\]
+.*:    a5cfe000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, #-3, mul vl\]
+.*:    a5cfe000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, #-3, mul vl\]
+.*:    a5cfe000        ld3d    \{z0\.d-z2\.d\}, p0/z, \[x0, #-3, mul vl\]
+.*:    a4c0c000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c0c000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c0c000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c0c001        ld3h    \{z1\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c0c001        ld3h    \{z1\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c0c001        ld3h    \{z1\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c0c01f        ld3h    \{z31\.h, z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c0c01f        ld3h    \{z31\.h, z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c0c800        ld3h    \{z0\.h-z2\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4c0c800        ld3h    \{z0\.h-z2\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4c0c800        ld3h    \{z0\.h-z2\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4c0dc00        ld3h    \{z0\.h-z2\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4c0dc00        ld3h    \{z0\.h-z2\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4c0dc00        ld3h    \{z0\.h-z2\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4c0c060        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4c0c060        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4c0c060        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4c0c3e0        ld3h    \{z0\.h-z2\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4c0c3e0        ld3h    \{z0\.h-z2\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4c0c3e0        ld3h    \{z0\.h-z2\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4c4c000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4c4c000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4c4c000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4dec000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a4dec000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a4dec000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, x30, lsl #1\]
 .*:    a4c0e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0\]
 .*:    a4c0e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0\]
 .*:    a4c0e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0\]
@@ -16055,44 +16055,44 @@ Disassembly of section .*:
 .*:    a4c0e3e0        ld3h    \{z0\.h-z2\.h\}, p0/z, \[sp\]
 .*:    a4c0e3e0        ld3h    \{z0\.h-z2\.h\}, p0/z, \[sp\]
 .*:    a4c0e3e0        ld3h    \{z0\.h-z2\.h\}, p0/z, \[sp\]
-.*:    a4c7e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,#21,mul vl\]
-.*:    a4c7e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,#21,mul vl\]
-.*:    a4c7e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,#21,mul vl\]
-.*:    a4c8e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,#-24,mul vl\]
-.*:    a4c8e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,#-24,mul vl\]
-.*:    a4c8e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,#-24,mul vl\]
-.*:    a4c9e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,#-21,mul vl\]
-.*:    a4c9e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,#-21,mul vl\]
-.*:    a4c9e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,#-21,mul vl\]
-.*:    a4cfe000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,#-3,mul vl\]
-.*:    a4cfe000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,#-3,mul vl\]
-.*:    a4cfe000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0,#-3,mul vl\]
-.*:    a540c000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a540c000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a540c000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a540c001        ld3w    \{z1\.s-z3\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a540c001        ld3w    \{z1\.s-z3\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a540c001        ld3w    \{z1\.s-z3\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a540c01f        ld3w    \{z31\.s, z0\.s, z1\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a540c01f        ld3w    \{z31\.s, z0\.s, z1\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a540c800        ld3w    \{z0\.s-z2\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a540c800        ld3w    \{z0\.s-z2\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a540c800        ld3w    \{z0\.s-z2\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a540dc00        ld3w    \{z0\.s-z2\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a540dc00        ld3w    \{z0\.s-z2\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a540dc00        ld3w    \{z0\.s-z2\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a540c060        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a540c060        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a540c060        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a540c3e0        ld3w    \{z0\.s-z2\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a540c3e0        ld3w    \{z0\.s-z2\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a540c3e0        ld3w    \{z0\.s-z2\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a544c000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a544c000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a544c000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a55ec000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,x30,lsl #2\]
-.*:    a55ec000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,x30,lsl #2\]
-.*:    a55ec000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,x30,lsl #2\]
+.*:    a4c7e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, #21, mul vl\]
+.*:    a4c7e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, #21, mul vl\]
+.*:    a4c7e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, #21, mul vl\]
+.*:    a4c8e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, #-24, mul vl\]
+.*:    a4c8e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, #-24, mul vl\]
+.*:    a4c8e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, #-24, mul vl\]
+.*:    a4c9e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, #-21, mul vl\]
+.*:    a4c9e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, #-21, mul vl\]
+.*:    a4c9e000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, #-21, mul vl\]
+.*:    a4cfe000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, #-3, mul vl\]
+.*:    a4cfe000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, #-3, mul vl\]
+.*:    a4cfe000        ld3h    \{z0\.h-z2\.h\}, p0/z, \[x0, #-3, mul vl\]
+.*:    a540c000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a540c000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a540c000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a540c001        ld3w    \{z1\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a540c001        ld3w    \{z1\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a540c001        ld3w    \{z1\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a540c01f        ld3w    \{z31\.s, z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a540c01f        ld3w    \{z31\.s, z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a540c800        ld3w    \{z0\.s-z2\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a540c800        ld3w    \{z0\.s-z2\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a540c800        ld3w    \{z0\.s-z2\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a540dc00        ld3w    \{z0\.s-z2\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a540dc00        ld3w    \{z0\.s-z2\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a540dc00        ld3w    \{z0\.s-z2\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a540c060        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a540c060        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a540c060        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a540c3e0        ld3w    \{z0\.s-z2\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a540c3e0        ld3w    \{z0\.s-z2\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a540c3e0        ld3w    \{z0\.s-z2\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a544c000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a544c000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a544c000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a55ec000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, x30, lsl #2\]
+.*:    a55ec000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, x30, lsl #2\]
+.*:    a55ec000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, x30, lsl #2\]
 .*:    a540e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0\]
 .*:    a540e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0\]
 .*:    a540e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0\]
@@ -16139,61 +16139,61 @@ Disassembly of section .*:
 .*:    a540e3e0        ld3w    \{z0\.s-z2\.s\}, p0/z, \[sp\]
 .*:    a540e3e0        ld3w    \{z0\.s-z2\.s\}, p0/z, \[sp\]
 .*:    a540e3e0        ld3w    \{z0\.s-z2\.s\}, p0/z, \[sp\]
-.*:    a547e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,#21,mul vl\]
-.*:    a547e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,#21,mul vl\]
-.*:    a547e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,#21,mul vl\]
-.*:    a548e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,#-24,mul vl\]
-.*:    a548e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,#-24,mul vl\]
-.*:    a548e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,#-24,mul vl\]
-.*:    a549e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,#-21,mul vl\]
-.*:    a549e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,#-21,mul vl\]
-.*:    a549e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,#-21,mul vl\]
-.*:    a54fe000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,#-3,mul vl\]
-.*:    a54fe000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,#-3,mul vl\]
-.*:    a54fe000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0,#-3,mul vl\]
-.*:    a460c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x0\]
-.*:    a460c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x0\]
-.*:    a460c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x0\]
-.*:    a460c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x0\]
-.*:    a460c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x0\]
-.*:    a460c001        ld4b    \{z1\.b-z4\.b\}, p0/z, \[x0,x0\]
-.*:    a460c001        ld4b    \{z1\.b-z4\.b\}, p0/z, \[x0,x0\]
-.*:    a460c001        ld4b    \{z1\.b-z4\.b\}, p0/z, \[x0,x0\]
-.*:    a460c001        ld4b    \{z1\.b-z4\.b\}, p0/z, \[x0,x0\]
-.*:    a460c001        ld4b    \{z1\.b-z4\.b\}, p0/z, \[x0,x0\]
-.*:    a460c01f        ld4b    \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0,x0\]
-.*:    a460c01f        ld4b    \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0,x0\]
-.*:    a460c01f        ld4b    \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0,x0\]
-.*:    a460c800        ld4b    \{z0\.b-z3\.b\}, p2/z, \[x0,x0\]
-.*:    a460c800        ld4b    \{z0\.b-z3\.b\}, p2/z, \[x0,x0\]
-.*:    a460c800        ld4b    \{z0\.b-z3\.b\}, p2/z, \[x0,x0\]
-.*:    a460c800        ld4b    \{z0\.b-z3\.b\}, p2/z, \[x0,x0\]
-.*:    a460c800        ld4b    \{z0\.b-z3\.b\}, p2/z, \[x0,x0\]
-.*:    a460dc00        ld4b    \{z0\.b-z3\.b\}, p7/z, \[x0,x0\]
-.*:    a460dc00        ld4b    \{z0\.b-z3\.b\}, p7/z, \[x0,x0\]
-.*:    a460dc00        ld4b    \{z0\.b-z3\.b\}, p7/z, \[x0,x0\]
-.*:    a460dc00        ld4b    \{z0\.b-z3\.b\}, p7/z, \[x0,x0\]
-.*:    a460dc00        ld4b    \{z0\.b-z3\.b\}, p7/z, \[x0,x0\]
-.*:    a460c060        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x3,x0\]
-.*:    a460c060        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x3,x0\]
-.*:    a460c060        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x3,x0\]
-.*:    a460c060        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x3,x0\]
-.*:    a460c060        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x3,x0\]
-.*:    a460c3e0        ld4b    \{z0\.b-z3\.b\}, p0/z, \[sp,x0\]
-.*:    a460c3e0        ld4b    \{z0\.b-z3\.b\}, p0/z, \[sp,x0\]
-.*:    a460c3e0        ld4b    \{z0\.b-z3\.b\}, p0/z, \[sp,x0\]
-.*:    a460c3e0        ld4b    \{z0\.b-z3\.b\}, p0/z, \[sp,x0\]
-.*:    a460c3e0        ld4b    \{z0\.b-z3\.b\}, p0/z, \[sp,x0\]
-.*:    a464c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x4\]
-.*:    a464c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x4\]
-.*:    a464c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x4\]
-.*:    a464c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x4\]
-.*:    a464c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x4\]
-.*:    a47ec000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x30\]
-.*:    a47ec000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x30\]
-.*:    a47ec000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x30\]
-.*:    a47ec000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x30\]
-.*:    a47ec000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,x30\]
+.*:    a547e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, #21, mul vl\]
+.*:    a547e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, #21, mul vl\]
+.*:    a547e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, #21, mul vl\]
+.*:    a548e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, #-24, mul vl\]
+.*:    a548e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, #-24, mul vl\]
+.*:    a548e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, #-24, mul vl\]
+.*:    a549e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, #-21, mul vl\]
+.*:    a549e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, #-21, mul vl\]
+.*:    a549e000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, #-21, mul vl\]
+.*:    a54fe000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, #-3, mul vl\]
+.*:    a54fe000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, #-3, mul vl\]
+.*:    a54fe000        ld3w    \{z0\.s-z2\.s\}, p0/z, \[x0, #-3, mul vl\]
+.*:    a460c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x0\]
+.*:    a460c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x0\]
+.*:    a460c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x0\]
+.*:    a460c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x0\]
+.*:    a460c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x0\]
+.*:    a460c001        ld4b    \{z1\.b-z4\.b\}, p0/z, \[x0, x0\]
+.*:    a460c001        ld4b    \{z1\.b-z4\.b\}, p0/z, \[x0, x0\]
+.*:    a460c001        ld4b    \{z1\.b-z4\.b\}, p0/z, \[x0, x0\]
+.*:    a460c001        ld4b    \{z1\.b-z4\.b\}, p0/z, \[x0, x0\]
+.*:    a460c001        ld4b    \{z1\.b-z4\.b\}, p0/z, \[x0, x0\]
+.*:    a460c01f        ld4b    \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0, x0\]
+.*:    a460c01f        ld4b    \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0, x0\]
+.*:    a460c01f        ld4b    \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0, x0\]
+.*:    a460c800        ld4b    \{z0\.b-z3\.b\}, p2/z, \[x0, x0\]
+.*:    a460c800        ld4b    \{z0\.b-z3\.b\}, p2/z, \[x0, x0\]
+.*:    a460c800        ld4b    \{z0\.b-z3\.b\}, p2/z, \[x0, x0\]
+.*:    a460c800        ld4b    \{z0\.b-z3\.b\}, p2/z, \[x0, x0\]
+.*:    a460c800        ld4b    \{z0\.b-z3\.b\}, p2/z, \[x0, x0\]
+.*:    a460dc00        ld4b    \{z0\.b-z3\.b\}, p7/z, \[x0, x0\]
+.*:    a460dc00        ld4b    \{z0\.b-z3\.b\}, p7/z, \[x0, x0\]
+.*:    a460dc00        ld4b    \{z0\.b-z3\.b\}, p7/z, \[x0, x0\]
+.*:    a460dc00        ld4b    \{z0\.b-z3\.b\}, p7/z, \[x0, x0\]
+.*:    a460dc00        ld4b    \{z0\.b-z3\.b\}, p7/z, \[x0, x0\]
+.*:    a460c060        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x3, x0\]
+.*:    a460c060        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x3, x0\]
+.*:    a460c060        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x3, x0\]
+.*:    a460c060        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x3, x0\]
+.*:    a460c060        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x3, x0\]
+.*:    a460c3e0        ld4b    \{z0\.b-z3\.b\}, p0/z, \[sp, x0\]
+.*:    a460c3e0        ld4b    \{z0\.b-z3\.b\}, p0/z, \[sp, x0\]
+.*:    a460c3e0        ld4b    \{z0\.b-z3\.b\}, p0/z, \[sp, x0\]
+.*:    a460c3e0        ld4b    \{z0\.b-z3\.b\}, p0/z, \[sp, x0\]
+.*:    a460c3e0        ld4b    \{z0\.b-z3\.b\}, p0/z, \[sp, x0\]
+.*:    a464c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x4\]
+.*:    a464c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x4\]
+.*:    a464c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x4\]
+.*:    a464c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x4\]
+.*:    a464c000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x4\]
+.*:    a47ec000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x30\]
+.*:    a47ec000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x30\]
+.*:    a47ec000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x30\]
+.*:    a47ec000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x30\]
+.*:    a47ec000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, x30\]
 .*:    a460e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0\]
 .*:    a460e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0\]
 .*:    a460e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0\]
@@ -16240,44 +16240,44 @@ Disassembly of section .*:
 .*:    a460e3e0        ld4b    \{z0\.b-z3\.b\}, p0/z, \[sp\]
 .*:    a460e3e0        ld4b    \{z0\.b-z3\.b\}, p0/z, \[sp\]
 .*:    a460e3e0        ld4b    \{z0\.b-z3\.b\}, p0/z, \[sp\]
-.*:    a467e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,#28,mul vl\]
-.*:    a467e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,#28,mul vl\]
-.*:    a467e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,#28,mul vl\]
-.*:    a468e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,#-32,mul vl\]
-.*:    a468e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,#-32,mul vl\]
-.*:    a468e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,#-32,mul vl\]
-.*:    a469e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,#-28,mul vl\]
-.*:    a469e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,#-28,mul vl\]
-.*:    a469e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,#-28,mul vl\]
-.*:    a46fe000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,#-4,mul vl\]
-.*:    a46fe000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,#-4,mul vl\]
-.*:    a46fe000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0,#-4,mul vl\]
-.*:    a5e0c000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e0c000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e0c000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e0c001        ld4d    \{z1\.d-z4\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e0c001        ld4d    \{z1\.d-z4\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e0c001        ld4d    \{z1\.d-z4\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e0c01f        ld4d    \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e0c01f        ld4d    \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e0c800        ld4d    \{z0\.d-z3\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a5e0c800        ld4d    \{z0\.d-z3\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a5e0c800        ld4d    \{z0\.d-z3\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a5e0dc00        ld4d    \{z0\.d-z3\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a5e0dc00        ld4d    \{z0\.d-z3\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a5e0dc00        ld4d    \{z0\.d-z3\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a5e0c060        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a5e0c060        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a5e0c060        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a5e0c3e0        ld4d    \{z0\.d-z3\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a5e0c3e0        ld4d    \{z0\.d-z3\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a5e0c3e0        ld4d    \{z0\.d-z3\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a5e4c000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a5e4c000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a5e4c000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a5fec000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,x30,lsl #3\]
-.*:    a5fec000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,x30,lsl #3\]
-.*:    a5fec000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,x30,lsl #3\]
+.*:    a467e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, #28, mul vl\]
+.*:    a467e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, #28, mul vl\]
+.*:    a467e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, #28, mul vl\]
+.*:    a468e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, #-32, mul vl\]
+.*:    a468e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, #-32, mul vl\]
+.*:    a468e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, #-32, mul vl\]
+.*:    a469e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, #-28, mul vl\]
+.*:    a469e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, #-28, mul vl\]
+.*:    a469e000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, #-28, mul vl\]
+.*:    a46fe000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, #-4, mul vl\]
+.*:    a46fe000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, #-4, mul vl\]
+.*:    a46fe000        ld4b    \{z0\.b-z3\.b\}, p0/z, \[x0, #-4, mul vl\]
+.*:    a5e0c000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e0c000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e0c000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e0c001        ld4d    \{z1\.d-z4\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e0c001        ld4d    \{z1\.d-z4\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e0c001        ld4d    \{z1\.d-z4\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e0c01f        ld4d    \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e0c01f        ld4d    \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e0c800        ld4d    \{z0\.d-z3\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a5e0c800        ld4d    \{z0\.d-z3\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a5e0c800        ld4d    \{z0\.d-z3\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a5e0dc00        ld4d    \{z0\.d-z3\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a5e0dc00        ld4d    \{z0\.d-z3\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a5e0dc00        ld4d    \{z0\.d-z3\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a5e0c060        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a5e0c060        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a5e0c060        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a5e0c3e0        ld4d    \{z0\.d-z3\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a5e0c3e0        ld4d    \{z0\.d-z3\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a5e0c3e0        ld4d    \{z0\.d-z3\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a5e4c000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a5e4c000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a5e4c000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a5fec000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, x30, lsl #3\]
+.*:    a5fec000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, x30, lsl #3\]
+.*:    a5fec000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, x30, lsl #3\]
 .*:    a5e0e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0\]
 .*:    a5e0e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0\]
 .*:    a5e0e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0\]
@@ -16324,44 +16324,44 @@ Disassembly of section .*:
 .*:    a5e0e3e0        ld4d    \{z0\.d-z3\.d\}, p0/z, \[sp\]
 .*:    a5e0e3e0        ld4d    \{z0\.d-z3\.d\}, p0/z, \[sp\]
 .*:    a5e0e3e0        ld4d    \{z0\.d-z3\.d\}, p0/z, \[sp\]
-.*:    a5e7e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,#28,mul vl\]
-.*:    a5e7e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,#28,mul vl\]
-.*:    a5e7e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,#28,mul vl\]
-.*:    a5e8e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,#-32,mul vl\]
-.*:    a5e8e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,#-32,mul vl\]
-.*:    a5e8e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,#-32,mul vl\]
-.*:    a5e9e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,#-28,mul vl\]
-.*:    a5e9e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,#-28,mul vl\]
-.*:    a5e9e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,#-28,mul vl\]
-.*:    a5efe000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,#-4,mul vl\]
-.*:    a5efe000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,#-4,mul vl\]
-.*:    a5efe000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0,#-4,mul vl\]
-.*:    a4e0c000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e0c000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e0c000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e0c001        ld4h    \{z1\.h-z4\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e0c001        ld4h    \{z1\.h-z4\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e0c001        ld4h    \{z1\.h-z4\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e0c01f        ld4h    \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e0c01f        ld4h    \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e0c800        ld4h    \{z0\.h-z3\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4e0c800        ld4h    \{z0\.h-z3\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4e0c800        ld4h    \{z0\.h-z3\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4e0dc00        ld4h    \{z0\.h-z3\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4e0dc00        ld4h    \{z0\.h-z3\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4e0dc00        ld4h    \{z0\.h-z3\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4e0c060        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4e0c060        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4e0c060        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4e0c3e0        ld4h    \{z0\.h-z3\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4e0c3e0        ld4h    \{z0\.h-z3\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4e0c3e0        ld4h    \{z0\.h-z3\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4e4c000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4e4c000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4e4c000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4fec000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a4fec000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a4fec000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,x30,lsl #1\]
+.*:    a5e7e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, #28, mul vl\]
+.*:    a5e7e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, #28, mul vl\]
+.*:    a5e7e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, #28, mul vl\]
+.*:    a5e8e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, #-32, mul vl\]
+.*:    a5e8e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, #-32, mul vl\]
+.*:    a5e8e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, #-32, mul vl\]
+.*:    a5e9e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, #-28, mul vl\]
+.*:    a5e9e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, #-28, mul vl\]
+.*:    a5e9e000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, #-28, mul vl\]
+.*:    a5efe000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, #-4, mul vl\]
+.*:    a5efe000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, #-4, mul vl\]
+.*:    a5efe000        ld4d    \{z0\.d-z3\.d\}, p0/z, \[x0, #-4, mul vl\]
+.*:    a4e0c000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e0c000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e0c000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e0c001        ld4h    \{z1\.h-z4\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e0c001        ld4h    \{z1\.h-z4\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e0c001        ld4h    \{z1\.h-z4\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e0c01f        ld4h    \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e0c01f        ld4h    \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e0c800        ld4h    \{z0\.h-z3\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4e0c800        ld4h    \{z0\.h-z3\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4e0c800        ld4h    \{z0\.h-z3\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4e0dc00        ld4h    \{z0\.h-z3\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4e0dc00        ld4h    \{z0\.h-z3\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4e0dc00        ld4h    \{z0\.h-z3\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4e0c060        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4e0c060        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4e0c060        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4e0c3e0        ld4h    \{z0\.h-z3\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4e0c3e0        ld4h    \{z0\.h-z3\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4e0c3e0        ld4h    \{z0\.h-z3\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4e4c000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4e4c000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4e4c000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4fec000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a4fec000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a4fec000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, x30, lsl #1\]
 .*:    a4e0e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0\]
 .*:    a4e0e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0\]
 .*:    a4e0e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0\]
@@ -16408,44 +16408,44 @@ Disassembly of section .*:
 .*:    a4e0e3e0        ld4h    \{z0\.h-z3\.h\}, p0/z, \[sp\]
 .*:    a4e0e3e0        ld4h    \{z0\.h-z3\.h\}, p0/z, \[sp\]
 .*:    a4e0e3e0        ld4h    \{z0\.h-z3\.h\}, p0/z, \[sp\]
-.*:    a4e7e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,#28,mul vl\]
-.*:    a4e7e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,#28,mul vl\]
-.*:    a4e7e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,#28,mul vl\]
-.*:    a4e8e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,#-32,mul vl\]
-.*:    a4e8e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,#-32,mul vl\]
-.*:    a4e8e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,#-32,mul vl\]
-.*:    a4e9e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,#-28,mul vl\]
-.*:    a4e9e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,#-28,mul vl\]
-.*:    a4e9e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,#-28,mul vl\]
-.*:    a4efe000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,#-4,mul vl\]
-.*:    a4efe000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,#-4,mul vl\]
-.*:    a4efe000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0,#-4,mul vl\]
-.*:    a560c000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a560c000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a560c000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a560c001        ld4w    \{z1\.s-z4\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a560c001        ld4w    \{z1\.s-z4\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a560c001        ld4w    \{z1\.s-z4\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a560c01f        ld4w    \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a560c01f        ld4w    \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a560c800        ld4w    \{z0\.s-z3\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a560c800        ld4w    \{z0\.s-z3\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a560c800        ld4w    \{z0\.s-z3\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a560dc00        ld4w    \{z0\.s-z3\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a560dc00        ld4w    \{z0\.s-z3\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a560dc00        ld4w    \{z0\.s-z3\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a560c060        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a560c060        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a560c060        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a560c3e0        ld4w    \{z0\.s-z3\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a560c3e0        ld4w    \{z0\.s-z3\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a560c3e0        ld4w    \{z0\.s-z3\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a564c000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a564c000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a564c000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a57ec000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,x30,lsl #2\]
-.*:    a57ec000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,x30,lsl #2\]
-.*:    a57ec000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,x30,lsl #2\]
+.*:    a4e7e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, #28, mul vl\]
+.*:    a4e7e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, #28, mul vl\]
+.*:    a4e7e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, #28, mul vl\]
+.*:    a4e8e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, #-32, mul vl\]
+.*:    a4e8e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, #-32, mul vl\]
+.*:    a4e8e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, #-32, mul vl\]
+.*:    a4e9e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, #-28, mul vl\]
+.*:    a4e9e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, #-28, mul vl\]
+.*:    a4e9e000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, #-28, mul vl\]
+.*:    a4efe000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, #-4, mul vl\]
+.*:    a4efe000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, #-4, mul vl\]
+.*:    a4efe000        ld4h    \{z0\.h-z3\.h\}, p0/z, \[x0, #-4, mul vl\]
+.*:    a560c000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a560c000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a560c000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a560c001        ld4w    \{z1\.s-z4\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a560c001        ld4w    \{z1\.s-z4\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a560c001        ld4w    \{z1\.s-z4\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a560c01f        ld4w    \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a560c01f        ld4w    \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a560c800        ld4w    \{z0\.s-z3\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a560c800        ld4w    \{z0\.s-z3\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a560c800        ld4w    \{z0\.s-z3\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a560dc00        ld4w    \{z0\.s-z3\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a560dc00        ld4w    \{z0\.s-z3\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a560dc00        ld4w    \{z0\.s-z3\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a560c060        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a560c060        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a560c060        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a560c3e0        ld4w    \{z0\.s-z3\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a560c3e0        ld4w    \{z0\.s-z3\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a560c3e0        ld4w    \{z0\.s-z3\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a564c000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a564c000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a564c000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a57ec000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, x30, lsl #2\]
+.*:    a57ec000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, x30, lsl #2\]
+.*:    a57ec000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, x30, lsl #2\]
 .*:    a560e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0\]
 .*:    a560e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0\]
 .*:    a560e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0\]
@@ -16492,288 +16492,288 @@ Disassembly of section .*:
 .*:    a560e3e0        ld4w    \{z0\.s-z3\.s\}, p0/z, \[sp\]
 .*:    a560e3e0        ld4w    \{z0\.s-z3\.s\}, p0/z, \[sp\]
 .*:    a560e3e0        ld4w    \{z0\.s-z3\.s\}, p0/z, \[sp\]
-.*:    a567e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,#28,mul vl\]
-.*:    a567e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,#28,mul vl\]
-.*:    a567e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,#28,mul vl\]
-.*:    a568e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,#-32,mul vl\]
-.*:    a568e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,#-32,mul vl\]
-.*:    a568e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,#-32,mul vl\]
-.*:    a569e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,#-28,mul vl\]
-.*:    a569e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,#-28,mul vl\]
-.*:    a569e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,#-28,mul vl\]
-.*:    a56fe000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,#-4,mul vl\]
-.*:    a56fe000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,#-4,mul vl\]
-.*:    a56fe000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0,#-4,mul vl\]
-.*:    84006000        ldff1b  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84006000        ldff1b  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84006000        ldff1b  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84006000        ldff1b  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84006001        ldff1b  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84006001        ldff1b  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84006001        ldff1b  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84006001        ldff1b  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400601f        ldff1b  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400601f        ldff1b  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400601f        ldff1b  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400601f        ldff1b  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84006800        ldff1b  \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84006800        ldff1b  \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84006800        ldff1b  \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84007c00        ldff1b  \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84007c00        ldff1b  \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84007c00        ldff1b  \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84006060        ldff1b  \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84006060        ldff1b  \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84006060        ldff1b  \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    840063e0        ldff1b  \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    840063e0        ldff1b  \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    840063e0        ldff1b  \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    84046000        ldff1b  \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84046000        ldff1b  \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84046000        ldff1b  \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    841f6000        ldff1b  \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    841f6000        ldff1b  \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    841f6000        ldff1b  \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    84406000        ldff1b  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84406000        ldff1b  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84406000        ldff1b  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84406000        ldff1b  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84406001        ldff1b  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84406001        ldff1b  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84406001        ldff1b  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84406001        ldff1b  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440601f        ldff1b  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440601f        ldff1b  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440601f        ldff1b  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440601f        ldff1b  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84406800        ldff1b  \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84406800        ldff1b  \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84406800        ldff1b  \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84407c00        ldff1b  \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84407c00        ldff1b  \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84407c00        ldff1b  \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84406060        ldff1b  \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84406060        ldff1b  \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84406060        ldff1b  \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    844063e0        ldff1b  \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    844063e0        ldff1b  \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    844063e0        ldff1b  \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84446000        ldff1b  \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84446000        ldff1b  \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84446000        ldff1b  \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    845f6000        ldff1b  \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    845f6000        ldff1b  \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    845f6000        ldff1b  \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    a4006000        ldff1b  \{z0\.b\}, p0/z, \[x0,x0\]
-.*:    a4006000        ldff1b  \{z0\.b\}, p0/z, \[x0,x0\]
-.*:    a4006000        ldff1b  \{z0\.b\}, p0/z, \[x0,x0\]
-.*:    a4006000        ldff1b  \{z0\.b\}, p0/z, \[x0,x0\]
-.*:    a4006001        ldff1b  \{z1\.b\}, p0/z, \[x0,x0\]
-.*:    a4006001        ldff1b  \{z1\.b\}, p0/z, \[x0,x0\]
-.*:    a4006001        ldff1b  \{z1\.b\}, p0/z, \[x0,x0\]
-.*:    a4006001        ldff1b  \{z1\.b\}, p0/z, \[x0,x0\]
-.*:    a400601f        ldff1b  \{z31\.b\}, p0/z, \[x0,x0\]
-.*:    a400601f        ldff1b  \{z31\.b\}, p0/z, \[x0,x0\]
-.*:    a400601f        ldff1b  \{z31\.b\}, p0/z, \[x0,x0\]
-.*:    a400601f        ldff1b  \{z31\.b\}, p0/z, \[x0,x0\]
-.*:    a4006800        ldff1b  \{z0\.b\}, p2/z, \[x0,x0\]
-.*:    a4006800        ldff1b  \{z0\.b\}, p2/z, \[x0,x0\]
-.*:    a4006800        ldff1b  \{z0\.b\}, p2/z, \[x0,x0\]
-.*:    a4007c00        ldff1b  \{z0\.b\}, p7/z, \[x0,x0\]
-.*:    a4007c00        ldff1b  \{z0\.b\}, p7/z, \[x0,x0\]
-.*:    a4007c00        ldff1b  \{z0\.b\}, p7/z, \[x0,x0\]
-.*:    a4006060        ldff1b  \{z0\.b\}, p0/z, \[x3,x0\]
-.*:    a4006060        ldff1b  \{z0\.b\}, p0/z, \[x3,x0\]
-.*:    a4006060        ldff1b  \{z0\.b\}, p0/z, \[x3,x0\]
-.*:    a40063e0        ldff1b  \{z0\.b\}, p0/z, \[sp,x0\]
-.*:    a40063e0        ldff1b  \{z0\.b\}, p0/z, \[sp,x0\]
-.*:    a40063e0        ldff1b  \{z0\.b\}, p0/z, \[sp,x0\]
-.*:    a4046000        ldff1b  \{z0\.b\}, p0/z, \[x0,x4\]
-.*:    a4046000        ldff1b  \{z0\.b\}, p0/z, \[x0,x4\]
-.*:    a4046000        ldff1b  \{z0\.b\}, p0/z, \[x0,x4\]
-.*:    a41f6000        ldff1b  \{z0\.b\}, p0/z, \[x0,xzr\]
-.*:    a41f6000        ldff1b  \{z0\.b\}, p0/z, \[x0,xzr\]
-.*:    a41f6000        ldff1b  \{z0\.b\}, p0/z, \[x0,xzr\]
-.*:    a4206000        ldff1b  \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a4206000        ldff1b  \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a4206000        ldff1b  \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a4206000        ldff1b  \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a4206001        ldff1b  \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a4206001        ldff1b  \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a4206001        ldff1b  \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a4206001        ldff1b  \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a420601f        ldff1b  \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a420601f        ldff1b  \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a420601f        ldff1b  \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a420601f        ldff1b  \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a4206800        ldff1b  \{z0\.h\}, p2/z, \[x0,x0\]
-.*:    a4206800        ldff1b  \{z0\.h\}, p2/z, \[x0,x0\]
-.*:    a4206800        ldff1b  \{z0\.h\}, p2/z, \[x0,x0\]
-.*:    a4207c00        ldff1b  \{z0\.h\}, p7/z, \[x0,x0\]
-.*:    a4207c00        ldff1b  \{z0\.h\}, p7/z, \[x0,x0\]
-.*:    a4207c00        ldff1b  \{z0\.h\}, p7/z, \[x0,x0\]
-.*:    a4206060        ldff1b  \{z0\.h\}, p0/z, \[x3,x0\]
-.*:    a4206060        ldff1b  \{z0\.h\}, p0/z, \[x3,x0\]
-.*:    a4206060        ldff1b  \{z0\.h\}, p0/z, \[x3,x0\]
-.*:    a42063e0        ldff1b  \{z0\.h\}, p0/z, \[sp,x0\]
-.*:    a42063e0        ldff1b  \{z0\.h\}, p0/z, \[sp,x0\]
-.*:    a42063e0        ldff1b  \{z0\.h\}, p0/z, \[sp,x0\]
-.*:    a4246000        ldff1b  \{z0\.h\}, p0/z, \[x0,x4\]
-.*:    a4246000        ldff1b  \{z0\.h\}, p0/z, \[x0,x4\]
-.*:    a4246000        ldff1b  \{z0\.h\}, p0/z, \[x0,x4\]
-.*:    a43f6000        ldff1b  \{z0\.h\}, p0/z, \[x0,xzr\]
-.*:    a43f6000        ldff1b  \{z0\.h\}, p0/z, \[x0,xzr\]
-.*:    a43f6000        ldff1b  \{z0\.h\}, p0/z, \[x0,xzr\]
-.*:    a4406000        ldff1b  \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a4406000        ldff1b  \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a4406000        ldff1b  \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a4406000        ldff1b  \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a4406001        ldff1b  \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a4406001        ldff1b  \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a4406001        ldff1b  \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a4406001        ldff1b  \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a440601f        ldff1b  \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a440601f        ldff1b  \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a440601f        ldff1b  \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a440601f        ldff1b  \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a4406800        ldff1b  \{z0\.s\}, p2/z, \[x0,x0\]
-.*:    a4406800        ldff1b  \{z0\.s\}, p2/z, \[x0,x0\]
-.*:    a4406800        ldff1b  \{z0\.s\}, p2/z, \[x0,x0\]
-.*:    a4407c00        ldff1b  \{z0\.s\}, p7/z, \[x0,x0\]
-.*:    a4407c00        ldff1b  \{z0\.s\}, p7/z, \[x0,x0\]
-.*:    a4407c00        ldff1b  \{z0\.s\}, p7/z, \[x0,x0\]
-.*:    a4406060        ldff1b  \{z0\.s\}, p0/z, \[x3,x0\]
-.*:    a4406060        ldff1b  \{z0\.s\}, p0/z, \[x3,x0\]
-.*:    a4406060        ldff1b  \{z0\.s\}, p0/z, \[x3,x0\]
-.*:    a44063e0        ldff1b  \{z0\.s\}, p0/z, \[sp,x0\]
-.*:    a44063e0        ldff1b  \{z0\.s\}, p0/z, \[sp,x0\]
-.*:    a44063e0        ldff1b  \{z0\.s\}, p0/z, \[sp,x0\]
-.*:    a4446000        ldff1b  \{z0\.s\}, p0/z, \[x0,x4\]
-.*:    a4446000        ldff1b  \{z0\.s\}, p0/z, \[x0,x4\]
-.*:    a4446000        ldff1b  \{z0\.s\}, p0/z, \[x0,x4\]
-.*:    a45f6000        ldff1b  \{z0\.s\}, p0/z, \[x0,xzr\]
-.*:    a45f6000        ldff1b  \{z0\.s\}, p0/z, \[x0,xzr\]
-.*:    a45f6000        ldff1b  \{z0\.s\}, p0/z, \[x0,xzr\]
-.*:    a4606000        ldff1b  \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a4606000        ldff1b  \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a4606000        ldff1b  \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a4606000        ldff1b  \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a4606001        ldff1b  \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a4606001        ldff1b  \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a4606001        ldff1b  \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a4606001        ldff1b  \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a460601f        ldff1b  \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a460601f        ldff1b  \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a460601f        ldff1b  \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a460601f        ldff1b  \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a4606800        ldff1b  \{z0\.d\}, p2/z, \[x0,x0\]
-.*:    a4606800        ldff1b  \{z0\.d\}, p2/z, \[x0,x0\]
-.*:    a4606800        ldff1b  \{z0\.d\}, p2/z, \[x0,x0\]
-.*:    a4607c00        ldff1b  \{z0\.d\}, p7/z, \[x0,x0\]
-.*:    a4607c00        ldff1b  \{z0\.d\}, p7/z, \[x0,x0\]
-.*:    a4607c00        ldff1b  \{z0\.d\}, p7/z, \[x0,x0\]
-.*:    a4606060        ldff1b  \{z0\.d\}, p0/z, \[x3,x0\]
-.*:    a4606060        ldff1b  \{z0\.d\}, p0/z, \[x3,x0\]
-.*:    a4606060        ldff1b  \{z0\.d\}, p0/z, \[x3,x0\]
-.*:    a46063e0        ldff1b  \{z0\.d\}, p0/z, \[sp,x0\]
-.*:    a46063e0        ldff1b  \{z0\.d\}, p0/z, \[sp,x0\]
-.*:    a46063e0        ldff1b  \{z0\.d\}, p0/z, \[sp,x0\]
-.*:    a4646000        ldff1b  \{z0\.d\}, p0/z, \[x0,x4\]
-.*:    a4646000        ldff1b  \{z0\.d\}, p0/z, \[x0,x4\]
-.*:    a4646000        ldff1b  \{z0\.d\}, p0/z, \[x0,x4\]
-.*:    a47f6000        ldff1b  \{z0\.d\}, p0/z, \[x0,xzr\]
-.*:    a47f6000        ldff1b  \{z0\.d\}, p0/z, \[x0,xzr\]
-.*:    a47f6000        ldff1b  \{z0\.d\}, p0/z, \[x0,xzr\]
-.*:    c4006000        ldff1b  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4006000        ldff1b  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4006000        ldff1b  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4006000        ldff1b  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4006001        ldff1b  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4006001        ldff1b  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4006001        ldff1b  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4006001        ldff1b  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400601f        ldff1b  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400601f        ldff1b  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400601f        ldff1b  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400601f        ldff1b  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4006800        ldff1b  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4006800        ldff1b  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4006800        ldff1b  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4007c00        ldff1b  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4007c00        ldff1b  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4007c00        ldff1b  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4006060        ldff1b  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4006060        ldff1b  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4006060        ldff1b  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c40063e0        ldff1b  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c40063e0        ldff1b  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c40063e0        ldff1b  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c4046000        ldff1b  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4046000        ldff1b  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4046000        ldff1b  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c41f6000        ldff1b  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c41f6000        ldff1b  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c41f6000        ldff1b  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c4406000        ldff1b  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4406000        ldff1b  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4406000        ldff1b  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4406000        ldff1b  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4406001        ldff1b  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4406001        ldff1b  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4406001        ldff1b  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4406001        ldff1b  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440601f        ldff1b  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440601f        ldff1b  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440601f        ldff1b  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440601f        ldff1b  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4406800        ldff1b  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4406800        ldff1b  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4406800        ldff1b  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4407c00        ldff1b  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4407c00        ldff1b  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4407c00        ldff1b  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4406060        ldff1b  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4406060        ldff1b  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4406060        ldff1b  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c44063e0        ldff1b  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c44063e0        ldff1b  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c44063e0        ldff1b  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4446000        ldff1b  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4446000        ldff1b  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4446000        ldff1b  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c45f6000        ldff1b  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c45f6000        ldff1b  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c45f6000        ldff1b  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c440e000        ldff1b  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440e000        ldff1b  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440e000        ldff1b  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440e000        ldff1b  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440e001        ldff1b  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440e001        ldff1b  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440e001        ldff1b  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440e001        ldff1b  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440e01f        ldff1b  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440e01f        ldff1b  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440e01f        ldff1b  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440e01f        ldff1b  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440e800        ldff1b  \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c440e800        ldff1b  \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c440e800        ldff1b  \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c440fc00        ldff1b  \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c440fc00        ldff1b  \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c440fc00        ldff1b  \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c440e060        ldff1b  \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c440e060        ldff1b  \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c440e060        ldff1b  \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c440e3e0        ldff1b  \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c440e3e0        ldff1b  \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c440e3e0        ldff1b  \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c444e000        ldff1b  \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c444e000        ldff1b  \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c444e000        ldff1b  \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c45fe000        ldff1b  \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c45fe000        ldff1b  \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c45fe000        ldff1b  \{z0\.d\}, p0/z, \[x0,z31\.d\]
+.*:    a567e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, #28, mul vl\]
+.*:    a567e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, #28, mul vl\]
+.*:    a567e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, #28, mul vl\]
+.*:    a568e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, #-32, mul vl\]
+.*:    a568e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, #-32, mul vl\]
+.*:    a568e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, #-32, mul vl\]
+.*:    a569e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, #-28, mul vl\]
+.*:    a569e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, #-28, mul vl\]
+.*:    a569e000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, #-28, mul vl\]
+.*:    a56fe000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, #-4, mul vl\]
+.*:    a56fe000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, #-4, mul vl\]
+.*:    a56fe000        ld4w    \{z0\.s-z3\.s\}, p0/z, \[x0, #-4, mul vl\]
+.*:    84006000        ldff1b  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84006000        ldff1b  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84006000        ldff1b  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84006000        ldff1b  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84006001        ldff1b  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84006001        ldff1b  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84006001        ldff1b  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84006001        ldff1b  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400601f        ldff1b  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400601f        ldff1b  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400601f        ldff1b  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400601f        ldff1b  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84006800        ldff1b  \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84006800        ldff1b  \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84006800        ldff1b  \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84007c00        ldff1b  \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84007c00        ldff1b  \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84007c00        ldff1b  \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84006060        ldff1b  \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84006060        ldff1b  \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84006060        ldff1b  \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    840063e0        ldff1b  \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    840063e0        ldff1b  \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    840063e0        ldff1b  \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    84046000        ldff1b  \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84046000        ldff1b  \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84046000        ldff1b  \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    841f6000        ldff1b  \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    841f6000        ldff1b  \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    841f6000        ldff1b  \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    84406000        ldff1b  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84406000        ldff1b  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84406000        ldff1b  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84406000        ldff1b  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84406001        ldff1b  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84406001        ldff1b  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84406001        ldff1b  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84406001        ldff1b  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440601f        ldff1b  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440601f        ldff1b  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440601f        ldff1b  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440601f        ldff1b  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84406800        ldff1b  \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84406800        ldff1b  \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84406800        ldff1b  \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84407c00        ldff1b  \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84407c00        ldff1b  \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84407c00        ldff1b  \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84406060        ldff1b  \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84406060        ldff1b  \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84406060        ldff1b  \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    844063e0        ldff1b  \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    844063e0        ldff1b  \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    844063e0        ldff1b  \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84446000        ldff1b  \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84446000        ldff1b  \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84446000        ldff1b  \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    845f6000        ldff1b  \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    845f6000        ldff1b  \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    845f6000        ldff1b  \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    a4006000        ldff1b  \{z0\.b\}, p0/z, \[x0, x0\]
+.*:    a4006000        ldff1b  \{z0\.b\}, p0/z, \[x0, x0\]
+.*:    a4006000        ldff1b  \{z0\.b\}, p0/z, \[x0, x0\]
+.*:    a4006000        ldff1b  \{z0\.b\}, p0/z, \[x0, x0\]
+.*:    a4006001        ldff1b  \{z1\.b\}, p0/z, \[x0, x0\]
+.*:    a4006001        ldff1b  \{z1\.b\}, p0/z, \[x0, x0\]
+.*:    a4006001        ldff1b  \{z1\.b\}, p0/z, \[x0, x0\]
+.*:    a4006001        ldff1b  \{z1\.b\}, p0/z, \[x0, x0\]
+.*:    a400601f        ldff1b  \{z31\.b\}, p0/z, \[x0, x0\]
+.*:    a400601f        ldff1b  \{z31\.b\}, p0/z, \[x0, x0\]
+.*:    a400601f        ldff1b  \{z31\.b\}, p0/z, \[x0, x0\]
+.*:    a400601f        ldff1b  \{z31\.b\}, p0/z, \[x0, x0\]
+.*:    a4006800        ldff1b  \{z0\.b\}, p2/z, \[x0, x0\]
+.*:    a4006800        ldff1b  \{z0\.b\}, p2/z, \[x0, x0\]
+.*:    a4006800        ldff1b  \{z0\.b\}, p2/z, \[x0, x0\]
+.*:    a4007c00        ldff1b  \{z0\.b\}, p7/z, \[x0, x0\]
+.*:    a4007c00        ldff1b  \{z0\.b\}, p7/z, \[x0, x0\]
+.*:    a4007c00        ldff1b  \{z0\.b\}, p7/z, \[x0, x0\]
+.*:    a4006060        ldff1b  \{z0\.b\}, p0/z, \[x3, x0\]
+.*:    a4006060        ldff1b  \{z0\.b\}, p0/z, \[x3, x0\]
+.*:    a4006060        ldff1b  \{z0\.b\}, p0/z, \[x3, x0\]
+.*:    a40063e0        ldff1b  \{z0\.b\}, p0/z, \[sp, x0\]
+.*:    a40063e0        ldff1b  \{z0\.b\}, p0/z, \[sp, x0\]
+.*:    a40063e0        ldff1b  \{z0\.b\}, p0/z, \[sp, x0\]
+.*:    a4046000        ldff1b  \{z0\.b\}, p0/z, \[x0, x4\]
+.*:    a4046000        ldff1b  \{z0\.b\}, p0/z, \[x0, x4\]
+.*:    a4046000        ldff1b  \{z0\.b\}, p0/z, \[x0, x4\]
+.*:    a41f6000        ldff1b  \{z0\.b\}, p0/z, \[x0, xzr\]
+.*:    a41f6000        ldff1b  \{z0\.b\}, p0/z, \[x0, xzr\]
+.*:    a41f6000        ldff1b  \{z0\.b\}, p0/z, \[x0, xzr\]
+.*:    a4206000        ldff1b  \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a4206000        ldff1b  \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a4206000        ldff1b  \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a4206000        ldff1b  \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a4206001        ldff1b  \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a4206001        ldff1b  \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a4206001        ldff1b  \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a4206001        ldff1b  \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a420601f        ldff1b  \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a420601f        ldff1b  \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a420601f        ldff1b  \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a420601f        ldff1b  \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a4206800        ldff1b  \{z0\.h\}, p2/z, \[x0, x0\]
+.*:    a4206800        ldff1b  \{z0\.h\}, p2/z, \[x0, x0\]
+.*:    a4206800        ldff1b  \{z0\.h\}, p2/z, \[x0, x0\]
+.*:    a4207c00        ldff1b  \{z0\.h\}, p7/z, \[x0, x0\]
+.*:    a4207c00        ldff1b  \{z0\.h\}, p7/z, \[x0, x0\]
+.*:    a4207c00        ldff1b  \{z0\.h\}, p7/z, \[x0, x0\]
+.*:    a4206060        ldff1b  \{z0\.h\}, p0/z, \[x3, x0\]
+.*:    a4206060        ldff1b  \{z0\.h\}, p0/z, \[x3, x0\]
+.*:    a4206060        ldff1b  \{z0\.h\}, p0/z, \[x3, x0\]
+.*:    a42063e0        ldff1b  \{z0\.h\}, p0/z, \[sp, x0\]
+.*:    a42063e0        ldff1b  \{z0\.h\}, p0/z, \[sp, x0\]
+.*:    a42063e0        ldff1b  \{z0\.h\}, p0/z, \[sp, x0\]
+.*:    a4246000        ldff1b  \{z0\.h\}, p0/z, \[x0, x4\]
+.*:    a4246000        ldff1b  \{z0\.h\}, p0/z, \[x0, x4\]
+.*:    a4246000        ldff1b  \{z0\.h\}, p0/z, \[x0, x4\]
+.*:    a43f6000        ldff1b  \{z0\.h\}, p0/z, \[x0, xzr\]
+.*:    a43f6000        ldff1b  \{z0\.h\}, p0/z, \[x0, xzr\]
+.*:    a43f6000        ldff1b  \{z0\.h\}, p0/z, \[x0, xzr\]
+.*:    a4406000        ldff1b  \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a4406000        ldff1b  \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a4406000        ldff1b  \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a4406000        ldff1b  \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a4406001        ldff1b  \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a4406001        ldff1b  \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a4406001        ldff1b  \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a4406001        ldff1b  \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a440601f        ldff1b  \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a440601f        ldff1b  \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a440601f        ldff1b  \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a440601f        ldff1b  \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a4406800        ldff1b  \{z0\.s\}, p2/z, \[x0, x0\]
+.*:    a4406800        ldff1b  \{z0\.s\}, p2/z, \[x0, x0\]
+.*:    a4406800        ldff1b  \{z0\.s\}, p2/z, \[x0, x0\]
+.*:    a4407c00        ldff1b  \{z0\.s\}, p7/z, \[x0, x0\]
+.*:    a4407c00        ldff1b  \{z0\.s\}, p7/z, \[x0, x0\]
+.*:    a4407c00        ldff1b  \{z0\.s\}, p7/z, \[x0, x0\]
+.*:    a4406060        ldff1b  \{z0\.s\}, p0/z, \[x3, x0\]
+.*:    a4406060        ldff1b  \{z0\.s\}, p0/z, \[x3, x0\]
+.*:    a4406060        ldff1b  \{z0\.s\}, p0/z, \[x3, x0\]
+.*:    a44063e0        ldff1b  \{z0\.s\}, p0/z, \[sp, x0\]
+.*:    a44063e0        ldff1b  \{z0\.s\}, p0/z, \[sp, x0\]
+.*:    a44063e0        ldff1b  \{z0\.s\}, p0/z, \[sp, x0\]
+.*:    a4446000        ldff1b  \{z0\.s\}, p0/z, \[x0, x4\]
+.*:    a4446000        ldff1b  \{z0\.s\}, p0/z, \[x0, x4\]
+.*:    a4446000        ldff1b  \{z0\.s\}, p0/z, \[x0, x4\]
+.*:    a45f6000        ldff1b  \{z0\.s\}, p0/z, \[x0, xzr\]
+.*:    a45f6000        ldff1b  \{z0\.s\}, p0/z, \[x0, xzr\]
+.*:    a45f6000        ldff1b  \{z0\.s\}, p0/z, \[x0, xzr\]
+.*:    a4606000        ldff1b  \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a4606000        ldff1b  \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a4606000        ldff1b  \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a4606000        ldff1b  \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a4606001        ldff1b  \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a4606001        ldff1b  \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a4606001        ldff1b  \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a4606001        ldff1b  \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a460601f        ldff1b  \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a460601f        ldff1b  \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a460601f        ldff1b  \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a460601f        ldff1b  \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a4606800        ldff1b  \{z0\.d\}, p2/z, \[x0, x0\]
+.*:    a4606800        ldff1b  \{z0\.d\}, p2/z, \[x0, x0\]
+.*:    a4606800        ldff1b  \{z0\.d\}, p2/z, \[x0, x0\]
+.*:    a4607c00        ldff1b  \{z0\.d\}, p7/z, \[x0, x0\]
+.*:    a4607c00        ldff1b  \{z0\.d\}, p7/z, \[x0, x0\]
+.*:    a4607c00        ldff1b  \{z0\.d\}, p7/z, \[x0, x0\]
+.*:    a4606060        ldff1b  \{z0\.d\}, p0/z, \[x3, x0\]
+.*:    a4606060        ldff1b  \{z0\.d\}, p0/z, \[x3, x0\]
+.*:    a4606060        ldff1b  \{z0\.d\}, p0/z, \[x3, x0\]
+.*:    a46063e0        ldff1b  \{z0\.d\}, p0/z, \[sp, x0\]
+.*:    a46063e0        ldff1b  \{z0\.d\}, p0/z, \[sp, x0\]
+.*:    a46063e0        ldff1b  \{z0\.d\}, p0/z, \[sp, x0\]
+.*:    a4646000        ldff1b  \{z0\.d\}, p0/z, \[x0, x4\]
+.*:    a4646000        ldff1b  \{z0\.d\}, p0/z, \[x0, x4\]
+.*:    a4646000        ldff1b  \{z0\.d\}, p0/z, \[x0, x4\]
+.*:    a47f6000        ldff1b  \{z0\.d\}, p0/z, \[x0, xzr\]
+.*:    a47f6000        ldff1b  \{z0\.d\}, p0/z, \[x0, xzr\]
+.*:    a47f6000        ldff1b  \{z0\.d\}, p0/z, \[x0, xzr\]
+.*:    c4006000        ldff1b  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4006000        ldff1b  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4006000        ldff1b  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4006000        ldff1b  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4006001        ldff1b  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4006001        ldff1b  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4006001        ldff1b  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4006001        ldff1b  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400601f        ldff1b  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400601f        ldff1b  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400601f        ldff1b  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400601f        ldff1b  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4006800        ldff1b  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4006800        ldff1b  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4006800        ldff1b  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4007c00        ldff1b  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4007c00        ldff1b  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4007c00        ldff1b  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4006060        ldff1b  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4006060        ldff1b  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4006060        ldff1b  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c40063e0        ldff1b  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c40063e0        ldff1b  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c40063e0        ldff1b  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c4046000        ldff1b  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4046000        ldff1b  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4046000        ldff1b  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c41f6000        ldff1b  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c41f6000        ldff1b  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c41f6000        ldff1b  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c4406000        ldff1b  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4406000        ldff1b  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4406000        ldff1b  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4406000        ldff1b  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4406001        ldff1b  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4406001        ldff1b  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4406001        ldff1b  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4406001        ldff1b  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440601f        ldff1b  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440601f        ldff1b  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440601f        ldff1b  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440601f        ldff1b  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4406800        ldff1b  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4406800        ldff1b  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4406800        ldff1b  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4407c00        ldff1b  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4407c00        ldff1b  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4407c00        ldff1b  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4406060        ldff1b  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4406060        ldff1b  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4406060        ldff1b  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c44063e0        ldff1b  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c44063e0        ldff1b  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c44063e0        ldff1b  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4446000        ldff1b  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4446000        ldff1b  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4446000        ldff1b  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c45f6000        ldff1b  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c45f6000        ldff1b  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c45f6000        ldff1b  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c440e000        ldff1b  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440e000        ldff1b  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440e000        ldff1b  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440e000        ldff1b  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440e001        ldff1b  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440e001        ldff1b  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440e001        ldff1b  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440e001        ldff1b  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440e01f        ldff1b  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440e01f        ldff1b  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440e01f        ldff1b  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440e01f        ldff1b  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440e800        ldff1b  \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c440e800        ldff1b  \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c440e800        ldff1b  \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c440fc00        ldff1b  \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c440fc00        ldff1b  \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c440fc00        ldff1b  \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c440e060        ldff1b  \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c440e060        ldff1b  \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c440e060        ldff1b  \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c440e3e0        ldff1b  \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c440e3e0        ldff1b  \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c440e3e0        ldff1b  \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c444e000        ldff1b  \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c444e000        ldff1b  \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c444e000        ldff1b  \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c45fe000        ldff1b  \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c45fe000        ldff1b  \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c45fe000        ldff1b  \{z0\.d\}, p0/z, \[x0, z31\.d\]
 .*:    8420e000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    8420e000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    8420e000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s\]
@@ -16798,14 +16798,14 @@ Disassembly of section .*:
 .*:    8420e3e0        ldff1b  \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    8420e3e0        ldff1b  \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    8420e3e0        ldff1b  \{z0\.s\}, p0/z, \[z31\.s\]
-.*:    842fe000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s,#15\]
-.*:    842fe000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s,#15\]
-.*:    8430e000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s,#16\]
-.*:    8430e000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s,#16\]
-.*:    8431e000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s,#17\]
-.*:    8431e000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s,#17\]
-.*:    843fe000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s,#31\]
-.*:    843fe000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s,#31\]
+.*:    842fe000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s, #15\]
+.*:    842fe000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s, #15\]
+.*:    8430e000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s, #16\]
+.*:    8430e000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s, #16\]
+.*:    8431e000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s, #17\]
+.*:    8431e000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s, #17\]
+.*:    843fe000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s, #31\]
+.*:    843fe000        ldff1b  \{z0\.s\}, p0/z, \[z0\.s, #31\]
 .*:    c420e000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c420e000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c420e000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d\]
@@ -16830,188 +16830,188 @@ Disassembly of section .*:
 .*:    c420e3e0        ldff1b  \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c420e3e0        ldff1b  \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c420e3e0        ldff1b  \{z0\.d\}, p0/z, \[z31\.d\]
-.*:    c42fe000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d,#15\]
-.*:    c42fe000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d,#15\]
-.*:    c430e000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d,#16\]
-.*:    c430e000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d,#16\]
-.*:    c431e000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d,#17\]
-.*:    c431e000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d,#17\]
-.*:    c43fe000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d,#31\]
-.*:    c43fe000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d,#31\]
-.*:    a5e06000        ldff1d  \{z0\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e06000        ldff1d  \{z0\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e06000        ldff1d  \{z0\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e06001        ldff1d  \{z1\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e06001        ldff1d  \{z1\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e06001        ldff1d  \{z1\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e0601f        ldff1d  \{z31\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e0601f        ldff1d  \{z31\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e0601f        ldff1d  \{z31\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a5e06800        ldff1d  \{z0\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a5e06800        ldff1d  \{z0\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a5e07c00        ldff1d  \{z0\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a5e07c00        ldff1d  \{z0\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a5e06060        ldff1d  \{z0\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a5e06060        ldff1d  \{z0\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a5e063e0        ldff1d  \{z0\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a5e063e0        ldff1d  \{z0\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a5e46000        ldff1d  \{z0\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a5e46000        ldff1d  \{z0\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a5ff6000        ldff1d  \{z0\.d\}, p0/z, \[x0,xzr,lsl #3\]
-.*:    a5ff6000        ldff1d  \{z0\.d\}, p0/z, \[x0,xzr,lsl #3\]
-.*:    c5806000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5806000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5806000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5806000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5806001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5806001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5806001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5806001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c580601f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c580601f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c580601f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c580601f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5806800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5806800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5806800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5807c00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5807c00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5807c00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5806060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c5806060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c5806060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c58063e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c58063e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c58063e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c5846000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c5846000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c5846000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c59f6000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c59f6000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c59f6000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c5c06000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c06000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c06000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c06000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c06001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c06001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c06001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c06001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c0601f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c0601f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c0601f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c0601f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5c06800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5c06800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5c06800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5c07c00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5c07c00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5c07c00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5c06060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c5c06060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c5c06060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c5c063e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c5c063e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c5c063e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c5c46000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c5c46000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c5c46000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c5df6000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c5df6000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c5df6000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c5a06000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a06000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a06000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a06001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a06001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a06001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a0601f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a0601f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a0601f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a06800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a06800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a07c00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a07c00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #3\]
-.*:    c5a06060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #3\]
-.*:    c5a06060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #3\]
-.*:    c5a063e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #3\]
-.*:    c5a063e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #3\]
-.*:    c5a46000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #3\]
-.*:    c5a46000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #3\]
-.*:    c5bf6000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #3\]
-.*:    c5bf6000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #3\]
-.*:    c5e06000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e06000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e06000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e06001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e06001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e06001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e0601f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e0601f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e0601f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e06800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e06800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e07c00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e07c00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #3\]
-.*:    c5e06060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #3\]
-.*:    c5e06060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #3\]
-.*:    c5e063e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #3\]
-.*:    c5e063e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #3\]
-.*:    c5e46000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #3\]
-.*:    c5e46000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #3\]
-.*:    c5ff6000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #3\]
-.*:    c5ff6000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #3\]
-.*:    c5c0e000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0e000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0e000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0e000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0e001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0e001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0e001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0e001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0e01f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0e01f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0e01f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0e01f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c5c0e800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c5c0e800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c5c0e800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c5c0fc00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c5c0fc00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c5c0fc00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c5c0e060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c5c0e060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c5c0e060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c5c0e3e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c5c0e3e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c5c0e3e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c5c4e000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c5c4e000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c5c4e000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c5dfe000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c5dfe000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c5dfe000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c5e0e000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0e000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0e000        ldff1d  \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0e001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0e001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0e001        ldff1d  \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0e01f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0e01f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0e01f        ldff1d  \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0e800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0e800        ldff1d  \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0fc00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0fc00        ldff1d  \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #3\]
-.*:    c5e0e060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #3\]
-.*:    c5e0e060        ldff1d  \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #3\]
-.*:    c5e0e3e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #3\]
-.*:    c5e0e3e0        ldff1d  \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #3\]
-.*:    c5e4e000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #3\]
-.*:    c5e4e000        ldff1d  \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #3\]
-.*:    c5ffe000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #3\]
-.*:    c5ffe000        ldff1d  \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #3\]
+.*:    c42fe000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d, #15\]
+.*:    c42fe000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d, #15\]
+.*:    c430e000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d, #16\]
+.*:    c430e000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d, #16\]
+.*:    c431e000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d, #17\]
+.*:    c431e000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d, #17\]
+.*:    c43fe000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d, #31\]
+.*:    c43fe000        ldff1b  \{z0\.d\}, p0/z, \[z0\.d, #31\]
+.*:    a5e06000        ldff1d  \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e06000        ldff1d  \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e06000        ldff1d  \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e06001        ldff1d  \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e06001        ldff1d  \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e06001        ldff1d  \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e0601f        ldff1d  \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e0601f        ldff1d  \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e0601f        ldff1d  \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a5e06800        ldff1d  \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a5e06800        ldff1d  \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a5e07c00        ldff1d  \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a5e07c00        ldff1d  \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a5e06060        ldff1d  \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a5e06060        ldff1d  \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a5e063e0        ldff1d  \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a5e063e0        ldff1d  \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a5e46000        ldff1d  \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a5e46000        ldff1d  \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a5ff6000        ldff1d  \{z0\.d\}, p0/z, \[x0, xzr, lsl #3\]
+.*:    a5ff6000        ldff1d  \{z0\.d\}, p0/z, \[x0, xzr, lsl #3\]
+.*:    c5806000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5806000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5806000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5806000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5806001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5806001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5806001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5806001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c580601f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c580601f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c580601f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c580601f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5806800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5806800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5806800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5807c00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5807c00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5807c00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5806060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c5806060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c5806060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c58063e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c58063e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c58063e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c5846000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c5846000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c5846000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c59f6000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c59f6000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c59f6000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c5c06000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c06000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c06000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c06000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c06001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c06001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c06001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c06001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c0601f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c0601f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c0601f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c0601f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5c06800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5c06800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5c06800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5c07c00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5c07c00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5c07c00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5c06060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c5c06060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c5c06060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c5c063e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c5c063e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c5c063e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c5c46000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c5c46000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c5c46000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c5df6000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c5df6000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c5df6000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c5a06000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a06000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a06000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a06001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a06001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a06001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a0601f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a0601f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a0601f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a06800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a06800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a07c00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a07c00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #3\]
+.*:    c5a06060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #3\]
+.*:    c5a06060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #3\]
+.*:    c5a063e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #3\]
+.*:    c5a063e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #3\]
+.*:    c5a46000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #3\]
+.*:    c5a46000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #3\]
+.*:    c5bf6000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #3\]
+.*:    c5bf6000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #3\]
+.*:    c5e06000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e06000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e06000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e06001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e06001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e06001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e0601f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e0601f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e0601f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e06800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e06800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e07c00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e07c00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #3\]
+.*:    c5e06060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #3\]
+.*:    c5e06060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #3\]
+.*:    c5e063e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #3\]
+.*:    c5e063e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #3\]
+.*:    c5e46000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #3\]
+.*:    c5e46000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #3\]
+.*:    c5ff6000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #3\]
+.*:    c5ff6000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #3\]
+.*:    c5c0e000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0e000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0e000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0e000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0e001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0e001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0e001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0e001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0e01f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0e01f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0e01f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0e01f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c5c0e800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c5c0e800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c5c0e800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c5c0fc00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c5c0fc00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c5c0fc00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c5c0e060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c5c0e060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c5c0e060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c5c0e3e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c5c0e3e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c5c0e3e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c5c4e000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c5c4e000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c5c4e000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c5dfe000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c5dfe000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c5dfe000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c5e0e000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0e000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0e000        ldff1d  \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0e001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0e001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0e001        ldff1d  \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0e01f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0e01f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0e01f        ldff1d  \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0e800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0e800        ldff1d  \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0fc00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0fc00        ldff1d  \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #3\]
+.*:    c5e0e060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #3\]
+.*:    c5e0e060        ldff1d  \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #3\]
+.*:    c5e0e3e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #3\]
+.*:    c5e0e3e0        ldff1d  \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #3\]
+.*:    c5e4e000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #3\]
+.*:    c5e4e000        ldff1d  \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #3\]
+.*:    c5ffe000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #3\]
+.*:    c5ffe000        ldff1d  \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #3\]
 .*:    c5a0e000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c5a0e000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c5a0e000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d\]
@@ -17036,332 +17036,332 @@ Disassembly of section .*:
 .*:    c5a0e3e0        ldff1d  \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c5a0e3e0        ldff1d  \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c5a0e3e0        ldff1d  \{z0\.d\}, p0/z, \[z31\.d\]
-.*:    c5afe000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d,#120\]
-.*:    c5afe000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d,#120\]
-.*:    c5b0e000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d,#128\]
-.*:    c5b0e000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d,#128\]
-.*:    c5b1e000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d,#136\]
-.*:    c5b1e000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d,#136\]
-.*:    c5bfe000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d,#248\]
-.*:    c5bfe000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d,#248\]
-.*:    84806000        ldff1h  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84806000        ldff1h  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84806000        ldff1h  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84806000        ldff1h  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84806001        ldff1h  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84806001        ldff1h  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84806001        ldff1h  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84806001        ldff1h  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480601f        ldff1h  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480601f        ldff1h  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480601f        ldff1h  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480601f        ldff1h  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84806800        ldff1h  \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84806800        ldff1h  \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84806800        ldff1h  \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84807c00        ldff1h  \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84807c00        ldff1h  \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84807c00        ldff1h  \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84806060        ldff1h  \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84806060        ldff1h  \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84806060        ldff1h  \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    848063e0        ldff1h  \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    848063e0        ldff1h  \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    848063e0        ldff1h  \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    84846000        ldff1h  \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84846000        ldff1h  \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84846000        ldff1h  \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    849f6000        ldff1h  \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    849f6000        ldff1h  \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    849f6000        ldff1h  \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    84c06000        ldff1h  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c06000        ldff1h  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c06000        ldff1h  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c06000        ldff1h  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c06001        ldff1h  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c06001        ldff1h  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c06001        ldff1h  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c06001        ldff1h  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0601f        ldff1h  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0601f        ldff1h  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0601f        ldff1h  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0601f        ldff1h  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c06800        ldff1h  \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84c06800        ldff1h  \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84c06800        ldff1h  \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84c07c00        ldff1h  \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84c07c00        ldff1h  \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84c07c00        ldff1h  \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84c06060        ldff1h  \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84c06060        ldff1h  \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84c06060        ldff1h  \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84c063e0        ldff1h  \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84c063e0        ldff1h  \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84c063e0        ldff1h  \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84c46000        ldff1h  \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84c46000        ldff1h  \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84c46000        ldff1h  \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84df6000        ldff1h  \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    84df6000        ldff1h  \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    84df6000        ldff1h  \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    84a06000        ldff1h  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a06000        ldff1h  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a06000        ldff1h  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a06001        ldff1h  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a06001        ldff1h  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a06001        ldff1h  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a0601f        ldff1h  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a0601f        ldff1h  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a0601f        ldff1h  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a06800        ldff1h  \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a06800        ldff1h  \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a07c00        ldff1h  \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a07c00        ldff1h  \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a06060        ldff1h  \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\]
-.*:    84a06060        ldff1h  \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\]
-.*:    84a063e0        ldff1h  \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\]
-.*:    84a063e0        ldff1h  \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\]
-.*:    84a46000        ldff1h  \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\]
-.*:    84a46000        ldff1h  \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\]
-.*:    84bf6000        ldff1h  \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\]
-.*:    84bf6000        ldff1h  \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\]
-.*:    84e06000        ldff1h  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e06000        ldff1h  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e06000        ldff1h  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e06001        ldff1h  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e06001        ldff1h  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e06001        ldff1h  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e0601f        ldff1h  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e0601f        ldff1h  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e0601f        ldff1h  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e06800        ldff1h  \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e06800        ldff1h  \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e07c00        ldff1h  \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e07c00        ldff1h  \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e06060        ldff1h  \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\]
-.*:    84e06060        ldff1h  \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\]
-.*:    84e063e0        ldff1h  \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\]
-.*:    84e063e0        ldff1h  \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\]
-.*:    84e46000        ldff1h  \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\]
-.*:    84e46000        ldff1h  \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\]
-.*:    84ff6000        ldff1h  \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\]
-.*:    84ff6000        ldff1h  \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\]
-.*:    a4a06000        ldff1h  \{z0\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a06000        ldff1h  \{z0\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a06000        ldff1h  \{z0\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a06001        ldff1h  \{z1\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a06001        ldff1h  \{z1\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a06001        ldff1h  \{z1\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a0601f        ldff1h  \{z31\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a0601f        ldff1h  \{z31\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a0601f        ldff1h  \{z31\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4a06800        ldff1h  \{z0\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4a06800        ldff1h  \{z0\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4a07c00        ldff1h  \{z0\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4a07c00        ldff1h  \{z0\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4a06060        ldff1h  \{z0\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4a06060        ldff1h  \{z0\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4a063e0        ldff1h  \{z0\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4a063e0        ldff1h  \{z0\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4a46000        ldff1h  \{z0\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4a46000        ldff1h  \{z0\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4bf6000        ldff1h  \{z0\.h\}, p0/z, \[x0,xzr,lsl #1\]
-.*:    a4bf6000        ldff1h  \{z0\.h\}, p0/z, \[x0,xzr,lsl #1\]
-.*:    a4c06000        ldff1h  \{z0\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c06000        ldff1h  \{z0\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c06000        ldff1h  \{z0\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c06001        ldff1h  \{z1\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c06001        ldff1h  \{z1\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c06001        ldff1h  \{z1\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c0601f        ldff1h  \{z31\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c0601f        ldff1h  \{z31\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c0601f        ldff1h  \{z31\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4c06800        ldff1h  \{z0\.s\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4c06800        ldff1h  \{z0\.s\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4c07c00        ldff1h  \{z0\.s\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4c07c00        ldff1h  \{z0\.s\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4c06060        ldff1h  \{z0\.s\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4c06060        ldff1h  \{z0\.s\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4c063e0        ldff1h  \{z0\.s\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4c063e0        ldff1h  \{z0\.s\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4c46000        ldff1h  \{z0\.s\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4c46000        ldff1h  \{z0\.s\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4df6000        ldff1h  \{z0\.s\}, p0/z, \[x0,xzr,lsl #1\]
-.*:    a4df6000        ldff1h  \{z0\.s\}, p0/z, \[x0,xzr,lsl #1\]
-.*:    a4e06000        ldff1h  \{z0\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e06000        ldff1h  \{z0\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e06000        ldff1h  \{z0\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e06001        ldff1h  \{z1\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e06001        ldff1h  \{z1\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e06001        ldff1h  \{z1\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e0601f        ldff1h  \{z31\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e0601f        ldff1h  \{z31\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e0601f        ldff1h  \{z31\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a4e06800        ldff1h  \{z0\.d\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4e06800        ldff1h  \{z0\.d\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a4e07c00        ldff1h  \{z0\.d\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4e07c00        ldff1h  \{z0\.d\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a4e06060        ldff1h  \{z0\.d\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4e06060        ldff1h  \{z0\.d\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a4e063e0        ldff1h  \{z0\.d\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4e063e0        ldff1h  \{z0\.d\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a4e46000        ldff1h  \{z0\.d\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4e46000        ldff1h  \{z0\.d\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a4ff6000        ldff1h  \{z0\.d\}, p0/z, \[x0,xzr,lsl #1\]
-.*:    a4ff6000        ldff1h  \{z0\.d\}, p0/z, \[x0,xzr,lsl #1\]
-.*:    c4806000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4806000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4806000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4806000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4806001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4806001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4806001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4806001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480601f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480601f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480601f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480601f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4806800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4806800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4806800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4807c00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4807c00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4807c00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4806060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4806060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4806060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c48063e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c48063e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c48063e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c4846000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4846000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4846000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c49f6000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c49f6000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c49f6000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c4c06000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c06000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c06000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c06000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c06001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c06001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c06001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c06001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0601f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0601f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0601f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0601f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c06800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4c06800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4c06800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4c07c00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4c07c00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4c07c00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4c06060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4c06060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4c06060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4c063e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4c063e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4c063e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4c46000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4c46000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4c46000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4df6000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c4df6000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c4df6000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c4a06000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a06000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a06000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a06001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a06001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a06001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a0601f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a0601f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a0601f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a06800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a06800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a07c00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a07c00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a06060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\]
-.*:    c4a06060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\]
-.*:    c4a063e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\]
-.*:    c4a063e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\]
-.*:    c4a46000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\]
-.*:    c4a46000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\]
-.*:    c4bf6000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\]
-.*:    c4bf6000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\]
-.*:    c4e06000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e06000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e06000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e06001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e06001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e06001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e0601f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e0601f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e0601f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e06800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e06800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e07c00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e07c00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e06060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\]
-.*:    c4e06060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\]
-.*:    c4e063e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\]
-.*:    c4e063e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\]
-.*:    c4e46000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\]
-.*:    c4e46000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\]
-.*:    c4ff6000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\]
-.*:    c4ff6000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\]
-.*:    c4c0e000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0e000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0e000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0e000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0e001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0e001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0e001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0e001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0e01f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0e01f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0e01f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0e01f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0e800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4c0e800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4c0e800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4c0fc00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4c0fc00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4c0fc00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4c0e060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c4c0e060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c4c0e060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c4c0e3e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c4c0e3e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c4c0e3e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c4c4e000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c4c4e000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c4c4e000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c4dfe000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c4dfe000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c4dfe000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c4e0e000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0e000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0e000        ldff1h  \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0e001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0e001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0e001        ldff1h  \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0e01f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0e01f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0e01f        ldff1h  \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0e800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0e800        ldff1h  \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0fc00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0fc00        ldff1h  \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0e060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\]
-.*:    c4e0e060        ldff1h  \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\]
-.*:    c4e0e3e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\]
-.*:    c4e0e3e0        ldff1h  \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\]
-.*:    c4e4e000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\]
-.*:    c4e4e000        ldff1h  \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\]
-.*:    c4ffe000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\]
-.*:    c4ffe000        ldff1h  \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\]
+.*:    c5afe000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d, #120\]
+.*:    c5afe000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d, #120\]
+.*:    c5b0e000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d, #128\]
+.*:    c5b0e000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d, #128\]
+.*:    c5b1e000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d, #136\]
+.*:    c5b1e000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d, #136\]
+.*:    c5bfe000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d, #248\]
+.*:    c5bfe000        ldff1d  \{z0\.d\}, p0/z, \[z0\.d, #248\]
+.*:    84806000        ldff1h  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84806000        ldff1h  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84806000        ldff1h  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84806000        ldff1h  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84806001        ldff1h  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84806001        ldff1h  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84806001        ldff1h  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84806001        ldff1h  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480601f        ldff1h  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480601f        ldff1h  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480601f        ldff1h  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480601f        ldff1h  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84806800        ldff1h  \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84806800        ldff1h  \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84806800        ldff1h  \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84807c00        ldff1h  \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84807c00        ldff1h  \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84807c00        ldff1h  \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84806060        ldff1h  \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84806060        ldff1h  \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84806060        ldff1h  \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    848063e0        ldff1h  \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    848063e0        ldff1h  \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    848063e0        ldff1h  \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    84846000        ldff1h  \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84846000        ldff1h  \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84846000        ldff1h  \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    849f6000        ldff1h  \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    849f6000        ldff1h  \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    849f6000        ldff1h  \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    84c06000        ldff1h  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c06000        ldff1h  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c06000        ldff1h  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c06000        ldff1h  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c06001        ldff1h  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c06001        ldff1h  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c06001        ldff1h  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c06001        ldff1h  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0601f        ldff1h  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0601f        ldff1h  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0601f        ldff1h  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0601f        ldff1h  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c06800        ldff1h  \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84c06800        ldff1h  \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84c06800        ldff1h  \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84c07c00        ldff1h  \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84c07c00        ldff1h  \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84c07c00        ldff1h  \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84c06060        ldff1h  \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84c06060        ldff1h  \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84c06060        ldff1h  \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84c063e0        ldff1h  \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84c063e0        ldff1h  \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84c063e0        ldff1h  \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84c46000        ldff1h  \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84c46000        ldff1h  \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84c46000        ldff1h  \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84df6000        ldff1h  \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    84df6000        ldff1h  \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    84df6000        ldff1h  \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    84a06000        ldff1h  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a06000        ldff1h  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a06000        ldff1h  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a06001        ldff1h  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a06001        ldff1h  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a06001        ldff1h  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a0601f        ldff1h  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a0601f        ldff1h  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a0601f        ldff1h  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a06800        ldff1h  \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a06800        ldff1h  \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a07c00        ldff1h  \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a07c00        ldff1h  \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a06060        ldff1h  \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
+.*:    84a06060        ldff1h  \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
+.*:    84a063e0        ldff1h  \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
+.*:    84a063e0        ldff1h  \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
+.*:    84a46000        ldff1h  \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
+.*:    84a46000        ldff1h  \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
+.*:    84bf6000        ldff1h  \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
+.*:    84bf6000        ldff1h  \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
+.*:    84e06000        ldff1h  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e06000        ldff1h  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e06000        ldff1h  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e06001        ldff1h  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e06001        ldff1h  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e06001        ldff1h  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e0601f        ldff1h  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e0601f        ldff1h  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e0601f        ldff1h  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e06800        ldff1h  \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e06800        ldff1h  \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e07c00        ldff1h  \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e07c00        ldff1h  \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e06060        ldff1h  \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
+.*:    84e06060        ldff1h  \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
+.*:    84e063e0        ldff1h  \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
+.*:    84e063e0        ldff1h  \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
+.*:    84e46000        ldff1h  \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
+.*:    84e46000        ldff1h  \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
+.*:    84ff6000        ldff1h  \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
+.*:    84ff6000        ldff1h  \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
+.*:    a4a06000        ldff1h  \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a06000        ldff1h  \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a06000        ldff1h  \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a06001        ldff1h  \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a06001        ldff1h  \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a06001        ldff1h  \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a0601f        ldff1h  \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a0601f        ldff1h  \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a0601f        ldff1h  \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4a06800        ldff1h  \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4a06800        ldff1h  \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4a07c00        ldff1h  \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4a07c00        ldff1h  \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4a06060        ldff1h  \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4a06060        ldff1h  \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4a063e0        ldff1h  \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4a063e0        ldff1h  \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4a46000        ldff1h  \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4a46000        ldff1h  \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4bf6000        ldff1h  \{z0\.h\}, p0/z, \[x0, xzr, lsl #1\]
+.*:    a4bf6000        ldff1h  \{z0\.h\}, p0/z, \[x0, xzr, lsl #1\]
+.*:    a4c06000        ldff1h  \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c06000        ldff1h  \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c06000        ldff1h  \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c06001        ldff1h  \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c06001        ldff1h  \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c06001        ldff1h  \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c0601f        ldff1h  \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c0601f        ldff1h  \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c0601f        ldff1h  \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4c06800        ldff1h  \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4c06800        ldff1h  \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4c07c00        ldff1h  \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4c07c00        ldff1h  \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4c06060        ldff1h  \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4c06060        ldff1h  \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4c063e0        ldff1h  \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4c063e0        ldff1h  \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4c46000        ldff1h  \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4c46000        ldff1h  \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4df6000        ldff1h  \{z0\.s\}, p0/z, \[x0, xzr, lsl #1\]
+.*:    a4df6000        ldff1h  \{z0\.s\}, p0/z, \[x0, xzr, lsl #1\]
+.*:    a4e06000        ldff1h  \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e06000        ldff1h  \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e06000        ldff1h  \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e06001        ldff1h  \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e06001        ldff1h  \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e06001        ldff1h  \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e0601f        ldff1h  \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e0601f        ldff1h  \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e0601f        ldff1h  \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a4e06800        ldff1h  \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4e06800        ldff1h  \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a4e07c00        ldff1h  \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4e07c00        ldff1h  \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a4e06060        ldff1h  \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4e06060        ldff1h  \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a4e063e0        ldff1h  \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4e063e0        ldff1h  \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a4e46000        ldff1h  \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4e46000        ldff1h  \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a4ff6000        ldff1h  \{z0\.d\}, p0/z, \[x0, xzr, lsl #1\]
+.*:    a4ff6000        ldff1h  \{z0\.d\}, p0/z, \[x0, xzr, lsl #1\]
+.*:    c4806000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4806000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4806000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4806000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4806001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4806001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4806001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4806001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480601f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480601f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480601f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480601f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4806800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4806800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4806800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4807c00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4807c00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4807c00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4806060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4806060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4806060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c48063e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c48063e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c48063e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c4846000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4846000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4846000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c49f6000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c49f6000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c49f6000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c4c06000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c06000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c06000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c06000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c06001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c06001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c06001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c06001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0601f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0601f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0601f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0601f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c06800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4c06800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4c06800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4c07c00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4c07c00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4c07c00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4c06060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4c06060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4c06060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4c063e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4c063e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4c063e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4c46000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4c46000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4c46000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4df6000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c4df6000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c4df6000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c4a06000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a06000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a06000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a06001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a06001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a06001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a0601f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a0601f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a0601f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a06800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a06800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a07c00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a07c00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a06060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
+.*:    c4a06060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
+.*:    c4a063e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
+.*:    c4a063e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
+.*:    c4a46000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
+.*:    c4a46000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
+.*:    c4bf6000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
+.*:    c4bf6000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
+.*:    c4e06000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e06000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e06000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e06001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e06001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e06001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e0601f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e0601f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e0601f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e06800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e06800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e07c00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e07c00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e06060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
+.*:    c4e06060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
+.*:    c4e063e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
+.*:    c4e063e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
+.*:    c4e46000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
+.*:    c4e46000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
+.*:    c4ff6000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
+.*:    c4ff6000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
+.*:    c4c0e000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0e000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0e000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0e000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0e001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0e001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0e001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0e001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0e01f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0e01f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0e01f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0e01f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0e800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4c0e800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4c0e800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4c0fc00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4c0fc00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4c0fc00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4c0e060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c4c0e060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c4c0e060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c4c0e3e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c4c0e3e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c4c0e3e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c4c4e000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c4c4e000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c4c4e000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c4dfe000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c4dfe000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c4dfe000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c4e0e000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0e000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0e000        ldff1h  \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0e001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0e001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0e001        ldff1h  \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0e01f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0e01f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0e01f        ldff1h  \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0e800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0e800        ldff1h  \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0fc00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0fc00        ldff1h  \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0e060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
+.*:    c4e0e060        ldff1h  \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
+.*:    c4e0e3e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
+.*:    c4e0e3e0        ldff1h  \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
+.*:    c4e4e000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
+.*:    c4e4e000        ldff1h  \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
+.*:    c4ffe000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
+.*:    c4ffe000        ldff1h  \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
 .*:    84a0e000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    84a0e000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    84a0e000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s\]
@@ -17386,14 +17386,14 @@ Disassembly of section .*:
 .*:    84a0e3e0        ldff1h  \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    84a0e3e0        ldff1h  \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    84a0e3e0        ldff1h  \{z0\.s\}, p0/z, \[z31\.s\]
-.*:    84afe000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s,#30\]
-.*:    84afe000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s,#30\]
-.*:    84b0e000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s,#32\]
-.*:    84b0e000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s,#32\]
-.*:    84b1e000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s,#34\]
-.*:    84b1e000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s,#34\]
-.*:    84bfe000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s,#62\]
-.*:    84bfe000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s,#62\]
+.*:    84afe000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s, #30\]
+.*:    84afe000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s, #30\]
+.*:    84b0e000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s, #32\]
+.*:    84b0e000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s, #32\]
+.*:    84b1e000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s, #34\]
+.*:    84b1e000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s, #34\]
+.*:    84bfe000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s, #62\]
+.*:    84bfe000        ldff1h  \{z0\.s\}, p0/z, \[z0\.s, #62\]
 .*:    c4a0e000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c4a0e000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c4a0e000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d\]
@@ -17418,254 +17418,254 @@ Disassembly of section .*:
 .*:    c4a0e3e0        ldff1h  \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c4a0e3e0        ldff1h  \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c4a0e3e0        ldff1h  \{z0\.d\}, p0/z, \[z31\.d\]
-.*:    c4afe000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d,#30\]
-.*:    c4afe000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d,#30\]
-.*:    c4b0e000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d,#32\]
-.*:    c4b0e000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d,#32\]
-.*:    c4b1e000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d,#34\]
-.*:    c4b1e000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d,#34\]
-.*:    c4bfe000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d,#62\]
-.*:    c4bfe000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d,#62\]
-.*:    84002000        ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84002000        ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84002000        ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84002000        ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84002001        ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84002001        ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84002001        ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84002001        ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400201f        ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400201f        ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400201f        ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8400201f        ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84002800        ldff1sb \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84002800        ldff1sb \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84002800        ldff1sb \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84003c00        ldff1sb \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84003c00        ldff1sb \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84003c00        ldff1sb \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84002060        ldff1sb \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84002060        ldff1sb \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84002060        ldff1sb \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    840023e0        ldff1sb \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    840023e0        ldff1sb \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    840023e0        ldff1sb \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    84042000        ldff1sb \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84042000        ldff1sb \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84042000        ldff1sb \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    841f2000        ldff1sb \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    841f2000        ldff1sb \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    841f2000        ldff1sb \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    84402000        ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84402000        ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84402000        ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84402000        ldff1sb \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84402001        ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84402001        ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84402001        ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84402001        ldff1sb \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440201f        ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440201f        ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440201f        ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8440201f        ldff1sb \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84402800        ldff1sb \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84402800        ldff1sb \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84402800        ldff1sb \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84403c00        ldff1sb \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84403c00        ldff1sb \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84403c00        ldff1sb \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84402060        ldff1sb \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84402060        ldff1sb \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84402060        ldff1sb \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    844023e0        ldff1sb \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    844023e0        ldff1sb \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    844023e0        ldff1sb \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84442000        ldff1sb \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84442000        ldff1sb \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84442000        ldff1sb \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    845f2000        ldff1sb \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    845f2000        ldff1sb \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    845f2000        ldff1sb \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    a5806000        ldff1sb \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a5806000        ldff1sb \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a5806000        ldff1sb \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a5806000        ldff1sb \{z0\.d\}, p0/z, \[x0,x0\]
-.*:    a5806001        ldff1sb \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a5806001        ldff1sb \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a5806001        ldff1sb \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a5806001        ldff1sb \{z1\.d\}, p0/z, \[x0,x0\]
-.*:    a580601f        ldff1sb \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a580601f        ldff1sb \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a580601f        ldff1sb \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a580601f        ldff1sb \{z31\.d\}, p0/z, \[x0,x0\]
-.*:    a5806800        ldff1sb \{z0\.d\}, p2/z, \[x0,x0\]
-.*:    a5806800        ldff1sb \{z0\.d\}, p2/z, \[x0,x0\]
-.*:    a5806800        ldff1sb \{z0\.d\}, p2/z, \[x0,x0\]
-.*:    a5807c00        ldff1sb \{z0\.d\}, p7/z, \[x0,x0\]
-.*:    a5807c00        ldff1sb \{z0\.d\}, p7/z, \[x0,x0\]
-.*:    a5807c00        ldff1sb \{z0\.d\}, p7/z, \[x0,x0\]
-.*:    a5806060        ldff1sb \{z0\.d\}, p0/z, \[x3,x0\]
-.*:    a5806060        ldff1sb \{z0\.d\}, p0/z, \[x3,x0\]
-.*:    a5806060        ldff1sb \{z0\.d\}, p0/z, \[x3,x0\]
-.*:    a58063e0        ldff1sb \{z0\.d\}, p0/z, \[sp,x0\]
-.*:    a58063e0        ldff1sb \{z0\.d\}, p0/z, \[sp,x0\]
-.*:    a58063e0        ldff1sb \{z0\.d\}, p0/z, \[sp,x0\]
-.*:    a5846000        ldff1sb \{z0\.d\}, p0/z, \[x0,x4\]
-.*:    a5846000        ldff1sb \{z0\.d\}, p0/z, \[x0,x4\]
-.*:    a5846000        ldff1sb \{z0\.d\}, p0/z, \[x0,x4\]
-.*:    a59f6000        ldff1sb \{z0\.d\}, p0/z, \[x0,xzr\]
-.*:    a59f6000        ldff1sb \{z0\.d\}, p0/z, \[x0,xzr\]
-.*:    a59f6000        ldff1sb \{z0\.d\}, p0/z, \[x0,xzr\]
-.*:    a5a06000        ldff1sb \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a5a06000        ldff1sb \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a5a06000        ldff1sb \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a5a06000        ldff1sb \{z0\.s\}, p0/z, \[x0,x0\]
-.*:    a5a06001        ldff1sb \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a5a06001        ldff1sb \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a5a06001        ldff1sb \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a5a06001        ldff1sb \{z1\.s\}, p0/z, \[x0,x0\]
-.*:    a5a0601f        ldff1sb \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a5a0601f        ldff1sb \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a5a0601f        ldff1sb \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a5a0601f        ldff1sb \{z31\.s\}, p0/z, \[x0,x0\]
-.*:    a5a06800        ldff1sb \{z0\.s\}, p2/z, \[x0,x0\]
-.*:    a5a06800        ldff1sb \{z0\.s\}, p2/z, \[x0,x0\]
-.*:    a5a06800        ldff1sb \{z0\.s\}, p2/z, \[x0,x0\]
-.*:    a5a07c00        ldff1sb \{z0\.s\}, p7/z, \[x0,x0\]
-.*:    a5a07c00        ldff1sb \{z0\.s\}, p7/z, \[x0,x0\]
-.*:    a5a07c00        ldff1sb \{z0\.s\}, p7/z, \[x0,x0\]
-.*:    a5a06060        ldff1sb \{z0\.s\}, p0/z, \[x3,x0\]
-.*:    a5a06060        ldff1sb \{z0\.s\}, p0/z, \[x3,x0\]
-.*:    a5a06060        ldff1sb \{z0\.s\}, p0/z, \[x3,x0\]
-.*:    a5a063e0        ldff1sb \{z0\.s\}, p0/z, \[sp,x0\]
-.*:    a5a063e0        ldff1sb \{z0\.s\}, p0/z, \[sp,x0\]
-.*:    a5a063e0        ldff1sb \{z0\.s\}, p0/z, \[sp,x0\]
-.*:    a5a46000        ldff1sb \{z0\.s\}, p0/z, \[x0,x4\]
-.*:    a5a46000        ldff1sb \{z0\.s\}, p0/z, \[x0,x4\]
-.*:    a5a46000        ldff1sb \{z0\.s\}, p0/z, \[x0,x4\]
-.*:    a5bf6000        ldff1sb \{z0\.s\}, p0/z, \[x0,xzr\]
-.*:    a5bf6000        ldff1sb \{z0\.s\}, p0/z, \[x0,xzr\]
-.*:    a5bf6000        ldff1sb \{z0\.s\}, p0/z, \[x0,xzr\]
-.*:    a5c06000        ldff1sb \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a5c06000        ldff1sb \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a5c06000        ldff1sb \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a5c06000        ldff1sb \{z0\.h\}, p0/z, \[x0,x0\]
-.*:    a5c06001        ldff1sb \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a5c06001        ldff1sb \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a5c06001        ldff1sb \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a5c06001        ldff1sb \{z1\.h\}, p0/z, \[x0,x0\]
-.*:    a5c0601f        ldff1sb \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a5c0601f        ldff1sb \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a5c0601f        ldff1sb \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a5c0601f        ldff1sb \{z31\.h\}, p0/z, \[x0,x0\]
-.*:    a5c06800        ldff1sb \{z0\.h\}, p2/z, \[x0,x0\]
-.*:    a5c06800        ldff1sb \{z0\.h\}, p2/z, \[x0,x0\]
-.*:    a5c06800        ldff1sb \{z0\.h\}, p2/z, \[x0,x0\]
-.*:    a5c07c00        ldff1sb \{z0\.h\}, p7/z, \[x0,x0\]
-.*:    a5c07c00        ldff1sb \{z0\.h\}, p7/z, \[x0,x0\]
-.*:    a5c07c00        ldff1sb \{z0\.h\}, p7/z, \[x0,x0\]
-.*:    a5c06060        ldff1sb \{z0\.h\}, p0/z, \[x3,x0\]
-.*:    a5c06060        ldff1sb \{z0\.h\}, p0/z, \[x3,x0\]
-.*:    a5c06060        ldff1sb \{z0\.h\}, p0/z, \[x3,x0\]
-.*:    a5c063e0        ldff1sb \{z0\.h\}, p0/z, \[sp,x0\]
-.*:    a5c063e0        ldff1sb \{z0\.h\}, p0/z, \[sp,x0\]
-.*:    a5c063e0        ldff1sb \{z0\.h\}, p0/z, \[sp,x0\]
-.*:    a5c46000        ldff1sb \{z0\.h\}, p0/z, \[x0,x4\]
-.*:    a5c46000        ldff1sb \{z0\.h\}, p0/z, \[x0,x4\]
-.*:    a5c46000        ldff1sb \{z0\.h\}, p0/z, \[x0,x4\]
-.*:    a5df6000        ldff1sb \{z0\.h\}, p0/z, \[x0,xzr\]
-.*:    a5df6000        ldff1sb \{z0\.h\}, p0/z, \[x0,xzr\]
-.*:    a5df6000        ldff1sb \{z0\.h\}, p0/z, \[x0,xzr\]
-.*:    c4002000        ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4002000        ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4002000        ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4002000        ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4002001        ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4002001        ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4002001        ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4002001        ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400201f        ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400201f        ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400201f        ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c400201f        ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4002800        ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4002800        ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4002800        ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4003c00        ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4003c00        ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4003c00        ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4002060        ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4002060        ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4002060        ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c40023e0        ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c40023e0        ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c40023e0        ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c4042000        ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4042000        ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4042000        ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c41f2000        ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c41f2000        ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c41f2000        ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c4402000        ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4402000        ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4402000        ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4402000        ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4402001        ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4402001        ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4402001        ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4402001        ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440201f        ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440201f        ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440201f        ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c440201f        ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4402800        ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4402800        ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4402800        ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4403c00        ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4403c00        ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4403c00        ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4402060        ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4402060        ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4402060        ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c44023e0        ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c44023e0        ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c44023e0        ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4442000        ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4442000        ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4442000        ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c45f2000        ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c45f2000        ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c45f2000        ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c440a000        ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440a000        ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440a000        ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440a000        ldff1sb \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440a001        ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440a001        ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440a001        ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440a001        ldff1sb \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440a01f        ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440a01f        ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440a01f        ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440a01f        ldff1sb \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c440a800        ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c440a800        ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c440a800        ldff1sb \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c440bc00        ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c440bc00        ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c440bc00        ldff1sb \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c440a060        ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c440a060        ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c440a060        ldff1sb \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c440a3e0        ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c440a3e0        ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c440a3e0        ldff1sb \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c444a000        ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c444a000        ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c444a000        ldff1sb \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c45fa000        ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c45fa000        ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c45fa000        ldff1sb \{z0\.d\}, p0/z, \[x0,z31\.d\]
+.*:    c4afe000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d, #30\]
+.*:    c4afe000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d, #30\]
+.*:    c4b0e000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d, #32\]
+.*:    c4b0e000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d, #32\]
+.*:    c4b1e000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d, #34\]
+.*:    c4b1e000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d, #34\]
+.*:    c4bfe000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d, #62\]
+.*:    c4bfe000        ldff1h  \{z0\.d\}, p0/z, \[z0\.d, #62\]
+.*:    84002000        ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84002000        ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84002000        ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84002000        ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84002001        ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84002001        ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84002001        ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84002001        ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400201f        ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400201f        ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400201f        ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8400201f        ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84002800        ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84002800        ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84002800        ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84003c00        ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84003c00        ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84003c00        ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84002060        ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84002060        ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84002060        ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    840023e0        ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    840023e0        ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    840023e0        ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    84042000        ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84042000        ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84042000        ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    841f2000        ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    841f2000        ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    841f2000        ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    84402000        ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84402000        ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84402000        ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84402000        ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84402001        ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84402001        ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84402001        ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84402001        ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440201f        ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440201f        ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440201f        ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8440201f        ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84402800        ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84402800        ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84402800        ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84403c00        ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84403c00        ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84403c00        ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84402060        ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84402060        ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84402060        ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    844023e0        ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    844023e0        ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    844023e0        ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84442000        ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84442000        ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84442000        ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    845f2000        ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    845f2000        ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    845f2000        ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    a5806000        ldff1sb \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a5806000        ldff1sb \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a5806000        ldff1sb \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a5806000        ldff1sb \{z0\.d\}, p0/z, \[x0, x0\]
+.*:    a5806001        ldff1sb \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a5806001        ldff1sb \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a5806001        ldff1sb \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a5806001        ldff1sb \{z1\.d\}, p0/z, \[x0, x0\]
+.*:    a580601f        ldff1sb \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a580601f        ldff1sb \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a580601f        ldff1sb \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a580601f        ldff1sb \{z31\.d\}, p0/z, \[x0, x0\]
+.*:    a5806800        ldff1sb \{z0\.d\}, p2/z, \[x0, x0\]
+.*:    a5806800        ldff1sb \{z0\.d\}, p2/z, \[x0, x0\]
+.*:    a5806800        ldff1sb \{z0\.d\}, p2/z, \[x0, x0\]
+.*:    a5807c00        ldff1sb \{z0\.d\}, p7/z, \[x0, x0\]
+.*:    a5807c00        ldff1sb \{z0\.d\}, p7/z, \[x0, x0\]
+.*:    a5807c00        ldff1sb \{z0\.d\}, p7/z, \[x0, x0\]
+.*:    a5806060        ldff1sb \{z0\.d\}, p0/z, \[x3, x0\]
+.*:    a5806060        ldff1sb \{z0\.d\}, p0/z, \[x3, x0\]
+.*:    a5806060        ldff1sb \{z0\.d\}, p0/z, \[x3, x0\]
+.*:    a58063e0        ldff1sb \{z0\.d\}, p0/z, \[sp, x0\]
+.*:    a58063e0        ldff1sb \{z0\.d\}, p0/z, \[sp, x0\]
+.*:    a58063e0        ldff1sb \{z0\.d\}, p0/z, \[sp, x0\]
+.*:    a5846000        ldff1sb \{z0\.d\}, p0/z, \[x0, x4\]
+.*:    a5846000        ldff1sb \{z0\.d\}, p0/z, \[x0, x4\]
+.*:    a5846000        ldff1sb \{z0\.d\}, p0/z, \[x0, x4\]
+.*:    a59f6000        ldff1sb \{z0\.d\}, p0/z, \[x0, xzr\]
+.*:    a59f6000        ldff1sb \{z0\.d\}, p0/z, \[x0, xzr\]
+.*:    a59f6000        ldff1sb \{z0\.d\}, p0/z, \[x0, xzr\]
+.*:    a5a06000        ldff1sb \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a5a06000        ldff1sb \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a5a06000        ldff1sb \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a5a06000        ldff1sb \{z0\.s\}, p0/z, \[x0, x0\]
+.*:    a5a06001        ldff1sb \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a5a06001        ldff1sb \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a5a06001        ldff1sb \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a5a06001        ldff1sb \{z1\.s\}, p0/z, \[x0, x0\]
+.*:    a5a0601f        ldff1sb \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a5a0601f        ldff1sb \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a5a0601f        ldff1sb \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a5a0601f        ldff1sb \{z31\.s\}, p0/z, \[x0, x0\]
+.*:    a5a06800        ldff1sb \{z0\.s\}, p2/z, \[x0, x0\]
+.*:    a5a06800        ldff1sb \{z0\.s\}, p2/z, \[x0, x0\]
+.*:    a5a06800        ldff1sb \{z0\.s\}, p2/z, \[x0, x0\]
+.*:    a5a07c00        ldff1sb \{z0\.s\}, p7/z, \[x0, x0\]
+.*:    a5a07c00        ldff1sb \{z0\.s\}, p7/z, \[x0, x0\]
+.*:    a5a07c00        ldff1sb \{z0\.s\}, p7/z, \[x0, x0\]
+.*:    a5a06060        ldff1sb \{z0\.s\}, p0/z, \[x3, x0\]
+.*:    a5a06060        ldff1sb \{z0\.s\}, p0/z, \[x3, x0\]
+.*:    a5a06060        ldff1sb \{z0\.s\}, p0/z, \[x3, x0\]
+.*:    a5a063e0        ldff1sb \{z0\.s\}, p0/z, \[sp, x0\]
+.*:    a5a063e0        ldff1sb \{z0\.s\}, p0/z, \[sp, x0\]
+.*:    a5a063e0        ldff1sb \{z0\.s\}, p0/z, \[sp, x0\]
+.*:    a5a46000        ldff1sb \{z0\.s\}, p0/z, \[x0, x4\]
+.*:    a5a46000        ldff1sb \{z0\.s\}, p0/z, \[x0, x4\]
+.*:    a5a46000        ldff1sb \{z0\.s\}, p0/z, \[x0, x4\]
+.*:    a5bf6000        ldff1sb \{z0\.s\}, p0/z, \[x0, xzr\]
+.*:    a5bf6000        ldff1sb \{z0\.s\}, p0/z, \[x0, xzr\]
+.*:    a5bf6000        ldff1sb \{z0\.s\}, p0/z, \[x0, xzr\]
+.*:    a5c06000        ldff1sb \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a5c06000        ldff1sb \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a5c06000        ldff1sb \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a5c06000        ldff1sb \{z0\.h\}, p0/z, \[x0, x0\]
+.*:    a5c06001        ldff1sb \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a5c06001        ldff1sb \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a5c06001        ldff1sb \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a5c06001        ldff1sb \{z1\.h\}, p0/z, \[x0, x0\]
+.*:    a5c0601f        ldff1sb \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a5c0601f        ldff1sb \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a5c0601f        ldff1sb \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a5c0601f        ldff1sb \{z31\.h\}, p0/z, \[x0, x0\]
+.*:    a5c06800        ldff1sb \{z0\.h\}, p2/z, \[x0, x0\]
+.*:    a5c06800        ldff1sb \{z0\.h\}, p2/z, \[x0, x0\]
+.*:    a5c06800        ldff1sb \{z0\.h\}, p2/z, \[x0, x0\]
+.*:    a5c07c00        ldff1sb \{z0\.h\}, p7/z, \[x0, x0\]
+.*:    a5c07c00        ldff1sb \{z0\.h\}, p7/z, \[x0, x0\]
+.*:    a5c07c00        ldff1sb \{z0\.h\}, p7/z, \[x0, x0\]
+.*:    a5c06060        ldff1sb \{z0\.h\}, p0/z, \[x3, x0\]
+.*:    a5c06060        ldff1sb \{z0\.h\}, p0/z, \[x3, x0\]
+.*:    a5c06060        ldff1sb \{z0\.h\}, p0/z, \[x3, x0\]
+.*:    a5c063e0        ldff1sb \{z0\.h\}, p0/z, \[sp, x0\]
+.*:    a5c063e0        ldff1sb \{z0\.h\}, p0/z, \[sp, x0\]
+.*:    a5c063e0        ldff1sb \{z0\.h\}, p0/z, \[sp, x0\]
+.*:    a5c46000        ldff1sb \{z0\.h\}, p0/z, \[x0, x4\]
+.*:    a5c46000        ldff1sb \{z0\.h\}, p0/z, \[x0, x4\]
+.*:    a5c46000        ldff1sb \{z0\.h\}, p0/z, \[x0, x4\]
+.*:    a5df6000        ldff1sb \{z0\.h\}, p0/z, \[x0, xzr\]
+.*:    a5df6000        ldff1sb \{z0\.h\}, p0/z, \[x0, xzr\]
+.*:    a5df6000        ldff1sb \{z0\.h\}, p0/z, \[x0, xzr\]
+.*:    c4002000        ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4002000        ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4002000        ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4002000        ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4002001        ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4002001        ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4002001        ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4002001        ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400201f        ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400201f        ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400201f        ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c400201f        ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4002800        ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4002800        ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4002800        ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4003c00        ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4003c00        ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4003c00        ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4002060        ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4002060        ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4002060        ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c40023e0        ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c40023e0        ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c40023e0        ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c4042000        ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4042000        ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4042000        ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c41f2000        ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c41f2000        ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c41f2000        ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c4402000        ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4402000        ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4402000        ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4402000        ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4402001        ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4402001        ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4402001        ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4402001        ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440201f        ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440201f        ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440201f        ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c440201f        ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4402800        ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4402800        ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4402800        ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4403c00        ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4403c00        ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4403c00        ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4402060        ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4402060        ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4402060        ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c44023e0        ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c44023e0        ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c44023e0        ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4442000        ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4442000        ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4442000        ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c45f2000        ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c45f2000        ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c45f2000        ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c440a000        ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440a000        ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440a000        ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440a000        ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440a001        ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440a001        ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440a001        ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440a001        ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440a01f        ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440a01f        ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440a01f        ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440a01f        ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c440a800        ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c440a800        ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c440a800        ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c440bc00        ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c440bc00        ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c440bc00        ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c440a060        ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c440a060        ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c440a060        ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c440a3e0        ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c440a3e0        ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c440a3e0        ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c444a000        ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c444a000        ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c444a000        ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c45fa000        ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c45fa000        ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c45fa000        ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d\]
 .*:    8420a000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    8420a000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    8420a000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s\]
@@ -17690,14 +17690,14 @@ Disassembly of section .*:
 .*:    8420a3e0        ldff1sb \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    8420a3e0        ldff1sb \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    8420a3e0        ldff1sb \{z0\.s\}, p0/z, \[z31\.s\]
-.*:    842fa000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#15\]
-.*:    842fa000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#15\]
-.*:    8430a000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#16\]
-.*:    8430a000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#16\]
-.*:    8431a000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#17\]
-.*:    8431a000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#17\]
-.*:    843fa000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#31\]
-.*:    843fa000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s,#31\]
+.*:    842fa000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #15\]
+.*:    842fa000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #15\]
+.*:    8430a000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #16\]
+.*:    8430a000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #16\]
+.*:    8431a000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #17\]
+.*:    8431a000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #17\]
+.*:    843fa000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #31\]
+.*:    843fa000        ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #31\]
 .*:    c420a000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c420a000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c420a000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d\]
@@ -17722,311 +17722,311 @@ Disassembly of section .*:
 .*:    c420a3e0        ldff1sb \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c420a3e0        ldff1sb \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c420a3e0        ldff1sb \{z0\.d\}, p0/z, \[z31\.d\]
-.*:    c42fa000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#15\]
-.*:    c42fa000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#15\]
-.*:    c430a000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#16\]
-.*:    c430a000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#16\]
-.*:    c431a000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#17\]
-.*:    c431a000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#17\]
-.*:    c43fa000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#31\]
-.*:    c43fa000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d,#31\]
-.*:    84802000        ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84802000        ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84802000        ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84802000        ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84802001        ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84802001        ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84802001        ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84802001        ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480201f        ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480201f        ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480201f        ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8480201f        ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    84802800        ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84802800        ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84802800        ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    84803c00        ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84803c00        ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84803c00        ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    84802060        ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84802060        ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    84802060        ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    848023e0        ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    848023e0        ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    848023e0        ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    84842000        ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84842000        ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    84842000        ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    849f2000        ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    849f2000        ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    849f2000        ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    84c02000        ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c02000        ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c02000        ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c02000        ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c02001        ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c02001        ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c02001        ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c02001        ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0201f        ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0201f        ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0201f        ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c0201f        ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    84c02800        ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84c02800        ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84c02800        ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    84c03c00        ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84c03c00        ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84c03c00        ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    84c02060        ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84c02060        ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84c02060        ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    84c023e0        ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84c023e0        ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84c023e0        ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    84c42000        ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84c42000        ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84c42000        ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    84df2000        ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    84df2000        ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    84df2000        ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    84a02000        ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a02000        ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a02000        ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a02001        ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a02001        ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a02001        ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a0201f        ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a0201f        ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a0201f        ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a02800        ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a02800        ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a03c00        ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a03c00        ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #1\]
-.*:    84a02060        ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\]
-.*:    84a02060        ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #1\]
-.*:    84a023e0        ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\]
-.*:    84a023e0        ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #1\]
-.*:    84a42000        ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\]
-.*:    84a42000        ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #1\]
-.*:    84bf2000        ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\]
-.*:    84bf2000        ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #1\]
-.*:    84e02000        ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e02000        ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e02000        ldff1sh \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e02001        ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e02001        ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e02001        ldff1sh \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e0201f        ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e0201f        ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e0201f        ldff1sh \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e02800        ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e02800        ldff1sh \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e03c00        ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e03c00        ldff1sh \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #1\]
-.*:    84e02060        ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\]
-.*:    84e02060        ldff1sh \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #1\]
-.*:    84e023e0        ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\]
-.*:    84e023e0        ldff1sh \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #1\]
-.*:    84e42000        ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\]
-.*:    84e42000        ldff1sh \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #1\]
-.*:    84ff2000        ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\]
-.*:    84ff2000        ldff1sh \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #1\]
-.*:    a5006000        ldff1sh \{z0\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5006000        ldff1sh \{z0\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5006000        ldff1sh \{z0\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5006001        ldff1sh \{z1\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5006001        ldff1sh \{z1\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5006001        ldff1sh \{z1\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a500601f        ldff1sh \{z31\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a500601f        ldff1sh \{z31\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a500601f        ldff1sh \{z31\.d\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5006800        ldff1sh \{z0\.d\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a5006800        ldff1sh \{z0\.d\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a5007c00        ldff1sh \{z0\.d\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a5007c00        ldff1sh \{z0\.d\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a5006060        ldff1sh \{z0\.d\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a5006060        ldff1sh \{z0\.d\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a50063e0        ldff1sh \{z0\.d\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a50063e0        ldff1sh \{z0\.d\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a5046000        ldff1sh \{z0\.d\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a5046000        ldff1sh \{z0\.d\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a51f6000        ldff1sh \{z0\.d\}, p0/z, \[x0,xzr,lsl #1\]
-.*:    a51f6000        ldff1sh \{z0\.d\}, p0/z, \[x0,xzr,lsl #1\]
-.*:    a5206000        ldff1sh \{z0\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5206000        ldff1sh \{z0\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5206000        ldff1sh \{z0\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5206001        ldff1sh \{z1\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5206001        ldff1sh \{z1\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5206001        ldff1sh \{z1\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a520601f        ldff1sh \{z31\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a520601f        ldff1sh \{z31\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a520601f        ldff1sh \{z31\.s\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a5206800        ldff1sh \{z0\.s\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a5206800        ldff1sh \{z0\.s\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a5207c00        ldff1sh \{z0\.s\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a5207c00        ldff1sh \{z0\.s\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a5206060        ldff1sh \{z0\.s\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a5206060        ldff1sh \{z0\.s\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a52063e0        ldff1sh \{z0\.s\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a52063e0        ldff1sh \{z0\.s\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a5246000        ldff1sh \{z0\.s\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a5246000        ldff1sh \{z0\.s\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a53f6000        ldff1sh \{z0\.s\}, p0/z, \[x0,xzr,lsl #1\]
-.*:    a53f6000        ldff1sh \{z0\.s\}, p0/z, \[x0,xzr,lsl #1\]
-.*:    c4802000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4802000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4802000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4802000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4802001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4802001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4802001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4802001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480201f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480201f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480201f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c480201f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c4802800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4802800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4802800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c4803c00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4803c00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4803c00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c4802060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4802060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c4802060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c48023e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c48023e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c48023e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c4842000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4842000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c4842000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c49f2000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c49f2000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c49f2000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c4c02000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c02000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c02000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c02000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c02001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c02001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c02001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c02001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0201f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0201f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0201f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c0201f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c4c02800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4c02800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4c02800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c4c03c00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4c03c00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4c03c00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c4c02060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4c02060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4c02060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c4c023e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4c023e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4c023e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c4c42000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4c42000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4c42000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c4df2000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c4df2000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c4df2000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c4a02000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a02000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a02000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a02001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a02001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a02001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a0201f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a0201f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a0201f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a02800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a02800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a03c00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a03c00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #1\]
-.*:    c4a02060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\]
-.*:    c4a02060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #1\]
-.*:    c4a023e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\]
-.*:    c4a023e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #1\]
-.*:    c4a42000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\]
-.*:    c4a42000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #1\]
-.*:    c4bf2000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\]
-.*:    c4bf2000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #1\]
-.*:    c4e02000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e02000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e02000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e02001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e02001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e02001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e0201f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e0201f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e0201f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e02800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e02800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e03c00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e03c00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #1\]
-.*:    c4e02060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\]
-.*:    c4e02060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #1\]
-.*:    c4e023e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\]
-.*:    c4e023e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #1\]
-.*:    c4e42000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\]
-.*:    c4e42000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #1\]
-.*:    c4ff2000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\]
-.*:    c4ff2000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #1\]
-.*:    c4c0a000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0a000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0a000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0a000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0a001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0a001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0a001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0a001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0a01f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0a01f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0a01f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0a01f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c4c0a800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4c0a800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4c0a800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c4c0bc00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4c0bc00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4c0bc00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c4c0a060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c4c0a060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c4c0a060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c4c0a3e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c4c0a3e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c4c0a3e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c4c4a000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c4c4a000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c4c4a000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c4dfa000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c4dfa000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c4dfa000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c4e0a000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0a000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0a000        ldff1sh \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0a001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0a001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0a001        ldff1sh \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0a01f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0a01f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0a01f        ldff1sh \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0a800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0a800        ldff1sh \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0bc00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0bc00        ldff1sh \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #1\]
-.*:    c4e0a060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\]
-.*:    c4e0a060        ldff1sh \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #1\]
-.*:    c4e0a3e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\]
-.*:    c4e0a3e0        ldff1sh \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #1\]
-.*:    c4e4a000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\]
-.*:    c4e4a000        ldff1sh \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #1\]
-.*:    c4ffa000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\]
-.*:    c4ffa000        ldff1sh \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #1\]
+.*:    c42fa000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #15\]
+.*:    c42fa000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #15\]
+.*:    c430a000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #16\]
+.*:    c430a000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #16\]
+.*:    c431a000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #17\]
+.*:    c431a000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #17\]
+.*:    c43fa000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #31\]
+.*:    c43fa000        ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #31\]
+.*:    84802000        ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84802000        ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84802000        ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84802000        ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84802001        ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84802001        ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84802001        ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84802001        ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480201f        ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480201f        ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480201f        ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8480201f        ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    84802800        ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84802800        ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84802800        ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    84803c00        ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84803c00        ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84803c00        ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    84802060        ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84802060        ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    84802060        ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    848023e0        ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    848023e0        ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    848023e0        ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    84842000        ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84842000        ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    84842000        ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    849f2000        ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    849f2000        ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    849f2000        ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    84c02000        ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c02000        ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c02000        ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c02000        ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c02001        ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c02001        ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c02001        ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c02001        ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0201f        ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0201f        ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0201f        ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c0201f        ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    84c02800        ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84c02800        ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84c02800        ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    84c03c00        ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84c03c00        ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84c03c00        ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    84c02060        ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84c02060        ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84c02060        ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    84c023e0        ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84c023e0        ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84c023e0        ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    84c42000        ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84c42000        ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84c42000        ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    84df2000        ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    84df2000        ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    84df2000        ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    84a02000        ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a02000        ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a02000        ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a02001        ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a02001        ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a02001        ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a0201f        ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a0201f        ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a0201f        ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a02800        ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a02800        ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a03c00        ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a03c00        ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
+.*:    84a02060        ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
+.*:    84a02060        ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
+.*:    84a023e0        ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
+.*:    84a023e0        ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
+.*:    84a42000        ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
+.*:    84a42000        ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
+.*:    84bf2000        ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
+.*:    84bf2000        ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
+.*:    84e02000        ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e02000        ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e02000        ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e02001        ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e02001        ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e02001        ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e0201f        ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e0201f        ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e0201f        ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e02800        ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e02800        ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e03c00        ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e03c00        ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
+.*:    84e02060        ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
+.*:    84e02060        ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
+.*:    84e023e0        ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
+.*:    84e023e0        ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
+.*:    84e42000        ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
+.*:    84e42000        ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
+.*:    84ff2000        ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
+.*:    84ff2000        ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
+.*:    a5006000        ldff1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5006000        ldff1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5006000        ldff1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5006001        ldff1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5006001        ldff1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5006001        ldff1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a500601f        ldff1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a500601f        ldff1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a500601f        ldff1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5006800        ldff1sh \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a5006800        ldff1sh \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a5007c00        ldff1sh \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a5007c00        ldff1sh \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a5006060        ldff1sh \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a5006060        ldff1sh \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a50063e0        ldff1sh \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a50063e0        ldff1sh \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a5046000        ldff1sh \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a5046000        ldff1sh \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a51f6000        ldff1sh \{z0\.d\}, p0/z, \[x0, xzr, lsl #1\]
+.*:    a51f6000        ldff1sh \{z0\.d\}, p0/z, \[x0, xzr, lsl #1\]
+.*:    a5206000        ldff1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5206000        ldff1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5206000        ldff1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5206001        ldff1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5206001        ldff1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5206001        ldff1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a520601f        ldff1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a520601f        ldff1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a520601f        ldff1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a5206800        ldff1sh \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a5206800        ldff1sh \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a5207c00        ldff1sh \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a5207c00        ldff1sh \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a5206060        ldff1sh \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a5206060        ldff1sh \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a52063e0        ldff1sh \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a52063e0        ldff1sh \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a5246000        ldff1sh \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a5246000        ldff1sh \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a53f6000        ldff1sh \{z0\.s\}, p0/z, \[x0, xzr, lsl #1\]
+.*:    a53f6000        ldff1sh \{z0\.s\}, p0/z, \[x0, xzr, lsl #1\]
+.*:    c4802000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4802000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4802000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4802000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4802001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4802001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4802001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4802001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480201f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480201f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480201f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c480201f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c4802800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4802800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4802800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c4803c00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4803c00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4803c00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c4802060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4802060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c4802060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c48023e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c48023e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c48023e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c4842000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4842000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c4842000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c49f2000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c49f2000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c49f2000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c4c02000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c02000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c02000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c02000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c02001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c02001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c02001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c02001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0201f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0201f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0201f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c0201f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c4c02800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4c02800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4c02800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c4c03c00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4c03c00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4c03c00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c4c02060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4c02060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4c02060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c4c023e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4c023e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4c023e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c4c42000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4c42000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4c42000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c4df2000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c4df2000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c4df2000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c4a02000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a02000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a02000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a02001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a02001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a02001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a0201f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a0201f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a0201f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a02800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a02800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a03c00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a03c00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
+.*:    c4a02060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
+.*:    c4a02060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
+.*:    c4a023e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
+.*:    c4a023e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
+.*:    c4a42000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
+.*:    c4a42000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
+.*:    c4bf2000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
+.*:    c4bf2000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
+.*:    c4e02000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e02000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e02000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e02001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e02001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e02001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e0201f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e0201f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e0201f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e02800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e02800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e03c00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e03c00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
+.*:    c4e02060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
+.*:    c4e02060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
+.*:    c4e023e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
+.*:    c4e023e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
+.*:    c4e42000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
+.*:    c4e42000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
+.*:    c4ff2000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
+.*:    c4ff2000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
+.*:    c4c0a000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0a000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0a000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0a000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0a001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0a001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0a001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0a001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0a01f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0a01f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0a01f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0a01f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c4c0a800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4c0a800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4c0a800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c4c0bc00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4c0bc00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4c0bc00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c4c0a060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c4c0a060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c4c0a060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c4c0a3e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c4c0a3e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c4c0a3e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c4c4a000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c4c4a000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c4c4a000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c4dfa000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c4dfa000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c4dfa000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c4e0a000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0a000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0a000        ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0a001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0a001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0a001        ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0a01f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0a01f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0a01f        ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0a800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0a800        ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0bc00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0bc00        ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
+.*:    c4e0a060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
+.*:    c4e0a060        ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
+.*:    c4e0a3e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
+.*:    c4e0a3e0        ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
+.*:    c4e4a000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
+.*:    c4e4a000        ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
+.*:    c4ffa000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
+.*:    c4ffa000        ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
 .*:    84a0a000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    84a0a000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    84a0a000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s\]
@@ -18051,14 +18051,14 @@ Disassembly of section .*:
 .*:    84a0a3e0        ldff1sh \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    84a0a3e0        ldff1sh \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    84a0a3e0        ldff1sh \{z0\.s\}, p0/z, \[z31\.s\]
-.*:    84afa000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#30\]
-.*:    84afa000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#30\]
-.*:    84b0a000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#32\]
-.*:    84b0a000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#32\]
-.*:    84b1a000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#34\]
-.*:    84b1a000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#34\]
-.*:    84bfa000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#62\]
-.*:    84bfa000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s,#62\]
+.*:    84afa000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #30\]
+.*:    84afa000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #30\]
+.*:    84b0a000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #32\]
+.*:    84b0a000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #32\]
+.*:    84b1a000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #34\]
+.*:    84b1a000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #34\]
+.*:    84bfa000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #62\]
+.*:    84bfa000        ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #62\]
 .*:    c4a0a000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c4a0a000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c4a0a000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d\]
@@ -18083,188 +18083,188 @@ Disassembly of section .*:
 .*:    c4a0a3e0        ldff1sh \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c4a0a3e0        ldff1sh \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c4a0a3e0        ldff1sh \{z0\.d\}, p0/z, \[z31\.d\]
-.*:    c4afa000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#30\]
-.*:    c4afa000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#30\]
-.*:    c4b0a000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#32\]
-.*:    c4b0a000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#32\]
-.*:    c4b1a000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#34\]
-.*:    c4b1a000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#34\]
-.*:    c4bfa000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#62\]
-.*:    c4bfa000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d,#62\]
-.*:    a4806000        ldff1sw \{z0\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a4806000        ldff1sw \{z0\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a4806000        ldff1sw \{z0\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a4806001        ldff1sw \{z1\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a4806001        ldff1sw \{z1\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a4806001        ldff1sw \{z1\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a480601f        ldff1sw \{z31\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a480601f        ldff1sw \{z31\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a480601f        ldff1sw \{z31\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a4806800        ldff1sw \{z0\.d\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a4806800        ldff1sw \{z0\.d\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a4807c00        ldff1sw \{z0\.d\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a4807c00        ldff1sw \{z0\.d\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a4806060        ldff1sw \{z0\.d\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a4806060        ldff1sw \{z0\.d\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a48063e0        ldff1sw \{z0\.d\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a48063e0        ldff1sw \{z0\.d\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a4846000        ldff1sw \{z0\.d\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a4846000        ldff1sw \{z0\.d\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a49f6000        ldff1sw \{z0\.d\}, p0/z, \[x0,xzr,lsl #2\]
-.*:    a49f6000        ldff1sw \{z0\.d\}, p0/z, \[x0,xzr,lsl #2\]
-.*:    c5002000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5002000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5002000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5002000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5002001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5002001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5002001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5002001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500201f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500201f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500201f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500201f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5002800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5002800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5002800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5003c00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5003c00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5003c00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5002060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c5002060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c5002060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c50023e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c50023e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c50023e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c5042000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c5042000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c5042000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c51f2000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c51f2000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c51f2000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c5402000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5402000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5402000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5402000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5402001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5402001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5402001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5402001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540201f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540201f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540201f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540201f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5402800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5402800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5402800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5403c00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5403c00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5403c00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5402060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c5402060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c5402060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c54023e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c54023e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c54023e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c5442000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c5442000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c5442000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c55f2000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c55f2000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c55f2000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c5202000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5202000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5202000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5202001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5202001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5202001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c520201f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c520201f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c520201f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5202800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5202800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5203c00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5203c00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5202060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\]
-.*:    c5202060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\]
-.*:    c52023e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\]
-.*:    c52023e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\]
-.*:    c5242000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\]
-.*:    c5242000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\]
-.*:    c53f2000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\]
-.*:    c53f2000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\]
-.*:    c5602000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5602000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5602000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5602001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5602001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5602001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c560201f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c560201f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c560201f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5602800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5602800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5603c00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5603c00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5602060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\]
-.*:    c5602060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\]
-.*:    c56023e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\]
-.*:    c56023e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\]
-.*:    c5642000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\]
-.*:    c5642000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\]
-.*:    c57f2000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\]
-.*:    c57f2000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\]
-.*:    c540a000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540a000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540a000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540a000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540a001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540a001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540a001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540a001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540a01f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540a01f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540a01f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540a01f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540a800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c540a800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c540a800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c540bc00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c540bc00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c540bc00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c540a060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c540a060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c540a060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c540a3e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c540a3e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c540a3e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c544a000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c544a000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c544a000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c55fa000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c55fa000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c55fa000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c560a000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560a000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560a000        ldff1sw \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560a001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560a001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560a001        ldff1sw \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560a01f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560a01f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560a01f        ldff1sw \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560a800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\]
-.*:    c560a800        ldff1sw \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\]
-.*:    c560bc00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\]
-.*:    c560bc00        ldff1sw \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\]
-.*:    c560a060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\]
-.*:    c560a060        ldff1sw \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\]
-.*:    c560a3e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\]
-.*:    c560a3e0        ldff1sw \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\]
-.*:    c564a000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\]
-.*:    c564a000        ldff1sw \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\]
-.*:    c57fa000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\]
-.*:    c57fa000        ldff1sw \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\]
+.*:    c4afa000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #30\]
+.*:    c4afa000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #30\]
+.*:    c4b0a000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #32\]
+.*:    c4b0a000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #32\]
+.*:    c4b1a000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #34\]
+.*:    c4b1a000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #34\]
+.*:    c4bfa000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #62\]
+.*:    c4bfa000        ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #62\]
+.*:    a4806000        ldff1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a4806000        ldff1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a4806000        ldff1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a4806001        ldff1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a4806001        ldff1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a4806001        ldff1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a480601f        ldff1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a480601f        ldff1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a480601f        ldff1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a4806800        ldff1sw \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a4806800        ldff1sw \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a4807c00        ldff1sw \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a4807c00        ldff1sw \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a4806060        ldff1sw \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a4806060        ldff1sw \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a48063e0        ldff1sw \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a48063e0        ldff1sw \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a4846000        ldff1sw \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a4846000        ldff1sw \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a49f6000        ldff1sw \{z0\.d\}, p0/z, \[x0, xzr, lsl #2\]
+.*:    a49f6000        ldff1sw \{z0\.d\}, p0/z, \[x0, xzr, lsl #2\]
+.*:    c5002000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5002000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5002000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5002000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5002001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5002001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5002001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5002001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500201f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500201f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500201f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500201f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5002800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5002800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5002800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5003c00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5003c00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5003c00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5002060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c5002060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c5002060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c50023e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c50023e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c50023e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c5042000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c5042000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c5042000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c51f2000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c51f2000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c51f2000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c5402000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5402000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5402000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5402000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5402001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5402001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5402001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5402001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540201f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540201f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540201f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540201f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5402800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5402800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5402800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5403c00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5403c00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5403c00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5402060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c5402060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c5402060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c54023e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c54023e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c54023e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c5442000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c5442000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c5442000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c55f2000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c55f2000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c55f2000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c5202000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5202000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5202000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5202001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5202001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5202001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c520201f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c520201f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c520201f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5202800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5202800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5203c00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5203c00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5202060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
+.*:    c5202060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
+.*:    c52023e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
+.*:    c52023e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
+.*:    c5242000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
+.*:    c5242000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
+.*:    c53f2000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
+.*:    c53f2000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
+.*:    c5602000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5602000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5602000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5602001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5602001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5602001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c560201f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c560201f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c560201f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5602800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5602800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5603c00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5603c00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5602060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
+.*:    c5602060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
+.*:    c56023e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
+.*:    c56023e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
+.*:    c5642000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
+.*:    c5642000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
+.*:    c57f2000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
+.*:    c57f2000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
+.*:    c540a000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540a000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540a000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540a000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540a001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540a001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540a001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540a001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540a01f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540a01f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540a01f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540a01f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540a800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c540a800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c540a800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c540bc00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c540bc00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c540bc00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c540a060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c540a060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c540a060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c540a3e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c540a3e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c540a3e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c544a000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c544a000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c544a000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c55fa000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c55fa000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c55fa000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c560a000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560a000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560a000        ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560a001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560a001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560a001        ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560a01f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560a01f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560a01f        ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560a800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
+.*:    c560a800        ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
+.*:    c560bc00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
+.*:    c560bc00        ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
+.*:    c560a060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
+.*:    c560a060        ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
+.*:    c560a3e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
+.*:    c560a3e0        ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
+.*:    c564a000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
+.*:    c564a000        ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
+.*:    c57fa000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
+.*:    c57fa000        ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
 .*:    c520a000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c520a000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c520a000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d\]
@@ -18289,311 +18289,311 @@ Disassembly of section .*:
 .*:    c520a3e0        ldff1sw \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c520a3e0        ldff1sw \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c520a3e0        ldff1sw \{z0\.d\}, p0/z, \[z31\.d\]
-.*:    c52fa000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#60\]
-.*:    c52fa000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#60\]
-.*:    c530a000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#64\]
-.*:    c530a000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#64\]
-.*:    c531a000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#68\]
-.*:    c531a000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#68\]
-.*:    c53fa000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#124\]
-.*:    c53fa000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d,#124\]
-.*:    85006000        ldff1w  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85006000        ldff1w  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85006000        ldff1w  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85006000        ldff1w  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85006001        ldff1w  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85006001        ldff1w  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85006001        ldff1w  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85006001        ldff1w  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8500601f        ldff1w  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8500601f        ldff1w  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8500601f        ldff1w  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    8500601f        ldff1w  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw\]
-.*:    85006800        ldff1w  \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    85006800        ldff1w  \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    85006800        ldff1w  \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw\]
-.*:    85007c00        ldff1w  \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    85007c00        ldff1w  \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    85007c00        ldff1w  \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw\]
-.*:    85006060        ldff1w  \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    85006060        ldff1w  \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    85006060        ldff1w  \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw\]
-.*:    850063e0        ldff1w  \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    850063e0        ldff1w  \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    850063e0        ldff1w  \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw\]
-.*:    85046000        ldff1w  \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    85046000        ldff1w  \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    85046000        ldff1w  \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw\]
-.*:    851f6000        ldff1w  \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    851f6000        ldff1w  \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    851f6000        ldff1w  \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw\]
-.*:    85406000        ldff1w  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85406000        ldff1w  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85406000        ldff1w  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85406000        ldff1w  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85406001        ldff1w  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85406001        ldff1w  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85406001        ldff1w  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85406001        ldff1w  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8540601f        ldff1w  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8540601f        ldff1w  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8540601f        ldff1w  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    8540601f        ldff1w  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw\]
-.*:    85406800        ldff1w  \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    85406800        ldff1w  \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    85406800        ldff1w  \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw\]
-.*:    85407c00        ldff1w  \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    85407c00        ldff1w  \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    85407c00        ldff1w  \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw\]
-.*:    85406060        ldff1w  \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    85406060        ldff1w  \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    85406060        ldff1w  \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw\]
-.*:    854063e0        ldff1w  \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    854063e0        ldff1w  \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    854063e0        ldff1w  \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw\]
-.*:    85446000        ldff1w  \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    85446000        ldff1w  \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    85446000        ldff1w  \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw\]
-.*:    855f6000        ldff1w  \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    855f6000        ldff1w  \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    855f6000        ldff1w  \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw\]
-.*:    85206000        ldff1w  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    85206000        ldff1w  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    85206000        ldff1w  \{z0\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    85206001        ldff1w  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    85206001        ldff1w  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    85206001        ldff1w  \{z1\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    8520601f        ldff1w  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    8520601f        ldff1w  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    8520601f        ldff1w  \{z31\.s\}, p0/z, \[x0,z0\.s,uxtw #2\]
-.*:    85206800        ldff1w  \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #2\]
-.*:    85206800        ldff1w  \{z0\.s\}, p2/z, \[x0,z0\.s,uxtw #2\]
-.*:    85207c00        ldff1w  \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #2\]
-.*:    85207c00        ldff1w  \{z0\.s\}, p7/z, \[x0,z0\.s,uxtw #2\]
-.*:    85206060        ldff1w  \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #2\]
-.*:    85206060        ldff1w  \{z0\.s\}, p0/z, \[x3,z0\.s,uxtw #2\]
-.*:    852063e0        ldff1w  \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #2\]
-.*:    852063e0        ldff1w  \{z0\.s\}, p0/z, \[sp,z0\.s,uxtw #2\]
-.*:    85246000        ldff1w  \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #2\]
-.*:    85246000        ldff1w  \{z0\.s\}, p0/z, \[x0,z4\.s,uxtw #2\]
-.*:    853f6000        ldff1w  \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #2\]
-.*:    853f6000        ldff1w  \{z0\.s\}, p0/z, \[x0,z31\.s,uxtw #2\]
-.*:    85606000        ldff1w  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    85606000        ldff1w  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    85606000        ldff1w  \{z0\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    85606001        ldff1w  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    85606001        ldff1w  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    85606001        ldff1w  \{z1\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    8560601f        ldff1w  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    8560601f        ldff1w  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    8560601f        ldff1w  \{z31\.s\}, p0/z, \[x0,z0\.s,sxtw #2\]
-.*:    85606800        ldff1w  \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #2\]
-.*:    85606800        ldff1w  \{z0\.s\}, p2/z, \[x0,z0\.s,sxtw #2\]
-.*:    85607c00        ldff1w  \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #2\]
-.*:    85607c00        ldff1w  \{z0\.s\}, p7/z, \[x0,z0\.s,sxtw #2\]
-.*:    85606060        ldff1w  \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #2\]
-.*:    85606060        ldff1w  \{z0\.s\}, p0/z, \[x3,z0\.s,sxtw #2\]
-.*:    856063e0        ldff1w  \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #2\]
-.*:    856063e0        ldff1w  \{z0\.s\}, p0/z, \[sp,z0\.s,sxtw #2\]
-.*:    85646000        ldff1w  \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #2\]
-.*:    85646000        ldff1w  \{z0\.s\}, p0/z, \[x0,z4\.s,sxtw #2\]
-.*:    857f6000        ldff1w  \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #2\]
-.*:    857f6000        ldff1w  \{z0\.s\}, p0/z, \[x0,z31\.s,sxtw #2\]
-.*:    a5406000        ldff1w  \{z0\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5406000        ldff1w  \{z0\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5406000        ldff1w  \{z0\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5406001        ldff1w  \{z1\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5406001        ldff1w  \{z1\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5406001        ldff1w  \{z1\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a540601f        ldff1w  \{z31\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a540601f        ldff1w  \{z31\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a540601f        ldff1w  \{z31\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5406800        ldff1w  \{z0\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a5406800        ldff1w  \{z0\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a5407c00        ldff1w  \{z0\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a5407c00        ldff1w  \{z0\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a5406060        ldff1w  \{z0\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a5406060        ldff1w  \{z0\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a54063e0        ldff1w  \{z0\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a54063e0        ldff1w  \{z0\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a5446000        ldff1w  \{z0\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a5446000        ldff1w  \{z0\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a55f6000        ldff1w  \{z0\.s\}, p0/z, \[x0,xzr,lsl #2\]
-.*:    a55f6000        ldff1w  \{z0\.s\}, p0/z, \[x0,xzr,lsl #2\]
-.*:    a5606000        ldff1w  \{z0\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5606000        ldff1w  \{z0\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5606000        ldff1w  \{z0\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5606001        ldff1w  \{z1\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5606001        ldff1w  \{z1\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5606001        ldff1w  \{z1\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a560601f        ldff1w  \{z31\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a560601f        ldff1w  \{z31\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a560601f        ldff1w  \{z31\.d\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a5606800        ldff1w  \{z0\.d\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a5606800        ldff1w  \{z0\.d\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a5607c00        ldff1w  \{z0\.d\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a5607c00        ldff1w  \{z0\.d\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a5606060        ldff1w  \{z0\.d\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a5606060        ldff1w  \{z0\.d\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a56063e0        ldff1w  \{z0\.d\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a56063e0        ldff1w  \{z0\.d\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a5646000        ldff1w  \{z0\.d\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a5646000        ldff1w  \{z0\.d\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a57f6000        ldff1w  \{z0\.d\}, p0/z, \[x0,xzr,lsl #2\]
-.*:    a57f6000        ldff1w  \{z0\.d\}, p0/z, \[x0,xzr,lsl #2\]
-.*:    c5006000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5006000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5006000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5006000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5006001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5006001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5006001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5006001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500601f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500601f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500601f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c500601f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw\]
-.*:    c5006800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5006800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5006800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw\]
-.*:    c5007c00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5007c00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5007c00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw\]
-.*:    c5006060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c5006060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c5006060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw\]
-.*:    c50063e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c50063e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c50063e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw\]
-.*:    c5046000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c5046000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c5046000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw\]
-.*:    c51f6000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c51f6000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c51f6000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw\]
-.*:    c5406000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5406000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5406000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5406000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5406001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5406001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5406001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5406001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540601f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540601f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540601f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c540601f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw\]
-.*:    c5406800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5406800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5406800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw\]
-.*:    c5407c00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5407c00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5407c00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw\]
-.*:    c5406060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c5406060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c5406060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw\]
-.*:    c54063e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c54063e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c54063e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw\]
-.*:    c5446000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c5446000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c5446000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw\]
-.*:    c55f6000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c55f6000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c55f6000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw\]
-.*:    c5206000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5206000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5206000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5206001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5206001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5206001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c520601f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c520601f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c520601f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5206800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5206800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5207c00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5207c00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d,uxtw #2\]
-.*:    c5206060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\]
-.*:    c5206060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d,uxtw #2\]
-.*:    c52063e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\]
-.*:    c52063e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d,uxtw #2\]
-.*:    c5246000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\]
-.*:    c5246000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d,uxtw #2\]
-.*:    c53f6000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\]
-.*:    c53f6000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d,uxtw #2\]
-.*:    c5606000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5606000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5606000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5606001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5606001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5606001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c560601f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c560601f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c560601f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5606800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5606800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5607c00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5607c00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d,sxtw #2\]
-.*:    c5606060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\]
-.*:    c5606060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d,sxtw #2\]
-.*:    c56063e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\]
-.*:    c56063e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d,sxtw #2\]
-.*:    c5646000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\]
-.*:    c5646000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d,sxtw #2\]
-.*:    c57f6000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\]
-.*:    c57f6000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d,sxtw #2\]
-.*:    c540e000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540e000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540e000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540e000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540e001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540e001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540e001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540e001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540e01f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540e01f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540e01f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540e01f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d\]
-.*:    c540e800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c540e800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c540e800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d\]
-.*:    c540fc00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c540fc00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c540fc00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d\]
-.*:    c540e060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c540e060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c540e060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d\]
-.*:    c540e3e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c540e3e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c540e3e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d\]
-.*:    c544e000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c544e000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c544e000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d\]
-.*:    c55fe000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c55fe000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c55fe000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d\]
-.*:    c560e000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560e000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560e000        ldff1w  \{z0\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560e001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560e001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560e001        ldff1w  \{z1\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560e01f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560e01f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560e01f        ldff1w  \{z31\.d\}, p0/z, \[x0,z0\.d,lsl #2\]
-.*:    c560e800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\]
-.*:    c560e800        ldff1w  \{z0\.d\}, p2/z, \[x0,z0\.d,lsl #2\]
-.*:    c560fc00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\]
-.*:    c560fc00        ldff1w  \{z0\.d\}, p7/z, \[x0,z0\.d,lsl #2\]
-.*:    c560e060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\]
-.*:    c560e060        ldff1w  \{z0\.d\}, p0/z, \[x3,z0\.d,lsl #2\]
-.*:    c560e3e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\]
-.*:    c560e3e0        ldff1w  \{z0\.d\}, p0/z, \[sp,z0\.d,lsl #2\]
-.*:    c564e000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\]
-.*:    c564e000        ldff1w  \{z0\.d\}, p0/z, \[x0,z4\.d,lsl #2\]
-.*:    c57fe000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\]
-.*:    c57fe000        ldff1w  \{z0\.d\}, p0/z, \[x0,z31\.d,lsl #2\]
+.*:    c52fa000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #60\]
+.*:    c52fa000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #60\]
+.*:    c530a000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #64\]
+.*:    c530a000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #64\]
+.*:    c531a000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #68\]
+.*:    c531a000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #68\]
+.*:    c53fa000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #124\]
+.*:    c53fa000        ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #124\]
+.*:    85006000        ldff1w  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85006000        ldff1w  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85006000        ldff1w  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85006000        ldff1w  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85006001        ldff1w  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85006001        ldff1w  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85006001        ldff1w  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85006001        ldff1w  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8500601f        ldff1w  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8500601f        ldff1w  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8500601f        ldff1w  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    8500601f        ldff1w  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
+.*:    85006800        ldff1w  \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    85006800        ldff1w  \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    85006800        ldff1w  \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
+.*:    85007c00        ldff1w  \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    85007c00        ldff1w  \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    85007c00        ldff1w  \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
+.*:    85006060        ldff1w  \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    85006060        ldff1w  \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    85006060        ldff1w  \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
+.*:    850063e0        ldff1w  \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    850063e0        ldff1w  \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    850063e0        ldff1w  \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
+.*:    85046000        ldff1w  \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    85046000        ldff1w  \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    85046000        ldff1w  \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
+.*:    851f6000        ldff1w  \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    851f6000        ldff1w  \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    851f6000        ldff1w  \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
+.*:    85406000        ldff1w  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85406000        ldff1w  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85406000        ldff1w  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85406000        ldff1w  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85406001        ldff1w  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85406001        ldff1w  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85406001        ldff1w  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85406001        ldff1w  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8540601f        ldff1w  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8540601f        ldff1w  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8540601f        ldff1w  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    8540601f        ldff1w  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
+.*:    85406800        ldff1w  \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    85406800        ldff1w  \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    85406800        ldff1w  \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
+.*:    85407c00        ldff1w  \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    85407c00        ldff1w  \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    85407c00        ldff1w  \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
+.*:    85406060        ldff1w  \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    85406060        ldff1w  \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    85406060        ldff1w  \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
+.*:    854063e0        ldff1w  \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    854063e0        ldff1w  \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    854063e0        ldff1w  \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
+.*:    85446000        ldff1w  \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    85446000        ldff1w  \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    85446000        ldff1w  \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
+.*:    855f6000        ldff1w  \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    855f6000        ldff1w  \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    855f6000        ldff1w  \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
+.*:    85206000        ldff1w  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    85206000        ldff1w  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    85206000        ldff1w  \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    85206001        ldff1w  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    85206001        ldff1w  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    85206001        ldff1w  \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    8520601f        ldff1w  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    8520601f        ldff1w  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    8520601f        ldff1w  \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
+.*:    85206800        ldff1w  \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #2\]
+.*:    85206800        ldff1w  \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #2\]
+.*:    85207c00        ldff1w  \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #2\]
+.*:    85207c00        ldff1w  \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #2\]
+.*:    85206060        ldff1w  \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #2\]
+.*:    85206060        ldff1w  \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #2\]
+.*:    852063e0        ldff1w  \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #2\]
+.*:    852063e0        ldff1w  \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #2\]
+.*:    85246000        ldff1w  \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #2\]
+.*:    85246000        ldff1w  \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #2\]
+.*:    853f6000        ldff1w  \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #2\]
+.*:    853f6000        ldff1w  \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #2\]
+.*:    85606000        ldff1w  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    85606000        ldff1w  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    85606000        ldff1w  \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    85606001        ldff1w  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    85606001        ldff1w  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    85606001        ldff1w  \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    8560601f        ldff1w  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    8560601f        ldff1w  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    8560601f        ldff1w  \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
+.*:    85606800        ldff1w  \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #2\]
+.*:    85606800        ldff1w  \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #2\]
+.*:    85607c00        ldff1w  \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #2\]
+.*:    85607c00        ldff1w  \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #2\]
+.*:    85606060        ldff1w  \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #2\]
+.*:    85606060        ldff1w  \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #2\]
+.*:    856063e0        ldff1w  \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #2\]
+.*:    856063e0        ldff1w  \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #2\]
+.*:    85646000        ldff1w  \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #2\]
+.*:    85646000        ldff1w  \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #2\]
+.*:    857f6000        ldff1w  \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #2\]
+.*:    857f6000        ldff1w  \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #2\]
+.*:    a5406000        ldff1w  \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5406000        ldff1w  \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5406000        ldff1w  \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5406001        ldff1w  \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5406001        ldff1w  \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5406001        ldff1w  \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a540601f        ldff1w  \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a540601f        ldff1w  \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a540601f        ldff1w  \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5406800        ldff1w  \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a5406800        ldff1w  \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a5407c00        ldff1w  \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a5407c00        ldff1w  \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a5406060        ldff1w  \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a5406060        ldff1w  \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a54063e0        ldff1w  \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a54063e0        ldff1w  \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a5446000        ldff1w  \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a5446000        ldff1w  \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a55f6000        ldff1w  \{z0\.s\}, p0/z, \[x0, xzr, lsl #2\]
+.*:    a55f6000        ldff1w  \{z0\.s\}, p0/z, \[x0, xzr, lsl #2\]
+.*:    a5606000        ldff1w  \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5606000        ldff1w  \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5606000        ldff1w  \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5606001        ldff1w  \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5606001        ldff1w  \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5606001        ldff1w  \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a560601f        ldff1w  \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a560601f        ldff1w  \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a560601f        ldff1w  \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a5606800        ldff1w  \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a5606800        ldff1w  \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a5607c00        ldff1w  \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a5607c00        ldff1w  \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a5606060        ldff1w  \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a5606060        ldff1w  \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a56063e0        ldff1w  \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a56063e0        ldff1w  \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a5646000        ldff1w  \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a5646000        ldff1w  \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a57f6000        ldff1w  \{z0\.d\}, p0/z, \[x0, xzr, lsl #2\]
+.*:    a57f6000        ldff1w  \{z0\.d\}, p0/z, \[x0, xzr, lsl #2\]
+.*:    c5006000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5006000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5006000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5006000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5006001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5006001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5006001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5006001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500601f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500601f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500601f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c500601f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
+.*:    c5006800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5006800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5006800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
+.*:    c5007c00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5007c00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5007c00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
+.*:    c5006060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c5006060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c5006060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
+.*:    c50063e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c50063e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c50063e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
+.*:    c5046000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c5046000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c5046000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
+.*:    c51f6000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c51f6000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c51f6000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
+.*:    c5406000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5406000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5406000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5406000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5406001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5406001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5406001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5406001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540601f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540601f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540601f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c540601f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
+.*:    c5406800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5406800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5406800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
+.*:    c5407c00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5407c00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5407c00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
+.*:    c5406060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c5406060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c5406060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
+.*:    c54063e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c54063e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c54063e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
+.*:    c5446000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c5446000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c5446000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
+.*:    c55f6000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c55f6000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c55f6000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
+.*:    c5206000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5206000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5206000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5206001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5206001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5206001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c520601f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c520601f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c520601f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5206800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5206800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5207c00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5207c00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
+.*:    c5206060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
+.*:    c5206060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
+.*:    c52063e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
+.*:    c52063e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
+.*:    c5246000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
+.*:    c5246000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
+.*:    c53f6000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
+.*:    c53f6000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
+.*:    c5606000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5606000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5606000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5606001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5606001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5606001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c560601f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c560601f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c560601f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5606800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5606800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5607c00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5607c00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
+.*:    c5606060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
+.*:    c5606060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
+.*:    c56063e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
+.*:    c56063e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
+.*:    c5646000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
+.*:    c5646000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
+.*:    c57f6000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
+.*:    c57f6000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
+.*:    c540e000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540e000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540e000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540e000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540e001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540e001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540e001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540e001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540e01f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540e01f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540e01f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540e01f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d\]
+.*:    c540e800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c540e800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c540e800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d\]
+.*:    c540fc00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c540fc00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c540fc00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d\]
+.*:    c540e060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c540e060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c540e060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d\]
+.*:    c540e3e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c540e3e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c540e3e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d\]
+.*:    c544e000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c544e000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c544e000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d\]
+.*:    c55fe000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c55fe000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c55fe000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d\]
+.*:    c560e000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560e000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560e000        ldff1w  \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560e001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560e001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560e001        ldff1w  \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560e01f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560e01f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560e01f        ldff1w  \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
+.*:    c560e800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
+.*:    c560e800        ldff1w  \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
+.*:    c560fc00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
+.*:    c560fc00        ldff1w  \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
+.*:    c560e060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
+.*:    c560e060        ldff1w  \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
+.*:    c560e3e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
+.*:    c560e3e0        ldff1w  \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
+.*:    c564e000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
+.*:    c564e000        ldff1w  \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
+.*:    c57fe000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
+.*:    c57fe000        ldff1w  \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
 .*:    8520e000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    8520e000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s\]
 .*:    8520e000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s\]
@@ -18618,14 +18618,14 @@ Disassembly of section .*:
 .*:    8520e3e0        ldff1w  \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    8520e3e0        ldff1w  \{z0\.s\}, p0/z, \[z31\.s\]
 .*:    8520e3e0        ldff1w  \{z0\.s\}, p0/z, \[z31\.s\]
-.*:    852fe000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s,#60\]
-.*:    852fe000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s,#60\]
-.*:    8530e000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s,#64\]
-.*:    8530e000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s,#64\]
-.*:    8531e000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s,#68\]
-.*:    8531e000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s,#68\]
-.*:    853fe000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s,#124\]
-.*:    853fe000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s,#124\]
+.*:    852fe000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s, #60\]
+.*:    852fe000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s, #60\]
+.*:    8530e000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s, #64\]
+.*:    8530e000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s, #64\]
+.*:    8531e000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s, #68\]
+.*:    8531e000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s, #68\]
+.*:    853fe000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s, #124\]
+.*:    853fe000        ldff1w  \{z0\.s\}, p0/z, \[z0\.s, #124\]
 .*:    c520e000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c520e000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d\]
 .*:    c520e000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d\]
@@ -18650,14 +18650,14 @@ Disassembly of section .*:
 .*:    c520e3e0        ldff1w  \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c520e3e0        ldff1w  \{z0\.d\}, p0/z, \[z31\.d\]
 .*:    c520e3e0        ldff1w  \{z0\.d\}, p0/z, \[z31\.d\]
-.*:    c52fe000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d,#60\]
-.*:    c52fe000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d,#60\]
-.*:    c530e000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d,#64\]
-.*:    c530e000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d,#64\]
-.*:    c531e000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d,#68\]
-.*:    c531e000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d,#68\]
-.*:    c53fe000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d,#124\]
-.*:    c53fe000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d,#124\]
+.*:    c52fe000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d, #60\]
+.*:    c52fe000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d, #60\]
+.*:    c530e000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d, #64\]
+.*:    c530e000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d, #64\]
+.*:    c531e000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d, #68\]
+.*:    c531e000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d, #68\]
+.*:    c53fe000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d, #124\]
+.*:    c53fe000        ldff1w  \{z0\.d\}, p0/z, \[z0\.d, #124\]
 .*:    a410a000        ldnf1b  \{z0\.b\}, p0/z, \[x0\]
 .*:    a410a000        ldnf1b  \{z0\.b\}, p0/z, \[x0\]
 .*:    a410a000        ldnf1b  \{z0\.b\}, p0/z, \[x0\]
@@ -18689,14 +18689,14 @@ Disassembly of section .*:
 .*:    a410a3e0        ldnf1b  \{z0\.b\}, p0/z, \[sp\]
 .*:    a410a3e0        ldnf1b  \{z0\.b\}, p0/z, \[sp\]
 .*:    a410a3e0        ldnf1b  \{z0\.b\}, p0/z, \[sp\]
-.*:    a417a000        ldnf1b  \{z0\.b\}, p0/z, \[x0,#7,mul vl\]
-.*:    a417a000        ldnf1b  \{z0\.b\}, p0/z, \[x0,#7,mul vl\]
-.*:    a418a000        ldnf1b  \{z0\.b\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a418a000        ldnf1b  \{z0\.b\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a419a000        ldnf1b  \{z0\.b\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a419a000        ldnf1b  \{z0\.b\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a41fa000        ldnf1b  \{z0\.b\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a41fa000        ldnf1b  \{z0\.b\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a417a000        ldnf1b  \{z0\.b\}, p0/z, \[x0, #7, mul vl\]
+.*:    a417a000        ldnf1b  \{z0\.b\}, p0/z, \[x0, #7, mul vl\]
+.*:    a418a000        ldnf1b  \{z0\.b\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a418a000        ldnf1b  \{z0\.b\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a419a000        ldnf1b  \{z0\.b\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a419a000        ldnf1b  \{z0\.b\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a41fa000        ldnf1b  \{z0\.b\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a41fa000        ldnf1b  \{z0\.b\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a430a000        ldnf1b  \{z0\.h\}, p0/z, \[x0\]
 .*:    a430a000        ldnf1b  \{z0\.h\}, p0/z, \[x0\]
 .*:    a430a000        ldnf1b  \{z0\.h\}, p0/z, \[x0\]
@@ -18728,14 +18728,14 @@ Disassembly of section .*:
 .*:    a430a3e0        ldnf1b  \{z0\.h\}, p0/z, \[sp\]
 .*:    a430a3e0        ldnf1b  \{z0\.h\}, p0/z, \[sp\]
 .*:    a430a3e0        ldnf1b  \{z0\.h\}, p0/z, \[sp\]
-.*:    a437a000        ldnf1b  \{z0\.h\}, p0/z, \[x0,#7,mul vl\]
-.*:    a437a000        ldnf1b  \{z0\.h\}, p0/z, \[x0,#7,mul vl\]
-.*:    a438a000        ldnf1b  \{z0\.h\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a438a000        ldnf1b  \{z0\.h\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a439a000        ldnf1b  \{z0\.h\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a439a000        ldnf1b  \{z0\.h\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a43fa000        ldnf1b  \{z0\.h\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a43fa000        ldnf1b  \{z0\.h\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a437a000        ldnf1b  \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
+.*:    a437a000        ldnf1b  \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
+.*:    a438a000        ldnf1b  \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a438a000        ldnf1b  \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a439a000        ldnf1b  \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a439a000        ldnf1b  \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a43fa000        ldnf1b  \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a43fa000        ldnf1b  \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a450a000        ldnf1b  \{z0\.s\}, p0/z, \[x0\]
 .*:    a450a000        ldnf1b  \{z0\.s\}, p0/z, \[x0\]
 .*:    a450a000        ldnf1b  \{z0\.s\}, p0/z, \[x0\]
@@ -18767,14 +18767,14 @@ Disassembly of section .*:
 .*:    a450a3e0        ldnf1b  \{z0\.s\}, p0/z, \[sp\]
 .*:    a450a3e0        ldnf1b  \{z0\.s\}, p0/z, \[sp\]
 .*:    a450a3e0        ldnf1b  \{z0\.s\}, p0/z, \[sp\]
-.*:    a457a000        ldnf1b  \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a457a000        ldnf1b  \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a458a000        ldnf1b  \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a458a000        ldnf1b  \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a459a000        ldnf1b  \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a459a000        ldnf1b  \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a45fa000        ldnf1b  \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a45fa000        ldnf1b  \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a457a000        ldnf1b  \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a457a000        ldnf1b  \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a458a000        ldnf1b  \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a458a000        ldnf1b  \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a459a000        ldnf1b  \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a459a000        ldnf1b  \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a45fa000        ldnf1b  \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a45fa000        ldnf1b  \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a470a000        ldnf1b  \{z0\.d\}, p0/z, \[x0\]
 .*:    a470a000        ldnf1b  \{z0\.d\}, p0/z, \[x0\]
 .*:    a470a000        ldnf1b  \{z0\.d\}, p0/z, \[x0\]
@@ -18806,14 +18806,14 @@ Disassembly of section .*:
 .*:    a470a3e0        ldnf1b  \{z0\.d\}, p0/z, \[sp\]
 .*:    a470a3e0        ldnf1b  \{z0\.d\}, p0/z, \[sp\]
 .*:    a470a3e0        ldnf1b  \{z0\.d\}, p0/z, \[sp\]
-.*:    a477a000        ldnf1b  \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a477a000        ldnf1b  \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a478a000        ldnf1b  \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a478a000        ldnf1b  \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a479a000        ldnf1b  \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a479a000        ldnf1b  \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a47fa000        ldnf1b  \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a47fa000        ldnf1b  \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a477a000        ldnf1b  \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a477a000        ldnf1b  \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a478a000        ldnf1b  \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a478a000        ldnf1b  \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a479a000        ldnf1b  \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a479a000        ldnf1b  \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a47fa000        ldnf1b  \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a47fa000        ldnf1b  \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a5f0a000        ldnf1d  \{z0\.d\}, p0/z, \[x0\]
 .*:    a5f0a000        ldnf1d  \{z0\.d\}, p0/z, \[x0\]
 .*:    a5f0a000        ldnf1d  \{z0\.d\}, p0/z, \[x0\]
@@ -18845,14 +18845,14 @@ Disassembly of section .*:
 .*:    a5f0a3e0        ldnf1d  \{z0\.d\}, p0/z, \[sp\]
 .*:    a5f0a3e0        ldnf1d  \{z0\.d\}, p0/z, \[sp\]
 .*:    a5f0a3e0        ldnf1d  \{z0\.d\}, p0/z, \[sp\]
-.*:    a5f7a000        ldnf1d  \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a5f7a000        ldnf1d  \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a5f8a000        ldnf1d  \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a5f8a000        ldnf1d  \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a5f9a000        ldnf1d  \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a5f9a000        ldnf1d  \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a5ffa000        ldnf1d  \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a5ffa000        ldnf1d  \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a5f7a000        ldnf1d  \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a5f7a000        ldnf1d  \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a5f8a000        ldnf1d  \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a5f8a000        ldnf1d  \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a5f9a000        ldnf1d  \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a5f9a000        ldnf1d  \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a5ffa000        ldnf1d  \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a5ffa000        ldnf1d  \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a4b0a000        ldnf1h  \{z0\.h\}, p0/z, \[x0\]
 .*:    a4b0a000        ldnf1h  \{z0\.h\}, p0/z, \[x0\]
 .*:    a4b0a000        ldnf1h  \{z0\.h\}, p0/z, \[x0\]
@@ -18884,14 +18884,14 @@ Disassembly of section .*:
 .*:    a4b0a3e0        ldnf1h  \{z0\.h\}, p0/z, \[sp\]
 .*:    a4b0a3e0        ldnf1h  \{z0\.h\}, p0/z, \[sp\]
 .*:    a4b0a3e0        ldnf1h  \{z0\.h\}, p0/z, \[sp\]
-.*:    a4b7a000        ldnf1h  \{z0\.h\}, p0/z, \[x0,#7,mul vl\]
-.*:    a4b7a000        ldnf1h  \{z0\.h\}, p0/z, \[x0,#7,mul vl\]
-.*:    a4b8a000        ldnf1h  \{z0\.h\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a4b8a000        ldnf1h  \{z0\.h\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a4b9a000        ldnf1h  \{z0\.h\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a4b9a000        ldnf1h  \{z0\.h\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a4bfa000        ldnf1h  \{z0\.h\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a4bfa000        ldnf1h  \{z0\.h\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a4b7a000        ldnf1h  \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
+.*:    a4b7a000        ldnf1h  \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
+.*:    a4b8a000        ldnf1h  \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a4b8a000        ldnf1h  \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a4b9a000        ldnf1h  \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a4b9a000        ldnf1h  \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a4bfa000        ldnf1h  \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a4bfa000        ldnf1h  \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a4d0a000        ldnf1h  \{z0\.s\}, p0/z, \[x0\]
 .*:    a4d0a000        ldnf1h  \{z0\.s\}, p0/z, \[x0\]
 .*:    a4d0a000        ldnf1h  \{z0\.s\}, p0/z, \[x0\]
@@ -18923,14 +18923,14 @@ Disassembly of section .*:
 .*:    a4d0a3e0        ldnf1h  \{z0\.s\}, p0/z, \[sp\]
 .*:    a4d0a3e0        ldnf1h  \{z0\.s\}, p0/z, \[sp\]
 .*:    a4d0a3e0        ldnf1h  \{z0\.s\}, p0/z, \[sp\]
-.*:    a4d7a000        ldnf1h  \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a4d7a000        ldnf1h  \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a4d8a000        ldnf1h  \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a4d8a000        ldnf1h  \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a4d9a000        ldnf1h  \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a4d9a000        ldnf1h  \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a4dfa000        ldnf1h  \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a4dfa000        ldnf1h  \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a4d7a000        ldnf1h  \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a4d7a000        ldnf1h  \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a4d8a000        ldnf1h  \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a4d8a000        ldnf1h  \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a4d9a000        ldnf1h  \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a4d9a000        ldnf1h  \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a4dfa000        ldnf1h  \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a4dfa000        ldnf1h  \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a4f0a000        ldnf1h  \{z0\.d\}, p0/z, \[x0\]
 .*:    a4f0a000        ldnf1h  \{z0\.d\}, p0/z, \[x0\]
 .*:    a4f0a000        ldnf1h  \{z0\.d\}, p0/z, \[x0\]
@@ -18962,14 +18962,14 @@ Disassembly of section .*:
 .*:    a4f0a3e0        ldnf1h  \{z0\.d\}, p0/z, \[sp\]
 .*:    a4f0a3e0        ldnf1h  \{z0\.d\}, p0/z, \[sp\]
 .*:    a4f0a3e0        ldnf1h  \{z0\.d\}, p0/z, \[sp\]
-.*:    a4f7a000        ldnf1h  \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a4f7a000        ldnf1h  \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a4f8a000        ldnf1h  \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a4f8a000        ldnf1h  \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a4f9a000        ldnf1h  \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a4f9a000        ldnf1h  \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a4ffa000        ldnf1h  \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a4ffa000        ldnf1h  \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a4f7a000        ldnf1h  \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a4f7a000        ldnf1h  \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a4f8a000        ldnf1h  \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a4f8a000        ldnf1h  \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a4f9a000        ldnf1h  \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a4f9a000        ldnf1h  \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a4ffa000        ldnf1h  \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a4ffa000        ldnf1h  \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a590a000        ldnf1sb \{z0\.d\}, p0/z, \[x0\]
 .*:    a590a000        ldnf1sb \{z0\.d\}, p0/z, \[x0\]
 .*:    a590a000        ldnf1sb \{z0\.d\}, p0/z, \[x0\]
@@ -19001,14 +19001,14 @@ Disassembly of section .*:
 .*:    a590a3e0        ldnf1sb \{z0\.d\}, p0/z, \[sp\]
 .*:    a590a3e0        ldnf1sb \{z0\.d\}, p0/z, \[sp\]
 .*:    a590a3e0        ldnf1sb \{z0\.d\}, p0/z, \[sp\]
-.*:    a597a000        ldnf1sb \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a597a000        ldnf1sb \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a598a000        ldnf1sb \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a598a000        ldnf1sb \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a599a000        ldnf1sb \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a599a000        ldnf1sb \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a59fa000        ldnf1sb \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a59fa000        ldnf1sb \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a597a000        ldnf1sb \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a597a000        ldnf1sb \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a598a000        ldnf1sb \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a598a000        ldnf1sb \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a599a000        ldnf1sb \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a599a000        ldnf1sb \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a59fa000        ldnf1sb \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a59fa000        ldnf1sb \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a5b0a000        ldnf1sb \{z0\.s\}, p0/z, \[x0\]
 .*:    a5b0a000        ldnf1sb \{z0\.s\}, p0/z, \[x0\]
 .*:    a5b0a000        ldnf1sb \{z0\.s\}, p0/z, \[x0\]
@@ -19040,14 +19040,14 @@ Disassembly of section .*:
 .*:    a5b0a3e0        ldnf1sb \{z0\.s\}, p0/z, \[sp\]
 .*:    a5b0a3e0        ldnf1sb \{z0\.s\}, p0/z, \[sp\]
 .*:    a5b0a3e0        ldnf1sb \{z0\.s\}, p0/z, \[sp\]
-.*:    a5b7a000        ldnf1sb \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a5b7a000        ldnf1sb \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a5b8a000        ldnf1sb \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a5b8a000        ldnf1sb \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a5b9a000        ldnf1sb \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a5b9a000        ldnf1sb \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a5bfa000        ldnf1sb \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a5bfa000        ldnf1sb \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a5b7a000        ldnf1sb \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a5b7a000        ldnf1sb \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a5b8a000        ldnf1sb \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a5b8a000        ldnf1sb \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a5b9a000        ldnf1sb \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a5b9a000        ldnf1sb \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a5bfa000        ldnf1sb \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a5bfa000        ldnf1sb \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a5d0a000        ldnf1sb \{z0\.h\}, p0/z, \[x0\]
 .*:    a5d0a000        ldnf1sb \{z0\.h\}, p0/z, \[x0\]
 .*:    a5d0a000        ldnf1sb \{z0\.h\}, p0/z, \[x0\]
@@ -19079,14 +19079,14 @@ Disassembly of section .*:
 .*:    a5d0a3e0        ldnf1sb \{z0\.h\}, p0/z, \[sp\]
 .*:    a5d0a3e0        ldnf1sb \{z0\.h\}, p0/z, \[sp\]
 .*:    a5d0a3e0        ldnf1sb \{z0\.h\}, p0/z, \[sp\]
-.*:    a5d7a000        ldnf1sb \{z0\.h\}, p0/z, \[x0,#7,mul vl\]
-.*:    a5d7a000        ldnf1sb \{z0\.h\}, p0/z, \[x0,#7,mul vl\]
-.*:    a5d8a000        ldnf1sb \{z0\.h\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a5d8a000        ldnf1sb \{z0\.h\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a5d9a000        ldnf1sb \{z0\.h\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a5d9a000        ldnf1sb \{z0\.h\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a5dfa000        ldnf1sb \{z0\.h\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a5dfa000        ldnf1sb \{z0\.h\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a5d7a000        ldnf1sb \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
+.*:    a5d7a000        ldnf1sb \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
+.*:    a5d8a000        ldnf1sb \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a5d8a000        ldnf1sb \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a5d9a000        ldnf1sb \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a5d9a000        ldnf1sb \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a5dfa000        ldnf1sb \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a5dfa000        ldnf1sb \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a510a000        ldnf1sh \{z0\.d\}, p0/z, \[x0\]
 .*:    a510a000        ldnf1sh \{z0\.d\}, p0/z, \[x0\]
 .*:    a510a000        ldnf1sh \{z0\.d\}, p0/z, \[x0\]
@@ -19118,14 +19118,14 @@ Disassembly of section .*:
 .*:    a510a3e0        ldnf1sh \{z0\.d\}, p0/z, \[sp\]
 .*:    a510a3e0        ldnf1sh \{z0\.d\}, p0/z, \[sp\]
 .*:    a510a3e0        ldnf1sh \{z0\.d\}, p0/z, \[sp\]
-.*:    a517a000        ldnf1sh \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a517a000        ldnf1sh \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a518a000        ldnf1sh \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a518a000        ldnf1sh \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a519a000        ldnf1sh \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a519a000        ldnf1sh \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a51fa000        ldnf1sh \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a51fa000        ldnf1sh \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a517a000        ldnf1sh \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a517a000        ldnf1sh \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a518a000        ldnf1sh \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a518a000        ldnf1sh \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a519a000        ldnf1sh \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a519a000        ldnf1sh \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a51fa000        ldnf1sh \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a51fa000        ldnf1sh \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a530a000        ldnf1sh \{z0\.s\}, p0/z, \[x0\]
 .*:    a530a000        ldnf1sh \{z0\.s\}, p0/z, \[x0\]
 .*:    a530a000        ldnf1sh \{z0\.s\}, p0/z, \[x0\]
@@ -19157,14 +19157,14 @@ Disassembly of section .*:
 .*:    a530a3e0        ldnf1sh \{z0\.s\}, p0/z, \[sp\]
 .*:    a530a3e0        ldnf1sh \{z0\.s\}, p0/z, \[sp\]
 .*:    a530a3e0        ldnf1sh \{z0\.s\}, p0/z, \[sp\]
-.*:    a537a000        ldnf1sh \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a537a000        ldnf1sh \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a538a000        ldnf1sh \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a538a000        ldnf1sh \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a539a000        ldnf1sh \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a539a000        ldnf1sh \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a53fa000        ldnf1sh \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a53fa000        ldnf1sh \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a537a000        ldnf1sh \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a537a000        ldnf1sh \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a538a000        ldnf1sh \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a538a000        ldnf1sh \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a539a000        ldnf1sh \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a539a000        ldnf1sh \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a53fa000        ldnf1sh \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a53fa000        ldnf1sh \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a490a000        ldnf1sw \{z0\.d\}, p0/z, \[x0\]
 .*:    a490a000        ldnf1sw \{z0\.d\}, p0/z, \[x0\]
 .*:    a490a000        ldnf1sw \{z0\.d\}, p0/z, \[x0\]
@@ -19196,14 +19196,14 @@ Disassembly of section .*:
 .*:    a490a3e0        ldnf1sw \{z0\.d\}, p0/z, \[sp\]
 .*:    a490a3e0        ldnf1sw \{z0\.d\}, p0/z, \[sp\]
 .*:    a490a3e0        ldnf1sw \{z0\.d\}, p0/z, \[sp\]
-.*:    a497a000        ldnf1sw \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a497a000        ldnf1sw \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a498a000        ldnf1sw \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a498a000        ldnf1sw \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a499a000        ldnf1sw \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a499a000        ldnf1sw \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a49fa000        ldnf1sw \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a49fa000        ldnf1sw \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a497a000        ldnf1sw \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a497a000        ldnf1sw \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a498a000        ldnf1sw \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a498a000        ldnf1sw \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a499a000        ldnf1sw \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a499a000        ldnf1sw \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a49fa000        ldnf1sw \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a49fa000        ldnf1sw \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a550a000        ldnf1w  \{z0\.s\}, p0/z, \[x0\]
 .*:    a550a000        ldnf1w  \{z0\.s\}, p0/z, \[x0\]
 .*:    a550a000        ldnf1w  \{z0\.s\}, p0/z, \[x0\]
@@ -19235,14 +19235,14 @@ Disassembly of section .*:
 .*:    a550a3e0        ldnf1w  \{z0\.s\}, p0/z, \[sp\]
 .*:    a550a3e0        ldnf1w  \{z0\.s\}, p0/z, \[sp\]
 .*:    a550a3e0        ldnf1w  \{z0\.s\}, p0/z, \[sp\]
-.*:    a557a000        ldnf1w  \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a557a000        ldnf1w  \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a558a000        ldnf1w  \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a558a000        ldnf1w  \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a559a000        ldnf1w  \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a559a000        ldnf1w  \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a55fa000        ldnf1w  \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a55fa000        ldnf1w  \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a557a000        ldnf1w  \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a557a000        ldnf1w  \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a558a000        ldnf1w  \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a558a000        ldnf1w  \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a559a000        ldnf1w  \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a559a000        ldnf1w  \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a55fa000        ldnf1w  \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a55fa000        ldnf1w  \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
 .*:    a570a000        ldnf1w  \{z0\.d\}, p0/z, \[x0\]
 .*:    a570a000        ldnf1w  \{z0\.d\}, p0/z, \[x0\]
 .*:    a570a000        ldnf1w  \{z0\.d\}, p0/z, \[x0\]
@@ -19274,44 +19274,44 @@ Disassembly of section .*:
 .*:    a570a3e0        ldnf1w  \{z0\.d\}, p0/z, \[sp\]
 .*:    a570a3e0        ldnf1w  \{z0\.d\}, p0/z, \[sp\]
 .*:    a570a3e0        ldnf1w  \{z0\.d\}, p0/z, \[sp\]
-.*:    a577a000        ldnf1w  \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a577a000        ldnf1w  \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a578a000        ldnf1w  \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a578a000        ldnf1w  \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a579a000        ldnf1w  \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a579a000        ldnf1w  \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a57fa000        ldnf1w  \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a57fa000        ldnf1w  \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a400c000        ldnt1b  \{z0\.b\}, p0/z, \[x0,x0\]
-.*:    a400c000        ldnt1b  \{z0\.b\}, p0/z, \[x0,x0\]
-.*:    a400c000        ldnt1b  \{z0\.b\}, p0/z, \[x0,x0\]
-.*:    a400c000        ldnt1b  \{z0\.b\}, p0/z, \[x0,x0\]
-.*:    a400c001        ldnt1b  \{z1\.b\}, p0/z, \[x0,x0\]
-.*:    a400c001        ldnt1b  \{z1\.b\}, p0/z, \[x0,x0\]
-.*:    a400c001        ldnt1b  \{z1\.b\}, p0/z, \[x0,x0\]
-.*:    a400c001        ldnt1b  \{z1\.b\}, p0/z, \[x0,x0\]
-.*:    a400c01f        ldnt1b  \{z31\.b\}, p0/z, \[x0,x0\]
-.*:    a400c01f        ldnt1b  \{z31\.b\}, p0/z, \[x0,x0\]
-.*:    a400c01f        ldnt1b  \{z31\.b\}, p0/z, \[x0,x0\]
-.*:    a400c01f        ldnt1b  \{z31\.b\}, p0/z, \[x0,x0\]
-.*:    a400c800        ldnt1b  \{z0\.b\}, p2/z, \[x0,x0\]
-.*:    a400c800        ldnt1b  \{z0\.b\}, p2/z, \[x0,x0\]
-.*:    a400c800        ldnt1b  \{z0\.b\}, p2/z, \[x0,x0\]
-.*:    a400dc00        ldnt1b  \{z0\.b\}, p7/z, \[x0,x0\]
-.*:    a400dc00        ldnt1b  \{z0\.b\}, p7/z, \[x0,x0\]
-.*:    a400dc00        ldnt1b  \{z0\.b\}, p7/z, \[x0,x0\]
-.*:    a400c060        ldnt1b  \{z0\.b\}, p0/z, \[x3,x0\]
-.*:    a400c060        ldnt1b  \{z0\.b\}, p0/z, \[x3,x0\]
-.*:    a400c060        ldnt1b  \{z0\.b\}, p0/z, \[x3,x0\]
-.*:    a400c3e0        ldnt1b  \{z0\.b\}, p0/z, \[sp,x0\]
-.*:    a400c3e0        ldnt1b  \{z0\.b\}, p0/z, \[sp,x0\]
-.*:    a400c3e0        ldnt1b  \{z0\.b\}, p0/z, \[sp,x0\]
-.*:    a404c000        ldnt1b  \{z0\.b\}, p0/z, \[x0,x4\]
-.*:    a404c000        ldnt1b  \{z0\.b\}, p0/z, \[x0,x4\]
-.*:    a404c000        ldnt1b  \{z0\.b\}, p0/z, \[x0,x4\]
-.*:    a41ec000        ldnt1b  \{z0\.b\}, p0/z, \[x0,x30\]
-.*:    a41ec000        ldnt1b  \{z0\.b\}, p0/z, \[x0,x30\]
-.*:    a41ec000        ldnt1b  \{z0\.b\}, p0/z, \[x0,x30\]
+.*:    a577a000        ldnf1w  \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a577a000        ldnf1w  \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a578a000        ldnf1w  \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a578a000        ldnf1w  \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a579a000        ldnf1w  \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a579a000        ldnf1w  \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a57fa000        ldnf1w  \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a57fa000        ldnf1w  \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a400c000        ldnt1b  \{z0\.b\}, p0/z, \[x0, x0\]
+.*:    a400c000        ldnt1b  \{z0\.b\}, p0/z, \[x0, x0\]
+.*:    a400c000        ldnt1b  \{z0\.b\}, p0/z, \[x0, x0\]
+.*:    a400c000        ldnt1b  \{z0\.b\}, p0/z, \[x0, x0\]
+.*:    a400c001        ldnt1b  \{z1\.b\}, p0/z, \[x0, x0\]
+.*:    a400c001        ldnt1b  \{z1\.b\}, p0/z, \[x0, x0\]
+.*:    a400c001        ldnt1b  \{z1\.b\}, p0/z, \[x0, x0\]
+.*:    a400c001        ldnt1b  \{z1\.b\}, p0/z, \[x0, x0\]
+.*:    a400c01f        ldnt1b  \{z31\.b\}, p0/z, \[x0, x0\]
+.*:    a400c01f        ldnt1b  \{z31\.b\}, p0/z, \[x0, x0\]
+.*:    a400c01f        ldnt1b  \{z31\.b\}, p0/z, \[x0, x0\]
+.*:    a400c01f        ldnt1b  \{z31\.b\}, p0/z, \[x0, x0\]
+.*:    a400c800        ldnt1b  \{z0\.b\}, p2/z, \[x0, x0\]
+.*:    a400c800        ldnt1b  \{z0\.b\}, p2/z, \[x0, x0\]
+.*:    a400c800        ldnt1b  \{z0\.b\}, p2/z, \[x0, x0\]
+.*:    a400dc00        ldnt1b  \{z0\.b\}, p7/z, \[x0, x0\]
+.*:    a400dc00        ldnt1b  \{z0\.b\}, p7/z, \[x0, x0\]
+.*:    a400dc00        ldnt1b  \{z0\.b\}, p7/z, \[x0, x0\]
+.*:    a400c060        ldnt1b  \{z0\.b\}, p0/z, \[x3, x0\]
+.*:    a400c060        ldnt1b  \{z0\.b\}, p0/z, \[x3, x0\]
+.*:    a400c060        ldnt1b  \{z0\.b\}, p0/z, \[x3, x0\]
+.*:    a400c3e0        ldnt1b  \{z0\.b\}, p0/z, \[sp, x0\]
+.*:    a400c3e0        ldnt1b  \{z0\.b\}, p0/z, \[sp, x0\]
+.*:    a400c3e0        ldnt1b  \{z0\.b\}, p0/z, \[sp, x0\]
+.*:    a404c000        ldnt1b  \{z0\.b\}, p0/z, \[x0, x4\]
+.*:    a404c000        ldnt1b  \{z0\.b\}, p0/z, \[x0, x4\]
+.*:    a404c000        ldnt1b  \{z0\.b\}, p0/z, \[x0, x4\]
+.*:    a41ec000        ldnt1b  \{z0\.b\}, p0/z, \[x0, x30\]
+.*:    a41ec000        ldnt1b  \{z0\.b\}, p0/z, \[x0, x30\]
+.*:    a41ec000        ldnt1b  \{z0\.b\}, p0/z, \[x0, x30\]
 .*:    a400e000        ldnt1b  \{z0\.b\}, p0/z, \[x0\]
 .*:    a400e000        ldnt1b  \{z0\.b\}, p0/z, \[x0\]
 .*:    a400e000        ldnt1b  \{z0\.b\}, p0/z, \[x0\]
@@ -19343,35 +19343,35 @@ Disassembly of section .*:
 .*:    a400e3e0        ldnt1b  \{z0\.b\}, p0/z, \[sp\]
 .*:    a400e3e0        ldnt1b  \{z0\.b\}, p0/z, \[sp\]
 .*:    a400e3e0        ldnt1b  \{z0\.b\}, p0/z, \[sp\]
-.*:    a407e000        ldnt1b  \{z0\.b\}, p0/z, \[x0,#7,mul vl\]
-.*:    a407e000        ldnt1b  \{z0\.b\}, p0/z, \[x0,#7,mul vl\]
-.*:    a408e000        ldnt1b  \{z0\.b\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a408e000        ldnt1b  \{z0\.b\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a409e000        ldnt1b  \{z0\.b\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a409e000        ldnt1b  \{z0\.b\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a40fe000        ldnt1b  \{z0\.b\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a40fe000        ldnt1b  \{z0\.b\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a580c000        ldnt1d  \{z0\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a580c000        ldnt1d  \{z0\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a580c000        ldnt1d  \{z0\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a580c001        ldnt1d  \{z1\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a580c001        ldnt1d  \{z1\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a580c001        ldnt1d  \{z1\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a580c01f        ldnt1d  \{z31\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a580c01f        ldnt1d  \{z31\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a580c01f        ldnt1d  \{z31\.d\}, p0/z, \[x0,x0,lsl #3\]
-.*:    a580c800        ldnt1d  \{z0\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a580c800        ldnt1d  \{z0\.d\}, p2/z, \[x0,x0,lsl #3\]
-.*:    a580dc00        ldnt1d  \{z0\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a580dc00        ldnt1d  \{z0\.d\}, p7/z, \[x0,x0,lsl #3\]
-.*:    a580c060        ldnt1d  \{z0\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a580c060        ldnt1d  \{z0\.d\}, p0/z, \[x3,x0,lsl #3\]
-.*:    a580c3e0        ldnt1d  \{z0\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a580c3e0        ldnt1d  \{z0\.d\}, p0/z, \[sp,x0,lsl #3\]
-.*:    a584c000        ldnt1d  \{z0\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a584c000        ldnt1d  \{z0\.d\}, p0/z, \[x0,x4,lsl #3\]
-.*:    a59ec000        ldnt1d  \{z0\.d\}, p0/z, \[x0,x30,lsl #3\]
-.*:    a59ec000        ldnt1d  \{z0\.d\}, p0/z, \[x0,x30,lsl #3\]
+.*:    a407e000        ldnt1b  \{z0\.b\}, p0/z, \[x0, #7, mul vl\]
+.*:    a407e000        ldnt1b  \{z0\.b\}, p0/z, \[x0, #7, mul vl\]
+.*:    a408e000        ldnt1b  \{z0\.b\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a408e000        ldnt1b  \{z0\.b\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a409e000        ldnt1b  \{z0\.b\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a409e000        ldnt1b  \{z0\.b\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a40fe000        ldnt1b  \{z0\.b\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a40fe000        ldnt1b  \{z0\.b\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a580c000        ldnt1d  \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a580c000        ldnt1d  \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a580c000        ldnt1d  \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a580c001        ldnt1d  \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a580c001        ldnt1d  \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a580c001        ldnt1d  \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a580c01f        ldnt1d  \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a580c01f        ldnt1d  \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a580c01f        ldnt1d  \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
+.*:    a580c800        ldnt1d  \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a580c800        ldnt1d  \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
+.*:    a580dc00        ldnt1d  \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a580dc00        ldnt1d  \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
+.*:    a580c060        ldnt1d  \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a580c060        ldnt1d  \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
+.*:    a580c3e0        ldnt1d  \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a580c3e0        ldnt1d  \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
+.*:    a584c000        ldnt1d  \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a584c000        ldnt1d  \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
+.*:    a59ec000        ldnt1d  \{z0\.d\}, p0/z, \[x0, x30, lsl #3\]
+.*:    a59ec000        ldnt1d  \{z0\.d\}, p0/z, \[x0, x30, lsl #3\]
 .*:    a580e000        ldnt1d  \{z0\.d\}, p0/z, \[x0\]
 .*:    a580e000        ldnt1d  \{z0\.d\}, p0/z, \[x0\]
 .*:    a580e000        ldnt1d  \{z0\.d\}, p0/z, \[x0\]
@@ -19403,35 +19403,35 @@ Disassembly of section .*:
 .*:    a580e3e0        ldnt1d  \{z0\.d\}, p0/z, \[sp\]
 .*:    a580e3e0        ldnt1d  \{z0\.d\}, p0/z, \[sp\]
 .*:    a580e3e0        ldnt1d  \{z0\.d\}, p0/z, \[sp\]
-.*:    a587e000        ldnt1d  \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a587e000        ldnt1d  \{z0\.d\}, p0/z, \[x0,#7,mul vl\]
-.*:    a588e000        ldnt1d  \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a588e000        ldnt1d  \{z0\.d\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a589e000        ldnt1d  \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a589e000        ldnt1d  \{z0\.d\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a58fe000        ldnt1d  \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a58fe000        ldnt1d  \{z0\.d\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a480c000        ldnt1h  \{z0\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a480c000        ldnt1h  \{z0\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a480c000        ldnt1h  \{z0\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a480c001        ldnt1h  \{z1\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a480c001        ldnt1h  \{z1\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a480c001        ldnt1h  \{z1\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a480c01f        ldnt1h  \{z31\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a480c01f        ldnt1h  \{z31\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a480c01f        ldnt1h  \{z31\.h\}, p0/z, \[x0,x0,lsl #1\]
-.*:    a480c800        ldnt1h  \{z0\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a480c800        ldnt1h  \{z0\.h\}, p2/z, \[x0,x0,lsl #1\]
-.*:    a480dc00        ldnt1h  \{z0\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a480dc00        ldnt1h  \{z0\.h\}, p7/z, \[x0,x0,lsl #1\]
-.*:    a480c060        ldnt1h  \{z0\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a480c060        ldnt1h  \{z0\.h\}, p0/z, \[x3,x0,lsl #1\]
-.*:    a480c3e0        ldnt1h  \{z0\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a480c3e0        ldnt1h  \{z0\.h\}, p0/z, \[sp,x0,lsl #1\]
-.*:    a484c000        ldnt1h  \{z0\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a484c000        ldnt1h  \{z0\.h\}, p0/z, \[x0,x4,lsl #1\]
-.*:    a49ec000        ldnt1h  \{z0\.h\}, p0/z, \[x0,x30,lsl #1\]
-.*:    a49ec000        ldnt1h  \{z0\.h\}, p0/z, \[x0,x30,lsl #1\]
+.*:    a587e000        ldnt1d  \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a587e000        ldnt1d  \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
+.*:    a588e000        ldnt1d  \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a588e000        ldnt1d  \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a589e000        ldnt1d  \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a589e000        ldnt1d  \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a58fe000        ldnt1d  \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a58fe000        ldnt1d  \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a480c000        ldnt1h  \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a480c000        ldnt1h  \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a480c000        ldnt1h  \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a480c001        ldnt1h  \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a480c001        ldnt1h  \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a480c001        ldnt1h  \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a480c01f        ldnt1h  \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a480c01f        ldnt1h  \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a480c01f        ldnt1h  \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
+.*:    a480c800        ldnt1h  \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a480c800        ldnt1h  \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
+.*:    a480dc00        ldnt1h  \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a480dc00        ldnt1h  \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
+.*:    a480c060        ldnt1h  \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a480c060        ldnt1h  \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
+.*:    a480c3e0        ldnt1h  \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a480c3e0        ldnt1h  \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
+.*:    a484c000        ldnt1h  \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a484c000        ldnt1h  \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
+.*:    a49ec000        ldnt1h  \{z0\.h\}, p0/z, \[x0, x30, lsl #1\]
+.*:    a49ec000        ldnt1h  \{z0\.h\}, p0/z, \[x0, x30, lsl #1\]
 .*:    a480e000        ldnt1h  \{z0\.h\}, p0/z, \[x0\]
 .*:    a480e000        ldnt1h  \{z0\.h\}, p0/z, \[x0\]
 .*:    a480e000        ldnt1h  \{z0\.h\}, p0/z, \[x0\]
@@ -19463,35 +19463,35 @@ Disassembly of section .*:
 .*:    a480e3e0        ldnt1h  \{z0\.h\}, p0/z, \[sp\]
 .*:    a480e3e0        ldnt1h  \{z0\.h\}, p0/z, \[sp\]
 .*:    a480e3e0        ldnt1h  \{z0\.h\}, p0/z, \[sp\]
-.*:    a487e000        ldnt1h  \{z0\.h\}, p0/z, \[x0,#7,mul vl\]
-.*:    a487e000        ldnt1h  \{z0\.h\}, p0/z, \[x0,#7,mul vl\]
-.*:    a488e000        ldnt1h  \{z0\.h\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a488e000        ldnt1h  \{z0\.h\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a489e000        ldnt1h  \{z0\.h\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a489e000        ldnt1h  \{z0\.h\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a48fe000        ldnt1h  \{z0\.h\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a48fe000        ldnt1h  \{z0\.h\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a500c000        ldnt1w  \{z0\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a500c000        ldnt1w  \{z0\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a500c000        ldnt1w  \{z0\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a500c001        ldnt1w  \{z1\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a500c001        ldnt1w  \{z1\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a500c001        ldnt1w  \{z1\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a500c01f        ldnt1w  \{z31\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a500c01f        ldnt1w  \{z31\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a500c01f        ldnt1w  \{z31\.s\}, p0/z, \[x0,x0,lsl #2\]
-.*:    a500c800        ldnt1w  \{z0\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a500c800        ldnt1w  \{z0\.s\}, p2/z, \[x0,x0,lsl #2\]
-.*:    a500dc00        ldnt1w  \{z0\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a500dc00        ldnt1w  \{z0\.s\}, p7/z, \[x0,x0,lsl #2\]
-.*:    a500c060        ldnt1w  \{z0\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a500c060        ldnt1w  \{z0\.s\}, p0/z, \[x3,x0,lsl #2\]
-.*:    a500c3e0        ldnt1w  \{z0\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a500c3e0        ldnt1w  \{z0\.s\}, p0/z, \[sp,x0,lsl #2\]
-.*:    a504c000        ldnt1w  \{z0\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a504c000        ldnt1w  \{z0\.s\}, p0/z, \[x0,x4,lsl #2\]
-.*:    a51ec000        ldnt1w  \{z0\.s\}, p0/z, \[x0,x30,lsl #2\]
-.*:    a51ec000        ldnt1w  \{z0\.s\}, p0/z, \[x0,x30,lsl #2\]
+.*:    a487e000        ldnt1h  \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
+.*:    a487e000        ldnt1h  \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
+.*:    a488e000        ldnt1h  \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a488e000        ldnt1h  \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a489e000        ldnt1h  \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a489e000        ldnt1h  \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a48fe000        ldnt1h  \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a48fe000        ldnt1h  \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a500c000        ldnt1w  \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a500c000        ldnt1w  \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a500c000        ldnt1w  \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a500c001        ldnt1w  \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a500c001        ldnt1w  \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a500c001        ldnt1w  \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a500c01f        ldnt1w  \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a500c01f        ldnt1w  \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a500c01f        ldnt1w  \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
+.*:    a500c800        ldnt1w  \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a500c800        ldnt1w  \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
+.*:    a500dc00        ldnt1w  \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a500dc00        ldnt1w  \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
+.*:    a500c060        ldnt1w  \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a500c060        ldnt1w  \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
+.*:    a500c3e0        ldnt1w  \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a500c3e0        ldnt1w  \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
+.*:    a504c000        ldnt1w  \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a504c000        ldnt1w  \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
+.*:    a51ec000        ldnt1w  \{z0\.s\}, p0/z, \[x0, x30, lsl #2\]
+.*:    a51ec000        ldnt1w  \{z0\.s\}, p0/z, \[x0, x30, lsl #2\]
 .*:    a500e000        ldnt1w  \{z0\.s\}, p0/z, \[x0\]
 .*:    a500e000        ldnt1w  \{z0\.s\}, p0/z, \[x0\]
 .*:    a500e000        ldnt1w  \{z0\.s\}, p0/z, \[x0\]
@@ -19523,14 +19523,14 @@ Disassembly of section .*:
 .*:    a500e3e0        ldnt1w  \{z0\.s\}, p0/z, \[sp\]
 .*:    a500e3e0        ldnt1w  \{z0\.s\}, p0/z, \[sp\]
 .*:    a500e3e0        ldnt1w  \{z0\.s\}, p0/z, \[sp\]
-.*:    a507e000        ldnt1w  \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a507e000        ldnt1w  \{z0\.s\}, p0/z, \[x0,#7,mul vl\]
-.*:    a508e000        ldnt1w  \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a508e000        ldnt1w  \{z0\.s\}, p0/z, \[x0,#-8,mul vl\]
-.*:    a509e000        ldnt1w  \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a509e000        ldnt1w  \{z0\.s\}, p0/z, \[x0,#-7,mul vl\]
-.*:    a50fe000        ldnt1w  \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
-.*:    a50fe000        ldnt1w  \{z0\.s\}, p0/z, \[x0,#-1,mul vl\]
+.*:    a507e000        ldnt1w  \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a507e000        ldnt1w  \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
+.*:    a508e000        ldnt1w  \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a508e000        ldnt1w  \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
+.*:    a509e000        ldnt1w  \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a509e000        ldnt1w  \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
+.*:    a50fe000        ldnt1w  \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
+.*:    a50fe000        ldnt1w  \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
 .*:    85800000        ldr     p0, \[x0\]
 .*:    85800000        ldr     p0, \[x0\]
 .*:    85800000        ldr     p0, \[x0\]
@@ -19551,14 +19551,14 @@ Disassembly of section .*:
 .*:    858003e0        ldr     p0, \[sp\]
 .*:    858003e0        ldr     p0, \[sp\]
 .*:    858003e0        ldr     p0, \[sp\]
-.*:    859f1c00        ldr     p0, \[x0,#255,mul vl\]
-.*:    859f1c00        ldr     p0, \[x0,#255,mul vl\]
-.*:    85a00000        ldr     p0, \[x0,#-256,mul vl\]
-.*:    85a00000        ldr     p0, \[x0,#-256,mul vl\]
-.*:    85a00400        ldr     p0, \[x0,#-255,mul vl\]
-.*:    85a00400        ldr     p0, \[x0,#-255,mul vl\]
-.*:    85bf1c00        ldr     p0, \[x0,#-1,mul vl\]
-.*:    85bf1c00        ldr     p0, \[x0,#-1,mul vl\]
+.*:    859f1c00        ldr     p0, \[x0, #255, mul vl\]
+.*:    859f1c00        ldr     p0, \[x0, #255, mul vl\]
+.*:    85a00000        ldr     p0, \[x0, #-256, mul vl\]
+.*:    85a00000        ldr     p0, \[x0, #-256, mul vl\]
+.*:    85a00400        ldr     p0, \[x0, #-255, mul vl\]
+.*:    85a00400        ldr     p0, \[x0, #-255, mul vl\]
+.*:    85bf1c00        ldr     p0, \[x0, #-1, mul vl\]
+.*:    85bf1c00        ldr     p0, \[x0, #-1, mul vl\]
 .*:    85804000        ldr     z0, \[x0\]
 .*:    85804000        ldr     z0, \[x0\]
 .*:    85804000        ldr     z0, \[x0\]
@@ -19579,14 +19579,14 @@ Disassembly of section .*:
 .*:    858043e0        ldr     z0, \[sp\]
 .*:    858043e0        ldr     z0, \[sp\]
 .*:    858043e0        ldr     z0, \[sp\]
-.*:    859f5c00        ldr     z0, \[x0,#255,mul vl\]
-.*:    859f5c00        ldr     z0, \[x0,#255,mul vl\]
-.*:    85a04000        ldr     z0, \[x0,#-256,mul vl\]
-.*:    85a04000        ldr     z0, \[x0,#-256,mul vl\]
-.*:    85a04400        ldr     z0, \[x0,#-255,mul vl\]
-.*:    85a04400        ldr     z0, \[x0,#-255,mul vl\]
-.*:    85bf5c00        ldr     z0, \[x0,#-1,mul vl\]
-.*:    85bf5c00        ldr     z0, \[x0,#-1,mul vl\]
+.*:    859f5c00        ldr     z0, \[x0, #255, mul vl\]
+.*:    859f5c00        ldr     z0, \[x0, #255, mul vl\]
+.*:    85a04000        ldr     z0, \[x0, #-256, mul vl\]
+.*:    85a04000        ldr     z0, \[x0, #-256, mul vl\]
+.*:    85a04400        ldr     z0, \[x0, #-255, mul vl\]
+.*:    85a04400        ldr     z0, \[x0, #-255, mul vl\]
+.*:    85bf5c00        ldr     z0, \[x0, #-1, mul vl\]
+.*:    85bf5c00        ldr     z0, \[x0, #-1, mul vl\]
 .*:    04208c00        lsl     z0\.b, z0\.b, z0\.d
 .*:    04208c00        lsl     z0\.b, z0\.b, z0\.d
 .*:    04208c01        lsl     z1\.b, z0\.b, z0\.d
@@ -21986,402 +21986,402 @@ Disassembly of section .*:
 .*:    25d9c5e0        pnext   p0\.d, p15, p0\.d
 .*:    25d9c403        pnext   p3\.d, p0, p3\.d
 .*:    25d9c403        pnext   p3\.d, p0, p3\.d
-.*:    8400c000        prfb    pldl1keep, p0, \[x0,x0\]
-.*:    8400c000        prfb    pldl1keep, p0, \[x0,x0\]
-.*:    8400c000        prfb    pldl1keep, p0, \[x0,x0\]
-.*:    8400c001        prfb    pldl1strm, p0, \[x0,x0\]
-.*:    8400c001        prfb    pldl1strm, p0, \[x0,x0\]
-.*:    8400c001        prfb    pldl1strm, p0, \[x0,x0\]
-.*:    8400c002        prfb    pldl2keep, p0, \[x0,x0\]
-.*:    8400c002        prfb    pldl2keep, p0, \[x0,x0\]
-.*:    8400c002        prfb    pldl2keep, p0, \[x0,x0\]
-.*:    8400c003        prfb    pldl2strm, p0, \[x0,x0\]
-.*:    8400c003        prfb    pldl2strm, p0, \[x0,x0\]
-.*:    8400c003        prfb    pldl2strm, p0, \[x0,x0\]
-.*:    8400c004        prfb    pldl3keep, p0, \[x0,x0\]
-.*:    8400c004        prfb    pldl3keep, p0, \[x0,x0\]
-.*:    8400c004        prfb    pldl3keep, p0, \[x0,x0\]
-.*:    8400c005        prfb    pldl3strm, p0, \[x0,x0\]
-.*:    8400c005        prfb    pldl3strm, p0, \[x0,x0\]
-.*:    8400c005        prfb    pldl3strm, p0, \[x0,x0\]
-.*:    8400c006        prfb    #6, p0, \[x0,x0\]
-.*:    8400c006        prfb    #6, p0, \[x0,x0\]
-.*:    8400c006        prfb    #6, p0, \[x0,x0\]
-.*:    8400c007        prfb    #7, p0, \[x0,x0\]
-.*:    8400c007        prfb    #7, p0, \[x0,x0\]
-.*:    8400c007        prfb    #7, p0, \[x0,x0\]
-.*:    8400c008        prfb    pstl1keep, p0, \[x0,x0\]
-.*:    8400c008        prfb    pstl1keep, p0, \[x0,x0\]
-.*:    8400c008        prfb    pstl1keep, p0, \[x0,x0\]
-.*:    8400c009        prfb    pstl1strm, p0, \[x0,x0\]
-.*:    8400c009        prfb    pstl1strm, p0, \[x0,x0\]
-.*:    8400c009        prfb    pstl1strm, p0, \[x0,x0\]
-.*:    8400c00a        prfb    pstl2keep, p0, \[x0,x0\]
-.*:    8400c00a        prfb    pstl2keep, p0, \[x0,x0\]
-.*:    8400c00a        prfb    pstl2keep, p0, \[x0,x0\]
-.*:    8400c00b        prfb    pstl2strm, p0, \[x0,x0\]
-.*:    8400c00b        prfb    pstl2strm, p0, \[x0,x0\]
-.*:    8400c00b        prfb    pstl2strm, p0, \[x0,x0\]
-.*:    8400c00c        prfb    pstl3keep, p0, \[x0,x0\]
-.*:    8400c00c        prfb    pstl3keep, p0, \[x0,x0\]
-.*:    8400c00c        prfb    pstl3keep, p0, \[x0,x0\]
-.*:    8400c00d        prfb    pstl3strm, p0, \[x0,x0\]
-.*:    8400c00d        prfb    pstl3strm, p0, \[x0,x0\]
-.*:    8400c00d        prfb    pstl3strm, p0, \[x0,x0\]
-.*:    8400c00e        prfb    #14, p0, \[x0,x0\]
-.*:    8400c00e        prfb    #14, p0, \[x0,x0\]
-.*:    8400c00e        prfb    #14, p0, \[x0,x0\]
-.*:    8400c00f        prfb    #15, p0, \[x0,x0\]
-.*:    8400c00f        prfb    #15, p0, \[x0,x0\]
-.*:    8400c00f        prfb    #15, p0, \[x0,x0\]
-.*:    8400c800        prfb    pldl1keep, p2, \[x0,x0\]
-.*:    8400c800        prfb    pldl1keep, p2, \[x0,x0\]
-.*:    8400c800        prfb    pldl1keep, p2, \[x0,x0\]
-.*:    8400dc00        prfb    pldl1keep, p7, \[x0,x0\]
-.*:    8400dc00        prfb    pldl1keep, p7, \[x0,x0\]
-.*:    8400dc00        prfb    pldl1keep, p7, \[x0,x0\]
-.*:    8400c060        prfb    pldl1keep, p0, \[x3,x0\]
-.*:    8400c060        prfb    pldl1keep, p0, \[x3,x0\]
-.*:    8400c060        prfb    pldl1keep, p0, \[x3,x0\]
-.*:    8400c3e0        prfb    pldl1keep, p0, \[sp,x0\]
-.*:    8400c3e0        prfb    pldl1keep, p0, \[sp,x0\]
-.*:    8400c3e0        prfb    pldl1keep, p0, \[sp,x0\]
-.*:    8404c000        prfb    pldl1keep, p0, \[x0,x4\]
-.*:    8404c000        prfb    pldl1keep, p0, \[x0,x4\]
-.*:    8404c000        prfb    pldl1keep, p0, \[x0,x4\]
-.*:    841ec000        prfb    pldl1keep, p0, \[x0,x30\]
-.*:    841ec000        prfb    pldl1keep, p0, \[x0,x30\]
-.*:    841ec000        prfb    pldl1keep, p0, \[x0,x30\]
-.*:    84200000        prfb    pldl1keep, p0, \[x0,z0\.s,uxtw\]
-.*:    84200000        prfb    pldl1keep, p0, \[x0,z0\.s,uxtw\]
-.*:    84200000        prfb    pldl1keep, p0, \[x0,z0\.s,uxtw\]
-.*:    84200001        prfb    pldl1strm, p0, \[x0,z0\.s,uxtw\]
-.*:    84200001        prfb    pldl1strm, p0, \[x0,z0\.s,uxtw\]
-.*:    84200001        prfb    pldl1strm, p0, \[x0,z0\.s,uxtw\]
-.*:    84200002        prfb    pldl2keep, p0, \[x0,z0\.s,uxtw\]
-.*:    84200002        prfb    pldl2keep, p0, \[x0,z0\.s,uxtw\]
-.*:    84200002        prfb    pldl2keep, p0, \[x0,z0\.s,uxtw\]
-.*:    84200003        prfb    pldl2strm, p0, \[x0,z0\.s,uxtw\]
-.*:    84200003        prfb    pldl2strm, p0, \[x0,z0\.s,uxtw\]
-.*:    84200003        prfb    pldl2strm, p0, \[x0,z0\.s,uxtw\]
-.*:    84200004        prfb    pldl3keep, p0, \[x0,z0\.s,uxtw\]
-.*:    84200004        prfb    pldl3keep, p0, \[x0,z0\.s,uxtw\]
-.*:    84200004        prfb    pldl3keep, p0, \[x0,z0\.s,uxtw\]
-.*:    84200005        prfb    pldl3strm, p0, \[x0,z0\.s,uxtw\]
-.*:    84200005        prfb    pldl3strm, p0, \[x0,z0\.s,uxtw\]
-.*:    84200005        prfb    pldl3strm, p0, \[x0,z0\.s,uxtw\]
-.*:    84200006        prfb    #6, p0, \[x0,z0\.s,uxtw\]
-.*:    84200006        prfb    #6, p0, \[x0,z0\.s,uxtw\]
-.*:    84200006        prfb    #6, p0, \[x0,z0\.s,uxtw\]
-.*:    84200007        prfb    #7, p0, \[x0,z0\.s,uxtw\]
-.*:    84200007        prfb    #7, p0, \[x0,z0\.s,uxtw\]
-.*:    84200007        prfb    #7, p0, \[x0,z0\.s,uxtw\]
-.*:    84200008        prfb    pstl1keep, p0, \[x0,z0\.s,uxtw\]
-.*:    84200008        prfb    pstl1keep, p0, \[x0,z0\.s,uxtw\]
-.*:    84200008        prfb    pstl1keep, p0, \[x0,z0\.s,uxtw\]
-.*:    84200009        prfb    pstl1strm, p0, \[x0,z0\.s,uxtw\]
-.*:    84200009        prfb    pstl1strm, p0, \[x0,z0\.s,uxtw\]
-.*:    84200009        prfb    pstl1strm, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000a        prfb    pstl2keep, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000a        prfb    pstl2keep, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000a        prfb    pstl2keep, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000b        prfb    pstl2strm, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000b        prfb    pstl2strm, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000b        prfb    pstl2strm, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000c        prfb    pstl3keep, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000c        prfb    pstl3keep, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000c        prfb    pstl3keep, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000d        prfb    pstl3strm, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000d        prfb    pstl3strm, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000d        prfb    pstl3strm, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000e        prfb    #14, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000e        prfb    #14, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000e        prfb    #14, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000f        prfb    #15, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000f        prfb    #15, p0, \[x0,z0\.s,uxtw\]
-.*:    8420000f        prfb    #15, p0, \[x0,z0\.s,uxtw\]
-.*:    84200800        prfb    pldl1keep, p2, \[x0,z0\.s,uxtw\]
-.*:    84200800        prfb    pldl1keep, p2, \[x0,z0\.s,uxtw\]
-.*:    84200800        prfb    pldl1keep, p2, \[x0,z0\.s,uxtw\]
-.*:    84201c00        prfb    pldl1keep, p7, \[x0,z0\.s,uxtw\]
-.*:    84201c00        prfb    pldl1keep, p7, \[x0,z0\.s,uxtw\]
-.*:    84201c00        prfb    pldl1keep, p7, \[x0,z0\.s,uxtw\]
-.*:    84200060        prfb    pldl1keep, p0, \[x3,z0\.s,uxtw\]
-.*:    84200060        prfb    pldl1keep, p0, \[x3,z0\.s,uxtw\]
-.*:    84200060        prfb    pldl1keep, p0, \[x3,z0\.s,uxtw\]
-.*:    842003e0        prfb    pldl1keep, p0, \[sp,z0\.s,uxtw\]
-.*:    842003e0        prfb    pldl1keep, p0, \[sp,z0\.s,uxtw\]
-.*:    842003e0        prfb    pldl1keep, p0, \[sp,z0\.s,uxtw\]
-.*:    84240000        prfb    pldl1keep, p0, \[x0,z4\.s,uxtw\]
-.*:    84240000        prfb    pldl1keep, p0, \[x0,z4\.s,uxtw\]
-.*:    84240000        prfb    pldl1keep, p0, \[x0,z4\.s,uxtw\]
-.*:    843f0000        prfb    pldl1keep, p0, \[x0,z31\.s,uxtw\]
-.*:    843f0000        prfb    pldl1keep, p0, \[x0,z31\.s,uxtw\]
-.*:    843f0000        prfb    pldl1keep, p0, \[x0,z31\.s,uxtw\]
-.*:    84600000        prfb    pldl1keep, p0, \[x0,z0\.s,sxtw\]
-.*:    84600000        prfb    pldl1keep, p0, \[x0,z0\.s,sxtw\]
-.*:    84600000        prfb    pldl1keep, p0, \[x0,z0\.s,sxtw\]
-.*:    84600001        prfb    pldl1strm, p0, \[x0,z0\.s,sxtw\]
-.*:    84600001        prfb    pldl1strm, p0, \[x0,z0\.s,sxtw\]
-.*:    84600001        prfb    pldl1strm, p0, \[x0,z0\.s,sxtw\]
-.*:    84600002        prfb    pldl2keep, p0, \[x0,z0\.s,sxtw\]
-.*:    84600002        prfb    pldl2keep, p0, \[x0,z0\.s,sxtw\]
-.*:    84600002        prfb    pldl2keep, p0, \[x0,z0\.s,sxtw\]
-.*:    84600003        prfb    pldl2strm, p0, \[x0,z0\.s,sxtw\]
-.*:    84600003        prfb    pldl2strm, p0, \[x0,z0\.s,sxtw\]
-.*:    84600003        prfb    pldl2strm, p0, \[x0,z0\.s,sxtw\]
-.*:    84600004        prfb    pldl3keep, p0, \[x0,z0\.s,sxtw\]
-.*:    84600004        prfb    pldl3keep, p0, \[x0,z0\.s,sxtw\]
-.*:    84600004        prfb    pldl3keep, p0, \[x0,z0\.s,sxtw\]
-.*:    84600005        prfb    pldl3strm, p0, \[x0,z0\.s,sxtw\]
-.*:    84600005        prfb    pldl3strm, p0, \[x0,z0\.s,sxtw\]
-.*:    84600005        prfb    pldl3strm, p0, \[x0,z0\.s,sxtw\]
-.*:    84600006        prfb    #6, p0, \[x0,z0\.s,sxtw\]
-.*:    84600006        prfb    #6, p0, \[x0,z0\.s,sxtw\]
-.*:    84600006        prfb    #6, p0, \[x0,z0\.s,sxtw\]
-.*:    84600007        prfb    #7, p0, \[x0,z0\.s,sxtw\]
-.*:    84600007        prfb    #7, p0, \[x0,z0\.s,sxtw\]
-.*:    84600007        prfb    #7, p0, \[x0,z0\.s,sxtw\]
-.*:    84600008        prfb    pstl1keep, p0, \[x0,z0\.s,sxtw\]
-.*:    84600008        prfb    pstl1keep, p0, \[x0,z0\.s,sxtw\]
-.*:    84600008        prfb    pstl1keep, p0, \[x0,z0\.s,sxtw\]
-.*:    84600009        prfb    pstl1strm, p0, \[x0,z0\.s,sxtw\]
-.*:    84600009        prfb    pstl1strm, p0, \[x0,z0\.s,sxtw\]
-.*:    84600009        prfb    pstl1strm, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000a        prfb    pstl2keep, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000a        prfb    pstl2keep, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000a        prfb    pstl2keep, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000b        prfb    pstl2strm, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000b        prfb    pstl2strm, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000b        prfb    pstl2strm, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000c        prfb    pstl3keep, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000c        prfb    pstl3keep, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000c        prfb    pstl3keep, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000d        prfb    pstl3strm, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000d        prfb    pstl3strm, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000d        prfb    pstl3strm, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000e        prfb    #14, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000e        prfb    #14, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000e        prfb    #14, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000f        prfb    #15, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000f        prfb    #15, p0, \[x0,z0\.s,sxtw\]
-.*:    8460000f        prfb    #15, p0, \[x0,z0\.s,sxtw\]
-.*:    84600800        prfb    pldl1keep, p2, \[x0,z0\.s,sxtw\]
-.*:    84600800        prfb    pldl1keep, p2, \[x0,z0\.s,sxtw\]
-.*:    84600800        prfb    pldl1keep, p2, \[x0,z0\.s,sxtw\]
-.*:    84601c00        prfb    pldl1keep, p7, \[x0,z0\.s,sxtw\]
-.*:    84601c00        prfb    pldl1keep, p7, \[x0,z0\.s,sxtw\]
-.*:    84601c00        prfb    pldl1keep, p7, \[x0,z0\.s,sxtw\]
-.*:    84600060        prfb    pldl1keep, p0, \[x3,z0\.s,sxtw\]
-.*:    84600060        prfb    pldl1keep, p0, \[x3,z0\.s,sxtw\]
-.*:    84600060        prfb    pldl1keep, p0, \[x3,z0\.s,sxtw\]
-.*:    846003e0        prfb    pldl1keep, p0, \[sp,z0\.s,sxtw\]
-.*:    846003e0        prfb    pldl1keep, p0, \[sp,z0\.s,sxtw\]
-.*:    846003e0        prfb    pldl1keep, p0, \[sp,z0\.s,sxtw\]
-.*:    84640000        prfb    pldl1keep, p0, \[x0,z4\.s,sxtw\]
-.*:    84640000        prfb    pldl1keep, p0, \[x0,z4\.s,sxtw\]
-.*:    84640000        prfb    pldl1keep, p0, \[x0,z4\.s,sxtw\]
-.*:    847f0000        prfb    pldl1keep, p0, \[x0,z31\.s,sxtw\]
-.*:    847f0000        prfb    pldl1keep, p0, \[x0,z31\.s,sxtw\]
-.*:    847f0000        prfb    pldl1keep, p0, \[x0,z31\.s,sxtw\]
-.*:    c4200000        prfb    pldl1keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200000        prfb    pldl1keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200000        prfb    pldl1keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200001        prfb    pldl1strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200001        prfb    pldl1strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200001        prfb    pldl1strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200002        prfb    pldl2keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200002        prfb    pldl2keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200002        prfb    pldl2keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200003        prfb    pldl2strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200003        prfb    pldl2strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200003        prfb    pldl2strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200004        prfb    pldl3keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200004        prfb    pldl3keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200004        prfb    pldl3keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200005        prfb    pldl3strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200005        prfb    pldl3strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200005        prfb    pldl3strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200006        prfb    #6, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200006        prfb    #6, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200006        prfb    #6, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200007        prfb    #7, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200007        prfb    #7, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200007        prfb    #7, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200008        prfb    pstl1keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200008        prfb    pstl1keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200008        prfb    pstl1keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200009        prfb    pstl1strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200009        prfb    pstl1strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200009        prfb    pstl1strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000a        prfb    pstl2keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000a        prfb    pstl2keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000a        prfb    pstl2keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000b        prfb    pstl2strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000b        prfb    pstl2strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000b        prfb    pstl2strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000c        prfb    pstl3keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000c        prfb    pstl3keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000c        prfb    pstl3keep, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000d        prfb    pstl3strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000d        prfb    pstl3strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000d        prfb    pstl3strm, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000e        prfb    #14, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000e        prfb    #14, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000e        prfb    #14, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000f        prfb    #15, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000f        prfb    #15, p0, \[x0,z0\.d,uxtw\]
-.*:    c420000f        prfb    #15, p0, \[x0,z0\.d,uxtw\]
-.*:    c4200800        prfb    pldl1keep, p2, \[x0,z0\.d,uxtw\]
-.*:    c4200800        prfb    pldl1keep, p2, \[x0,z0\.d,uxtw\]
-.*:    c4200800        prfb    pldl1keep, p2, \[x0,z0\.d,uxtw\]
-.*:    c4201c00        prfb    pldl1keep, p7, \[x0,z0\.d,uxtw\]
-.*:    c4201c00        prfb    pldl1keep, p7, \[x0,z0\.d,uxtw\]
-.*:    c4201c00        prfb    pldl1keep, p7, \[x0,z0\.d,uxtw\]
-.*:    c4200060        prfb    pldl1keep, p0, \[x3,z0\.d,uxtw\]
-.*:    c4200060        prfb    pldl1keep, p0, \[x3,z0\.d,uxtw\]
-.*:    c4200060        prfb    pldl1keep, p0, \[x3,z0\.d,uxtw\]
-.*:    c42003e0        prfb    pldl1keep, p0, \[sp,z0\.d,uxtw\]
-.*:    c42003e0        prfb    pldl1keep, p0, \[sp,z0\.d,uxtw\]
-.*:    c42003e0        prfb    pldl1keep, p0, \[sp,z0\.d,uxtw\]
-.*:    c4240000        prfb    pldl1keep, p0, \[x0,z4\.d,uxtw\]
-.*:    c4240000        prfb    pldl1keep, p0, \[x0,z4\.d,uxtw\]
-.*:    c4240000        prfb    pldl1keep, p0, \[x0,z4\.d,uxtw\]
-.*:    c43f0000        prfb    pldl1keep, p0, \[x0,z31\.d,uxtw\]
-.*:    c43f0000        prfb    pldl1keep, p0, \[x0,z31\.d,uxtw\]
-.*:    c43f0000        prfb    pldl1keep, p0, \[x0,z31\.d,uxtw\]
-.*:    c4600000        prfb    pldl1keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600000        prfb    pldl1keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600000        prfb    pldl1keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600001        prfb    pldl1strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600001        prfb    pldl1strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600001        prfb    pldl1strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600002        prfb    pldl2keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600002        prfb    pldl2keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600002        prfb    pldl2keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600003        prfb    pldl2strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600003        prfb    pldl2strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600003        prfb    pldl2strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600004        prfb    pldl3keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600004        prfb    pldl3keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600004        prfb    pldl3keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600005        prfb    pldl3strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600005        prfb    pldl3strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600005        prfb    pldl3strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600006        prfb    #6, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600006        prfb    #6, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600006        prfb    #6, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600007        prfb    #7, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600007        prfb    #7, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600007        prfb    #7, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600008        prfb    pstl1keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600008        prfb    pstl1keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600008        prfb    pstl1keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600009        prfb    pstl1strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600009        prfb    pstl1strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600009        prfb    pstl1strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000a        prfb    pstl2keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000a        prfb    pstl2keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000a        prfb    pstl2keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000b        prfb    pstl2strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000b        prfb    pstl2strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000b        prfb    pstl2strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000c        prfb    pstl3keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000c        prfb    pstl3keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000c        prfb    pstl3keep, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000d        prfb    pstl3strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000d        prfb    pstl3strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000d        prfb    pstl3strm, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000e        prfb    #14, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000e        prfb    #14, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000e        prfb    #14, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000f        prfb    #15, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000f        prfb    #15, p0, \[x0,z0\.d,sxtw\]
-.*:    c460000f        prfb    #15, p0, \[x0,z0\.d,sxtw\]
-.*:    c4600800        prfb    pldl1keep, p2, \[x0,z0\.d,sxtw\]
-.*:    c4600800        prfb    pldl1keep, p2, \[x0,z0\.d,sxtw\]
-.*:    c4600800        prfb    pldl1keep, p2, \[x0,z0\.d,sxtw\]
-.*:    c4601c00        prfb    pldl1keep, p7, \[x0,z0\.d,sxtw\]
-.*:    c4601c00        prfb    pldl1keep, p7, \[x0,z0\.d,sxtw\]
-.*:    c4601c00        prfb    pldl1keep, p7, \[x0,z0\.d,sxtw\]
-.*:    c4600060        prfb    pldl1keep, p0, \[x3,z0\.d,sxtw\]
-.*:    c4600060        prfb    pldl1keep, p0, \[x3,z0\.d,sxtw\]
-.*:    c4600060        prfb    pldl1keep, p0, \[x3,z0\.d,sxtw\]
-.*:    c46003e0        prfb    pldl1keep, p0, \[sp,z0\.d,sxtw\]
-.*:    c46003e0        prfb    pldl1keep, p0, \[sp,z0\.d,sxtw\]
-.*:    c46003e0        prfb    pldl1keep, p0, \[sp,z0\.d,sxtw\]
-.*:    c4640000        prfb    pldl1keep, p0, \[x0,z4\.d,sxtw\]
-.*:    c4640000        prfb    pldl1keep, p0, \[x0,z4\.d,sxtw\]
-.*:    c4640000        prfb    pldl1keep, p0, \[x0,z4\.d,sxtw\]
-.*:    c47f0000        prfb    pldl1keep, p0, \[x0,z31\.d,sxtw\]
-.*:    c47f0000        prfb    pldl1keep, p0, \[x0,z31\.d,sxtw\]
-.*:    c47f0000        prfb    pldl1keep, p0, \[x0,z31\.d,sxtw\]
-.*:    c4608000        prfb    pldl1keep, p0, \[x0,z0\.d\]
-.*:    c4608000        prfb    pldl1keep, p0, \[x0,z0\.d\]
-.*:    c4608000        prfb    pldl1keep, p0, \[x0,z0\.d\]
-.*:    c4608001        prfb    pldl1strm, p0, \[x0,z0\.d\]
-.*:    c4608001        prfb    pldl1strm, p0, \[x0,z0\.d\]
-.*:    c4608001        prfb    pldl1strm, p0, \[x0,z0\.d\]
-.*:    c4608002        prfb    pldl2keep, p0, \[x0,z0\.d\]
-.*:    c4608002        prfb    pldl2keep, p0, \[x0,z0\.d\]
-.*:    c4608002        prfb    pldl2keep, p0, \[x0,z0\.d\]
-.*:    c4608003        prfb    pldl2strm, p0, \[x0,z0\.d\]
-.*:    c4608003        prfb    pldl2strm, p0, \[x0,z0\.d\]
-.*:    c4608003        prfb    pldl2strm, p0, \[x0,z0\.d\]
-.*:    c4608004        prfb    pldl3keep, p0, \[x0,z0\.d\]
-.*:    c4608004        prfb    pldl3keep, p0, \[x0,z0\.d\]
-.*:    c4608004        prfb    pldl3keep, p0, \[x0,z0\.d\]
-.*:    c4608005        prfb    pldl3strm, p0, \[x0,z0\.d\]
-.*:    c4608005        prfb    pldl3strm, p0, \[x0,z0\.d\]
-.*:    c4608005        prfb    pldl3strm, p0, \[x0,z0\.d\]
-.*:    c4608006        prfb    #6, p0, \[x0,z0\.d\]
-.*:    c4608006        prfb    #6, p0, \[x0,z0\.d\]
-.*:    c4608006        prfb    #6, p0, \[x0,z0\.d\]
-.*:    c4608007        prfb    #7, p0, \[x0,z0\.d\]
-.*:    c4608007        prfb    #7, p0, \[x0,z0\.d\]
-.*:    c4608007        prfb    #7, p0, \[x0,z0\.d\]
-.*:    c4608008        prfb    pstl1keep, p0, \[x0,z0\.d\]
-.*:    c4608008        prfb    pstl1keep, p0, \[x0,z0\.d\]
-.*:    c4608008        prfb    pstl1keep, p0, \[x0,z0\.d\]
-.*:    c4608009        prfb    pstl1strm, p0, \[x0,z0\.d\]
-.*:    c4608009        prfb    pstl1strm, p0, \[x0,z0\.d\]
-.*:    c4608009        prfb    pstl1strm, p0, \[x0,z0\.d\]
-.*:    c460800a        prfb    pstl2keep, p0, \[x0,z0\.d\]
-.*:    c460800a        prfb    pstl2keep, p0, \[x0,z0\.d\]
-.*:    c460800a        prfb    pstl2keep, p0, \[x0,z0\.d\]
-.*:    c460800b        prfb    pstl2strm, p0, \[x0,z0\.d\]
-.*:    c460800b        prfb    pstl2strm, p0, \[x0,z0\.d\]
-.*:    c460800b        prfb    pstl2strm, p0, \[x0,z0\.d\]
-.*:    c460800c        prfb    pstl3keep, p0, \[x0,z0\.d\]
-.*:    c460800c        prfb    pstl3keep, p0, \[x0,z0\.d\]
-.*:    c460800c        prfb    pstl3keep, p0, \[x0,z0\.d\]
-.*:    c460800d        prfb    pstl3strm, p0, \[x0,z0\.d\]
-.*:    c460800d        prfb    pstl3strm, p0, \[x0,z0\.d\]
-.*:    c460800d        prfb    pstl3strm, p0, \[x0,z0\.d\]
-.*:    c460800e        prfb    #14, p0, \[x0,z0\.d\]
-.*:    c460800e        prfb    #14, p0, \[x0,z0\.d\]
-.*:    c460800e        prfb    #14, p0, \[x0,z0\.d\]
-.*:    c460800f        prfb    #15, p0, \[x0,z0\.d\]
-.*:    c460800f        prfb    #15, p0, \[x0,z0\.d\]
-.*:    c460800f        prfb    #15, p0, \[x0,z0\.d\]
-.*:    c4608800        prfb    pldl1keep, p2, \[x0,z0\.d\]
-.*:    c4608800        prfb    pldl1keep, p2, \[x0,z0\.d\]
-.*:    c4608800        prfb    pldl1keep, p2, \[x0,z0\.d\]
-.*:    c4609c00        prfb    pldl1keep, p7, \[x0,z0\.d\]
-.*:    c4609c00        prfb    pldl1keep, p7, \[x0,z0\.d\]
-.*:    c4609c00        prfb    pldl1keep, p7, \[x0,z0\.d\]
-.*:    c4608060        prfb    pldl1keep, p0, \[x3,z0\.d\]
-.*:    c4608060        prfb    pldl1keep, p0, \[x3,z0\.d\]
-.*:    c4608060        prfb    pldl1keep, p0, \[x3,z0\.d\]
-.*:    c46083e0        prfb    pldl1keep, p0, \[sp,z0\.d\]
-.*:    c46083e0        prfb    pldl1keep, p0, \[sp,z0\.d\]
-.*:    c46083e0        prfb    pldl1keep, p0, \[sp,z0\.d\]
-.*:    c4648000        prfb    pldl1keep, p0, \[x0,z4\.d\]
-.*:    c4648000        prfb    pldl1keep, p0, \[x0,z4\.d\]
-.*:    c4648000        prfb    pldl1keep, p0, \[x0,z4\.d\]
-.*:    c47f8000        prfb    pldl1keep, p0, \[x0,z31\.d\]
-.*:    c47f8000        prfb    pldl1keep, p0, \[x0,z31\.d\]
-.*:    c47f8000        prfb    pldl1keep, p0, \[x0,z31\.d\]
+.*:    8400c000        prfb    pldl1keep, p0, \[x0, x0\]
+.*:    8400c000        prfb    pldl1keep, p0, \[x0, x0\]
+.*:    8400c000        prfb    pldl1keep, p0, \[x0, x0\]
+.*:    8400c001        prfb    pldl1strm, p0, \[x0, x0\]
+.*:    8400c001        prfb    pldl1strm, p0, \[x0, x0\]
+.*:    8400c001        prfb    pldl1strm, p0, \[x0, x0\]
+.*:    8400c002        prfb    pldl2keep, p0, \[x0, x0\]
+.*:    8400c002        prfb    pldl2keep, p0, \[x0, x0\]
+.*:    8400c002        prfb    pldl2keep, p0, \[x0, x0\]
+.*:    8400c003        prfb    pldl2strm, p0, \[x0, x0\]
+.*:    8400c003        prfb    pldl2strm, p0, \[x0, x0\]
+.*:    8400c003        prfb    pldl2strm, p0, \[x0, x0\]
+.*:    8400c004        prfb    pldl3keep, p0, \[x0, x0\]
+.*:    8400c004        prfb    pldl3keep, p0, \[x0, x0\]
+.*:    8400c004        prfb    pldl3keep, p0, \[x0, x0\]
+.*:    8400c005        prfb    pldl3strm, p0, \[x0, x0\]
+.*:    8400c005        prfb    pldl3strm, p0, \[x0, x0\]
+.*:    8400c005        prfb    pldl3strm, p0, \[x0, x0\]
+.*:    8400c006        prfb    #6, p0, \[x0, x0\]
+.*:    8400c006        prfb    #6, p0, \[x0, x0\]
+.*:    8400c006        prfb    #6, p0, \[x0, x0\]
+.*:    8400c007        prfb    #7, p0, \[x0, x0\]
+.*:    8400c007        prfb    #7, p0, \[x0, x0\]
+.*:    8400c007        prfb    #7, p0, \[x0, x0\]
+.*:    8400c008        prfb    pstl1keep, p0, \[x0, x0\]
+.*:    8400c008        prfb    pstl1keep, p0, \[x0, x0\]
+.*:    8400c008        prfb    pstl1keep, p0, \[x0, x0\]
+.*:    8400c009        prfb    pstl1strm, p0, \[x0, x0\]
+.*:    8400c009        prfb    pstl1strm, p0, \[x0, x0\]
+.*:    8400c009        prfb    pstl1strm, p0, \[x0, x0\]
+.*:    8400c00a        prfb    pstl2keep, p0, \[x0, x0\]
+.*:    8400c00a        prfb    pstl2keep, p0, \[x0, x0\]
+.*:    8400c00a        prfb    pstl2keep, p0, \[x0, x0\]
+.*:    8400c00b        prfb    pstl2strm, p0, \[x0, x0\]
+.*:    8400c00b        prfb    pstl2strm, p0, \[x0, x0\]
+.*:    8400c00b        prfb    pstl2strm, p0, \[x0, x0\]
+.*:    8400c00c        prfb    pstl3keep, p0, \[x0, x0\]
+.*:    8400c00c        prfb    pstl3keep, p0, \[x0, x0\]
+.*:    8400c00c        prfb    pstl3keep, p0, \[x0, x0\]
+.*:    8400c00d        prfb    pstl3strm, p0, \[x0, x0\]
+.*:    8400c00d        prfb    pstl3strm, p0, \[x0, x0\]
+.*:    8400c00d        prfb    pstl3strm, p0, \[x0, x0\]
+.*:    8400c00e        prfb    #14, p0, \[x0, x0\]
+.*:    8400c00e        prfb    #14, p0, \[x0, x0\]
+.*:    8400c00e        prfb    #14, p0, \[x0, x0\]
+.*:    8400c00f        prfb    #15, p0, \[x0, x0\]
+.*:    8400c00f        prfb    #15, p0, \[x0, x0\]
+.*:    8400c00f        prfb    #15, p0, \[x0, x0\]
+.*:    8400c800        prfb    pldl1keep, p2, \[x0, x0\]
+.*:    8400c800        prfb    pldl1keep, p2, \[x0, x0\]
+.*:    8400c800        prfb    pldl1keep, p2, \[x0, x0\]
+.*:    8400dc00        prfb    pldl1keep, p7, \[x0, x0\]
+.*:    8400dc00        prfb    pldl1keep, p7, \[x0, x0\]
+.*:    8400dc00        prfb    pldl1keep, p7, \[x0, x0\]
+.*:    8400c060        prfb    pldl1keep, p0, \[x3, x0\]
+.*:    8400c060        prfb    pldl1keep, p0, \[x3, x0\]
+.*:    8400c060        prfb    pldl1keep, p0, \[x3, x0\]
+.*:    8400c3e0        prfb    pldl1keep, p0, \[sp, x0\]
+.*:    8400c3e0        prfb    pldl1keep, p0, \[sp, x0\]
+.*:    8400c3e0        prfb    pldl1keep, p0, \[sp, x0\]
+.*:    8404c000        prfb    pldl1keep, p0, \[x0, x4\]
+.*:    8404c000        prfb    pldl1keep, p0, \[x0, x4\]
+.*:    8404c000        prfb    pldl1keep, p0, \[x0, x4\]
+.*:    841ec000        prfb    pldl1keep, p0, \[x0, x30\]
+.*:    841ec000        prfb    pldl1keep, p0, \[x0, x30\]
+.*:    841ec000        prfb    pldl1keep, p0, \[x0, x30\]
+.*:    84200000        prfb    pldl1keep, p0, \[x0, z0\.s, uxtw\]
+.*:    84200000        prfb    pldl1keep, p0, \[x0, z0\.s, uxtw\]
+.*:    84200000        prfb    pldl1keep, p0, \[x0, z0\.s, uxtw\]
+.*:    84200001        prfb    pldl1strm, p0, \[x0, z0\.s, uxtw\]
+.*:    84200001        prfb    pldl1strm, p0, \[x0, z0\.s, uxtw\]
+.*:    84200001        prfb    pldl1strm, p0, \[x0, z0\.s, uxtw\]
+.*:    84200002        prfb    pldl2keep, p0, \[x0, z0\.s, uxtw\]
+.*:    84200002        prfb    pldl2keep, p0, \[x0, z0\.s, uxtw\]
+.*:    84200002        prfb    pldl2keep, p0, \[x0, z0\.s, uxtw\]
+.*:    84200003        prfb    pldl2strm, p0, \[x0, z0\.s, uxtw\]
+.*:    84200003        prfb    pldl2strm, p0, \[x0, z0\.s, uxtw\]
+.*:    84200003        prfb    pldl2strm, p0, \[x0, z0\.s, uxtw\]
+.*:    84200004        prfb    pldl3keep, p0, \[x0, z0\.s, uxtw\]
+.*:    84200004        prfb    pldl3keep, p0, \[x0, z0\.s, uxtw\]
+.*:    84200004        prfb    pldl3keep, p0, \[x0, z0\.s, uxtw\]
+.*:    84200005        prfb    pldl3strm, p0, \[x0, z0\.s, uxtw\]
+.*:    84200005        prfb    pldl3strm, p0, \[x0, z0\.s, uxtw\]
+.*:    84200005        prfb    pldl3strm, p0, \[x0, z0\.s, uxtw\]
+.*:    84200006        prfb    #6, p0, \[x0, z0\.s, uxtw\]
+.*:    84200006        prfb    #6, p0, \[x0, z0\.s, uxtw\]
+.*:    84200006        prfb    #6, p0, \[x0, z0\.s, uxtw\]
+.*:    84200007        prfb    #7, p0, \[x0, z0\.s, uxtw\]
+.*:    84200007        prfb    #7, p0, \[x0, z0\.s, uxtw\]
+.*:    84200007        prfb    #7, p0, \[x0, z0\.s, uxtw\]
+.*:    84200008        prfb    pstl1keep, p0, \[x0, z0\.s, uxtw\]
+.*:    84200008        prfb    pstl1keep, p0, \[x0, z0\.s, uxtw\]
+.*:    84200008        prfb    pstl1keep, p0, \[x0, z0\.s, uxtw\]
+.*:    84200009        prfb    pstl1strm, p0, \[x0, z0\.s, uxtw\]
+.*:    84200009        prfb    pstl1strm, p0, \[x0, z0\.s, uxtw\]
+.*:    84200009        prfb    pstl1strm, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000a        prfb    pstl2keep, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000a        prfb    pstl2keep, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000a        prfb    pstl2keep, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000b        prfb    pstl2strm, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000b        prfb    pstl2strm, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000b        prfb    pstl2strm, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000c        prfb    pstl3keep, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000c        prfb    pstl3keep, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000c        prfb    pstl3keep, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000d        prfb    pstl3strm, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000d        prfb    pstl3strm, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000d        prfb    pstl3strm, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000e        prfb    #14, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000e        prfb    #14, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000e        prfb    #14, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000f        prfb    #15, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000f        prfb    #15, p0, \[x0, z0\.s, uxtw\]
+.*:    8420000f        prfb    #15, p0, \[x0, z0\.s, uxtw\]
+.*:    84200800        prfb    pldl1keep, p2, \[x0, z0\.s, uxtw\]
+.*:    84200800        prfb    pldl1keep, p2, \[x0, z0\.s, uxtw\]
+.*:    84200800        prfb    pldl1keep, p2, \[x0, z0\.s, uxtw\]
+.*:    84201c00        prfb    pldl1keep, p7, \[x0, z0\.s, uxtw\]
+.*:    84201c00        prfb    pldl1keep, p7, \[x0, z0\.s, uxtw\]
+.*:    84201c00        prfb    pldl1keep, p7, \[x0, z0\.s, uxtw\]
+.*:    84200060        prfb    pldl1keep, p0, \[x3, z0\.s, uxtw\]
+.*:    84200060        prfb    pldl1keep, p0, \[x3, z0\.s, uxtw\]
+.*:    84200060        prfb    pldl1keep, p0, \[x3, z0\.s, uxtw\]
+.*:    842003e0        prfb    pldl1keep, p0, \[sp, z0\.s, uxtw\]
+.*:    842003e0        prfb    pldl1keep, p0, \[sp, z0\.s, uxtw\]
+.*:    842003e0        prfb    pldl1keep, p0, \[sp, z0\.s, uxtw\]
+.*:    84240000        prfb    pldl1keep, p0, \[x0, z4\.s, uxtw\]
+.*:    84240000        prfb    pldl1keep, p0, \[x0, z4\.s, uxtw\]
+.*:    84240000        prfb    pldl1keep, p0, \[x0, z4\.s, uxtw\]
+.*:    843f0000        prfb    pldl1keep, p0, \[x0, z31\.s, uxtw\]
+.*:    843f0000        prfb    pldl1keep, p0, \[x0, z31\.s, uxtw\]
+.*:    843f0000        prfb    pldl1keep, p0, \[x0, z31\.s, uxtw\]
+.*:    84600000        prfb    pldl1keep, p0, \[x0, z0\.s, sxtw\]
+.*:    84600000        prfb    pldl1keep, p0, \[x0, z0\.s, sxtw\]
+.*:    84600000        prfb    pldl1keep, p0, \[x0, z0\.s, sxtw\]
+.*:    84600001        prfb    pldl1strm, p0, \[x0, z0\.s, sxtw\]
+.*:    84600001        prfb    pldl1strm, p0, \[x0, z0\.s, sxtw\]
+.*:    84600001        prfb    pldl1strm, p0, \[x0, z0\.s, sxtw\]
+.*:    84600002        prfb    pldl2keep, p0, \[x0, z0\.s, sxtw\]
+.*:    84600002        prfb    pldl2keep, p0, \[x0, z0\.s, sxtw\]
+.*:    84600002        prfb    pldl2keep, p0, \[x0, z0\.s, sxtw\]
+.*:    84600003        prfb    pldl2strm, p0, \[x0, z0\.s, sxtw\]
+.*:    84600003        prfb    pldl2strm, p0, \[x0, z0\.s, sxtw\]
+.*:    84600003        prfb    pldl2strm, p0, \[x0, z0\.s, sxtw\]
+.*:    84600004        prfb    pldl3keep, p0, \[x0, z0\.s, sxtw\]
+.*:    84600004        prfb    pldl3keep, p0, \[x0, z0\.s, sxtw\]
+.*:    84600004        prfb    pldl3keep, p0, \[x0, z0\.s, sxtw\]
+.*:    84600005        prfb    pldl3strm, p0, \[x0, z0\.s, sxtw\]
+.*:    84600005        prfb    pldl3strm, p0, \[x0, z0\.s, sxtw\]
+.*:    84600005        prfb    pldl3strm, p0, \[x0, z0\.s, sxtw\]
+.*:    84600006        prfb    #6, p0, \[x0, z0\.s, sxtw\]
+.*:    84600006        prfb    #6, p0, \[x0, z0\.s, sxtw\]
+.*:    84600006        prfb    #6, p0, \[x0, z0\.s, sxtw\]
+.*:    84600007        prfb    #7, p0, \[x0, z0\.s, sxtw\]
+.*:    84600007        prfb    #7, p0, \[x0, z0\.s, sxtw\]
+.*:    84600007        prfb    #7, p0, \[x0, z0\.s, sxtw\]
+.*:    84600008        prfb    pstl1keep, p0, \[x0, z0\.s, sxtw\]
+.*:    84600008        prfb    pstl1keep, p0, \[x0, z0\.s, sxtw\]
+.*:    84600008        prfb    pstl1keep, p0, \[x0, z0\.s, sxtw\]
+.*:    84600009        prfb    pstl1strm, p0, \[x0, z0\.s, sxtw\]
+.*:    84600009        prfb    pstl1strm, p0, \[x0, z0\.s, sxtw\]
+.*:    84600009        prfb    pstl1strm, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000a        prfb    pstl2keep, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000a        prfb    pstl2keep, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000a        prfb    pstl2keep, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000b        prfb    pstl2strm, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000b        prfb    pstl2strm, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000b        prfb    pstl2strm, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000c        prfb    pstl3keep, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000c        prfb    pstl3keep, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000c        prfb    pstl3keep, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000d        prfb    pstl3strm, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000d        prfb    pstl3strm, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000d        prfb    pstl3strm, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000e        prfb    #14, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000e        prfb    #14, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000e        prfb    #14, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000f        prfb    #15, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000f        prfb    #15, p0, \[x0, z0\.s, sxtw\]
+.*:    8460000f        prfb    #15, p0, \[x0, z0\.s, sxtw\]
+.*:    84600800        prfb    pldl1keep, p2, \[x0, z0\.s, sxtw\]
+.*:    84600800        prfb    pldl1keep, p2, \[x0, z0\.s, sxtw\]
+.*:    84600800        prfb    pldl1keep, p2, \[x0, z0\.s, sxtw\]
+.*:    84601c00        prfb    pldl1keep, p7, \[x0, z0\.s, sxtw\]
+.*:    84601c00        prfb    pldl1keep, p7, \[x0, z0\.s, sxtw\]
+.*:    84601c00        prfb    pldl1keep, p7, \[x0, z0\.s, sxtw\]
+.*:    84600060        prfb    pldl1keep, p0, \[x3, z0\.s, sxtw\]
+.*:    84600060        prfb    pldl1keep, p0, \[x3, z0\.s, sxtw\]
+.*:    84600060        prfb    pldl1keep, p0, \[x3, z0\.s, sxtw\]
+.*:    846003e0        prfb    pldl1keep, p0, \[sp, z0\.s, sxtw\]
+.*:    846003e0        prfb    pldl1keep, p0, \[sp, z0\.s, sxtw\]
+.*:    846003e0        prfb    pldl1keep, p0, \[sp, z0\.s, sxtw\]
+.*:    84640000        prfb    pldl1keep, p0, \[x0, z4\.s, sxtw\]
+.*:    84640000        prfb    pldl1keep, p0, \[x0, z4\.s, sxtw\]
+.*:    84640000        prfb    pldl1keep, p0, \[x0, z4\.s, sxtw\]
+.*:    847f0000        prfb    pldl1keep, p0, \[x0, z31\.s, sxtw\]
+.*:    847f0000        prfb    pldl1keep, p0, \[x0, z31\.s, sxtw\]
+.*:    847f0000        prfb    pldl1keep, p0, \[x0, z31\.s, sxtw\]
+.*:    c4200000        prfb    pldl1keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200000        prfb    pldl1keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200000        prfb    pldl1keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200001        prfb    pldl1strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200001        prfb    pldl1strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200001        prfb    pldl1strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200002        prfb    pldl2keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200002        prfb    pldl2keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200002        prfb    pldl2keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200003        prfb    pldl2strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200003        prfb    pldl2strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200003        prfb    pldl2strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200004        prfb    pldl3keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200004        prfb    pldl3keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200004        prfb    pldl3keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200005        prfb    pldl3strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200005        prfb    pldl3strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200005        prfb    pldl3strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200006        prfb    #6, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200006        prfb    #6, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200006        prfb    #6, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200007        prfb    #7, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200007        prfb    #7, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200007        prfb    #7, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200008        prfb    pstl1keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200008        prfb    pstl1keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200008        prfb    pstl1keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200009        prfb    pstl1strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200009        prfb    pstl1strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200009        prfb    pstl1strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000a        prfb    pstl2keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000a        prfb    pstl2keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000a        prfb    pstl2keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000b        prfb    pstl2strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000b        prfb    pstl2strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000b        prfb    pstl2strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000c        prfb    pstl3keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000c        prfb    pstl3keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000c        prfb    pstl3keep, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000d        prfb    pstl3strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000d        prfb    pstl3strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000d        prfb    pstl3strm, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000e        prfb    #14, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000e        prfb    #14, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000e        prfb    #14, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000f        prfb    #15, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000f        prfb    #15, p0, \[x0, z0\.d, uxtw\]
+.*:    c420000f        prfb    #15, p0, \[x0, z0\.d, uxtw\]
+.*:    c4200800        prfb    pldl1keep, p2, \[x0, z0\.d, uxtw\]
+.*:    c4200800        prfb    pldl1keep, p2, \[x0, z0\.d, uxtw\]
+.*:    c4200800        prfb    pldl1keep, p2, \[x0, z0\.d, uxtw\]
+.*:    c4201c00        prfb    pldl1keep, p7, \[x0, z0\.d, uxtw\]
+.*:    c4201c00        prfb    pldl1keep, p7, \[x0, z0\.d, uxtw\]
+.*:    c4201c00        prfb    pldl1keep, p7, \[x0, z0\.d, uxtw\]
+.*:    c4200060        prfb    pldl1keep, p0, \[x3, z0\.d, uxtw\]
+.*:    c4200060        prfb    pldl1keep, p0, \[x3, z0\.d, uxtw\]
+.*:    c4200060        prfb    pldl1keep, p0, \[x3, z0\.d, uxtw\]
+.*:    c42003e0        prfb    pldl1keep, p0, \[sp, z0\.d, uxtw\]
+.*:    c42003e0        prfb    pldl1keep, p0, \[sp, z0\.d, uxtw\]
+.*:    c42003e0        prfb    pldl1keep, p0, \[sp, z0\.d, uxtw\]
+.*:    c4240000        prfb    pldl1keep, p0, \[x0, z4\.d, uxtw\]
+.*:    c4240000        prfb    pldl1keep, p0, \[x0, z4\.d, uxtw\]
+.*:    c4240000        prfb    pldl1keep, p0, \[x0, z4\.d, uxtw\]
+.*:    c43f0000        prfb    pldl1keep, p0, \[x0, z31\.d, uxtw\]
+.*:    c43f0000        prfb    pldl1keep, p0, \[x0, z31\.d, uxtw\]
+.*:    c43f0000        prfb    pldl1keep, p0, \[x0, z31\.d, uxtw\]
+.*:    c4600000        prfb    pldl1keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600000        prfb    pldl1keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600000        prfb    pldl1keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600001        prfb    pldl1strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600001        prfb    pldl1strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600001        prfb    pldl1strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600002        prfb    pldl2keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600002        prfb    pldl2keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600002        prfb    pldl2keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600003        prfb    pldl2strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600003        prfb    pldl2strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600003        prfb    pldl2strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600004        prfb    pldl3keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600004        prfb    pldl3keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600004        prfb    pldl3keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600005        prfb    pldl3strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600005        prfb    pldl3strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600005        prfb    pldl3strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600006        prfb    #6, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600006        prfb    #6, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600006        prfb    #6, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600007        prfb    #7, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600007        prfb    #7, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600007        prfb    #7, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600008        prfb    pstl1keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600008        prfb    pstl1keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600008        prfb    pstl1keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600009        prfb    pstl1strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600009        prfb    pstl1strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600009        prfb    pstl1strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000a        prfb    pstl2keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000a        prfb    pstl2keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000a        prfb    pstl2keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000b        prfb    pstl2strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000b        prfb    pstl2strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000b        prfb    pstl2strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000c        prfb    pstl3keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000c        prfb    pstl3keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000c        prfb    pstl3keep, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000d        prfb    pstl3strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000d        prfb    pstl3strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000d        prfb    pstl3strm, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000e        prfb    #14, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000e        prfb    #14, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000e        prfb    #14, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000f        prfb    #15, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000f        prfb    #15, p0, \[x0, z0\.d, sxtw\]
+.*:    c460000f        prfb    #15, p0, \[x0, z0\.d, sxtw\]
+.*:    c4600800        prfb    pldl1keep, p2, \[x0, z0\.d, sxtw\]
+.*:    c4600800        prfb    pldl1keep, p2, \[x0, z0\.d, sxtw\]
+.*:    c4600800        prfb    pldl1keep, p2, \[x0, z0\.d, sxtw\]
+.*:    c4601c00        prfb    pldl1keep, p7, \[x0, z0\.d, sxtw\]
+.*:    c4601c00        prfb    pldl1keep, p7, \[x0, z0\.d, sxtw\]
+.*:    c4601c00        prfb    pldl1keep, p7, \[x0, z0\.d, sxtw\]
+.*:    c4600060        prfb    pldl1keep, p0, \[x3, z0\.d, sxtw\]
+.*:    c4600060        prfb    pldl1keep, p0, \[x3, z0\.d, sxtw\]
+.*:    c4600060        prfb    pldl1keep, p0, \[x3, z0\.d, sxtw\]
+.*:    c46003e0        prfb    pldl1keep, p0, \[sp, z0\.d, sxtw\]
+.*:    c46003e0        prfb    pldl1keep, p0, \[sp, z0\.d, sxtw\]
+.*:    c46003e0        prfb    pldl1keep, p0, \[sp, z0\.d, sxtw\]
+.*:    c4640000        prfb    pldl1keep, p0, \[x0, z4\.d, sxtw\]
+.*:    c4640000        prfb    pldl1keep, p0, \[x0, z4\.d, sxtw\]
+.*:    c4640000        prfb    pldl1keep, p0, \[x0, z4\.d, sxtw\]
+.*:    c47f0000        prfb    pldl1keep, p0, \[x0, z31\.d, sxtw\]
+.*:    c47f0000        prfb    pldl1keep, p0, \[x0, z31\.d, sxtw\]
+.*:    c47f0000        prfb    pldl1keep, p0, \[x0, z31\.d, sxtw\]
+.*:    c4608000        prfb    pldl1keep, p0, \[x0, z0\.d\]
+.*:    c4608000        prfb    pldl1keep, p0, \[x0, z0\.d\]
+.*:    c4608000        prfb    pldl1keep, p0, \[x0, z0\.d\]
+.*:    c4608001        prfb    pldl1strm, p0, \[x0, z0\.d\]
+.*:    c4608001        prfb    pldl1strm, p0, \[x0, z0\.d\]
+.*:    c4608001        prfb    pldl1strm, p0, \[x0, z0\.d\]
+.*:    c4608002        prfb    pldl2keep, p0, \[x0, z0\.d\]
+.*:    c4608002        prfb    pldl2keep, p0, \[x0, z0\.d\]
+.*:    c4608002        prfb    pldl2keep, p0, \[x0, z0\.d\]
+.*:    c4608003        prfb    pldl2strm, p0, \[x0, z0\.d\]
+.*:    c4608003        prfb    pldl2strm, p0, \[x0, z0\.d\]
+.*:    c4608003        prfb    pldl2strm, p0, \[x0, z0\.d\]
+.*:    c4608004        prfb    pldl3keep, p0, \[x0, z0\.d\]
+.*:    c4608004        prfb    pldl3keep, p0, \[x0, z0\.d\]
+.*:    c4608004        prfb    pldl3keep, p0, \[x0, z0\.d\]
+.*:    c4608005        prfb    pldl3strm, p0, \[x0, z0\.d\]
+.*:    c4608005        prfb    pldl3strm, p0, \[x0, z0\.d\]
+.*:    c4608005        prfb    pldl3strm, p0, \[x0, z0\.d\]
+.*:    c4608006        prfb    #6, p0, \[x0, z0\.d\]
+.*:    c4608006        prfb    #6, p0, \[x0, z0\.d\]
+.*:    c4608006        prfb    #6, p0, \[x0, z0\.d\]
+.*:    c4608007        prfb    #7, p0, \[x0, z0\.d\]
+.*:    c4608007        prfb    #7, p0, \[x0, z0\.d\]
+.*:    c4608007        prfb    #7, p0, \[x0, z0\.d\]
+.*:    c4608008        prfb    pstl1keep, p0, \[x0, z0\.d\]
+.*:    c4608008        prfb    pstl1keep, p0, \[x0, z0\.d\]
+.*:    c4608008        prfb    pstl1keep, p0, \[x0, z0\.d\]
+.*:    c4608009        prfb    pstl1strm, p0, \[x0, z0\.d\]
+.*:    c4608009        prfb    pstl1strm, p0, \[x0, z0\.d\]
+.*:    c4608009        prfb    pstl1strm, p0, \[x0, z0\.d\]
+.*:    c460800a        prfb    pstl2keep, p0, \[x0, z0\.d\]
+.*:    c460800a        prfb    pstl2keep, p0, \[x0, z0\.d\]
+.*:    c460800a        prfb    pstl2keep, p0, \[x0, z0\.d\]
+.*:    c460800b        prfb    pstl2strm, p0, \[x0, z0\.d\]
+.*:    c460800b        prfb    pstl2strm, p0, \[x0, z0\.d\]
+.*:    c460800b        prfb    pstl2strm, p0, \[x0, z0\.d\]
+.*:    c460800c        prfb    pstl3keep, p0, \[x0, z0\.d\]
+.*:    c460800c        prfb    pstl3keep, p0, \[x0, z0\.d\]
+.*:    c460800c        prfb    pstl3keep, p0, \[x0, z0\.d\]
+.*:    c460800d        prfb    pstl3strm, p0, \[x0, z0\.d\]
+.*:    c460800d        prfb    pstl3strm, p0, \[x0, z0\.d\]
+.*:    c460800d        prfb    pstl3strm, p0, \[x0, z0\.d\]
+.*:    c460800e        prfb    #14, p0, \[x0, z0\.d\]
+.*:    c460800e        prfb    #14, p0, \[x0, z0\.d\]
+.*:    c460800e        prfb    #14, p0, \[x0, z0\.d\]
+.*:    c460800f        prfb    #15, p0, \[x0, z0\.d\]
+.*:    c460800f        prfb    #15, p0, \[x0, z0\.d\]
+.*:    c460800f        prfb    #15, p0, \[x0, z0\.d\]
+.*:    c4608800        prfb    pldl1keep, p2, \[x0, z0\.d\]
+.*:    c4608800        prfb    pldl1keep, p2, \[x0, z0\.d\]
+.*:    c4608800        prfb    pldl1keep, p2, \[x0, z0\.d\]
+.*:    c4609c00        prfb    pldl1keep, p7, \[x0, z0\.d\]
+.*:    c4609c00        prfb    pldl1keep, p7, \[x0, z0\.d\]
+.*:    c4609c00        prfb    pldl1keep, p7, \[x0, z0\.d\]
+.*:    c4608060        prfb    pldl1keep, p0, \[x3, z0\.d\]
+.*:    c4608060        prfb    pldl1keep, p0, \[x3, z0\.d\]
+.*:    c4608060        prfb    pldl1keep, p0, \[x3, z0\.d\]
+.*:    c46083e0        prfb    pldl1keep, p0, \[sp, z0\.d\]
+.*:    c46083e0        prfb    pldl1keep, p0, \[sp, z0\.d\]
+.*:    c46083e0        prfb    pldl1keep, p0, \[sp, z0\.d\]
+.*:    c4648000        prfb    pldl1keep, p0, \[x0, z4\.d\]
+.*:    c4648000        prfb    pldl1keep, p0, \[x0, z4\.d\]
+.*:    c4648000        prfb    pldl1keep, p0, \[x0, z4\.d\]
+.*:    c47f8000        prfb    pldl1keep, p0, \[x0, z31\.d\]
+.*:    c47f8000        prfb    pldl1keep, p0, \[x0, z31\.d\]
+.*:    c47f8000        prfb    pldl1keep, p0, \[x0, z31\.d\]
 .*:    8400e000        prfb    pldl1keep, p0, \[z0\.s\]
 .*:    8400e000        prfb    pldl1keep, p0, \[z0\.s\]
 .*:    8400e000        prfb    pldl1keep, p0, \[z0\.s\]
@@ -22442,14 +22442,14 @@ Disassembly of section .*:
 .*:    8400e3e0        prfb    pldl1keep, p0, \[z31\.s\]
 .*:    8400e3e0        prfb    pldl1keep, p0, \[z31\.s\]
 .*:    8400e3e0        prfb    pldl1keep, p0, \[z31\.s\]
-.*:    840fe000        prfb    pldl1keep, p0, \[z0\.s,#15\]
-.*:    840fe000        prfb    pldl1keep, p0, \[z0\.s,#15\]
-.*:    8410e000        prfb    pldl1keep, p0, \[z0\.s,#16\]
-.*:    8410e000        prfb    pldl1keep, p0, \[z0\.s,#16\]
-.*:    8411e000        prfb    pldl1keep, p0, \[z0\.s,#17\]
-.*:    8411e000        prfb    pldl1keep, p0, \[z0\.s,#17\]
-.*:    841fe000        prfb    pldl1keep, p0, \[z0\.s,#31\]
-.*:    841fe000        prfb    pldl1keep, p0, \[z0\.s,#31\]
+.*:    840fe000        prfb    pldl1keep, p0, \[z0\.s, #15\]
+.*:    840fe000        prfb    pldl1keep, p0, \[z0\.s, #15\]
+.*:    8410e000        prfb    pldl1keep, p0, \[z0\.s, #16\]
+.*:    8410e000        prfb    pldl1keep, p0, \[z0\.s, #16\]
+.*:    8411e000        prfb    pldl1keep, p0, \[z0\.s, #17\]
+.*:    8411e000        prfb    pldl1keep, p0, \[z0\.s, #17\]
+.*:    841fe000        prfb    pldl1keep, p0, \[z0\.s, #31\]
+.*:    841fe000        prfb    pldl1keep, p0, \[z0\.s, #31\]
 .*:    85c00000        prfb    pldl1keep, p0, \[x0\]
 .*:    85c00000        prfb    pldl1keep, p0, \[x0\]
 .*:    85c00000        prfb    pldl1keep, p0, \[x0\]
@@ -22530,14 +22530,14 @@ Disassembly of section .*:
 .*:    85c003e0        prfb    pldl1keep, p0, \[sp\]
 .*:    85c003e0        prfb    pldl1keep, p0, \[sp\]
 .*:    85c003e0        prfb    pldl1keep, p0, \[sp\]
-.*:    85df0000        prfb    pldl1keep, p0, \[x0,#31,mul vl\]
-.*:    85df0000        prfb    pldl1keep, p0, \[x0,#31,mul vl\]
-.*:    85e00000        prfb    pldl1keep, p0, \[x0,#-32,mul vl\]
-.*:    85e00000        prfb    pldl1keep, p0, \[x0,#-32,mul vl\]
-.*:    85e10000        prfb    pldl1keep, p0, \[x0,#-31,mul vl\]
-.*:    85e10000        prfb    pldl1keep, p0, \[x0,#-31,mul vl\]
-.*:    85ff0000        prfb    pldl1keep, p0, \[x0,#-1,mul vl\]
-.*:    85ff0000        prfb    pldl1keep, p0, \[x0,#-1,mul vl\]
+.*:    85df0000        prfb    pldl1keep, p0, \[x0, #31, mul vl\]
+.*:    85df0000        prfb    pldl1keep, p0, \[x0, #31, mul vl\]
+.*:    85e00000        prfb    pldl1keep, p0, \[x0, #-32, mul vl\]
+.*:    85e00000        prfb    pldl1keep, p0, \[x0, #-32, mul vl\]
+.*:    85e10000        prfb    pldl1keep, p0, \[x0, #-31, mul vl\]
+.*:    85e10000        prfb    pldl1keep, p0, \[x0, #-31, mul vl\]
+.*:    85ff0000        prfb    pldl1keep, p0, \[x0, #-1, mul vl\]
+.*:    85ff0000        prfb    pldl1keep, p0, \[x0, #-1, mul vl\]
 .*:    c400e000        prfb    pldl1keep, p0, \[z0\.d\]
 .*:    c400e000        prfb    pldl1keep, p0, \[z0\.d\]
 .*:    c400e000        prfb    pldl1keep, p0, \[z0\.d\]
@@ -22598,278 +22598,278 @@ Disassembly of section .*:
 .*:    c400e3e0        prfb    pldl1keep, p0, \[z31\.d\]
 .*:    c400e3e0        prfb    pldl1keep, p0, \[z31\.d\]
 .*:    c400e3e0        prfb    pldl1keep, p0, \[z31\.d\]
-.*:    c40fe000        prfb    pldl1keep, p0, \[z0\.d,#15\]
-.*:    c40fe000        prfb    pldl1keep, p0, \[z0\.d,#15\]
-.*:    c410e000        prfb    pldl1keep, p0, \[z0\.d,#16\]
-.*:    c410e000        prfb    pldl1keep, p0, \[z0\.d,#16\]
-.*:    c411e000        prfb    pldl1keep, p0, \[z0\.d,#17\]
-.*:    c411e000        prfb    pldl1keep, p0, \[z0\.d,#17\]
-.*:    c41fe000        prfb    pldl1keep, p0, \[z0\.d,#31\]
-.*:    c41fe000        prfb    pldl1keep, p0, \[z0\.d,#31\]
-.*:    84206000        prfd    pldl1keep, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206000        prfd    pldl1keep, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206001        prfd    pldl1strm, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206001        prfd    pldl1strm, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206002        prfd    pldl2keep, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206002        prfd    pldl2keep, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206003        prfd    pldl2strm, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206003        prfd    pldl2strm, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206004        prfd    pldl3keep, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206004        prfd    pldl3keep, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206005        prfd    pldl3strm, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206005        prfd    pldl3strm, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206006        prfd    #6, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206006        prfd    #6, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206007        prfd    #7, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206007        prfd    #7, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206008        prfd    pstl1keep, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206008        prfd    pstl1keep, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206009        prfd    pstl1strm, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206009        prfd    pstl1strm, p0, \[x0,z0\.s,uxtw #3\]
-.*:    8420600a        prfd    pstl2keep, p0, \[x0,z0\.s,uxtw #3\]
-.*:    8420600a        prfd    pstl2keep, p0, \[x0,z0\.s,uxtw #3\]
-.*:    8420600b        prfd    pstl2strm, p0, \[x0,z0\.s,uxtw #3\]
-.*:    8420600b        prfd    pstl2strm, p0, \[x0,z0\.s,uxtw #3\]
-.*:    8420600c        prfd    pstl3keep, p0, \[x0,z0\.s,uxtw #3\]
-.*:    8420600c        prfd    pstl3keep, p0, \[x0,z0\.s,uxtw #3\]
-.*:    8420600d        prfd    pstl3strm, p0, \[x0,z0\.s,uxtw #3\]
-.*:    8420600d        prfd    pstl3strm, p0, \[x0,z0\.s,uxtw #3\]
-.*:    8420600e        prfd    #14, p0, \[x0,z0\.s,uxtw #3\]
-.*:    8420600e        prfd    #14, p0, \[x0,z0\.s,uxtw #3\]
-.*:    8420600f        prfd    #15, p0, \[x0,z0\.s,uxtw #3\]
-.*:    8420600f        prfd    #15, p0, \[x0,z0\.s,uxtw #3\]
-.*:    84206800        prfd    pldl1keep, p2, \[x0,z0\.s,uxtw #3\]
-.*:    84206800        prfd    pldl1keep, p2, \[x0,z0\.s,uxtw #3\]
-.*:    84207c00        prfd    pldl1keep, p7, \[x0,z0\.s,uxtw #3\]
-.*:    84207c00        prfd    pldl1keep, p7, \[x0,z0\.s,uxtw #3\]
-.*:    84206060        prfd    pldl1keep, p0, \[x3,z0\.s,uxtw #3\]
-.*:    84206060        prfd    pldl1keep, p0, \[x3,z0\.s,uxtw #3\]
-.*:    842063e0        prfd    pldl1keep, p0, \[sp,z0\.s,uxtw #3\]
-.*:    842063e0        prfd    pldl1keep, p0, \[sp,z0\.s,uxtw #3\]
-.*:    84246000        prfd    pldl1keep, p0, \[x0,z4\.s,uxtw #3\]
-.*:    84246000        prfd    pldl1keep, p0, \[x0,z4\.s,uxtw #3\]
-.*:    843f6000        prfd    pldl1keep, p0, \[x0,z31\.s,uxtw #3\]
-.*:    843f6000        prfd    pldl1keep, p0, \[x0,z31\.s,uxtw #3\]
-.*:    84606000        prfd    pldl1keep, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606000        prfd    pldl1keep, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606001        prfd    pldl1strm, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606001        prfd    pldl1strm, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606002        prfd    pldl2keep, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606002        prfd    pldl2keep, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606003        prfd    pldl2strm, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606003        prfd    pldl2strm, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606004        prfd    pldl3keep, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606004        prfd    pldl3keep, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606005        prfd    pldl3strm, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606005        prfd    pldl3strm, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606006        prfd    #6, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606006        prfd    #6, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606007        prfd    #7, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606007        prfd    #7, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606008        prfd    pstl1keep, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606008        prfd    pstl1keep, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606009        prfd    pstl1strm, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606009        prfd    pstl1strm, p0, \[x0,z0\.s,sxtw #3\]
-.*:    8460600a        prfd    pstl2keep, p0, \[x0,z0\.s,sxtw #3\]
-.*:    8460600a        prfd    pstl2keep, p0, \[x0,z0\.s,sxtw #3\]
-.*:    8460600b        prfd    pstl2strm, p0, \[x0,z0\.s,sxtw #3\]
-.*:    8460600b        prfd    pstl2strm, p0, \[x0,z0\.s,sxtw #3\]
-.*:    8460600c        prfd    pstl3keep, p0, \[x0,z0\.s,sxtw #3\]
-.*:    8460600c        prfd    pstl3keep, p0, \[x0,z0\.s,sxtw #3\]
-.*:    8460600d        prfd    pstl3strm, p0, \[x0,z0\.s,sxtw #3\]
-.*:    8460600d        prfd    pstl3strm, p0, \[x0,z0\.s,sxtw #3\]
-.*:    8460600e        prfd    #14, p0, \[x0,z0\.s,sxtw #3\]
-.*:    8460600e        prfd    #14, p0, \[x0,z0\.s,sxtw #3\]
-.*:    8460600f        prfd    #15, p0, \[x0,z0\.s,sxtw #3\]
-.*:    8460600f        prfd    #15, p0, \[x0,z0\.s,sxtw #3\]
-.*:    84606800        prfd    pldl1keep, p2, \[x0,z0\.s,sxtw #3\]
-.*:    84606800        prfd    pldl1keep, p2, \[x0,z0\.s,sxtw #3\]
-.*:    84607c00        prfd    pldl1keep, p7, \[x0,z0\.s,sxtw #3\]
-.*:    84607c00        prfd    pldl1keep, p7, \[x0,z0\.s,sxtw #3\]
-.*:    84606060        prfd    pldl1keep, p0, \[x3,z0\.s,sxtw #3\]
-.*:    84606060        prfd    pldl1keep, p0, \[x3,z0\.s,sxtw #3\]
-.*:    846063e0        prfd    pldl1keep, p0, \[sp,z0\.s,sxtw #3\]
-.*:    846063e0        prfd    pldl1keep, p0, \[sp,z0\.s,sxtw #3\]
-.*:    84646000        prfd    pldl1keep, p0, \[x0,z4\.s,sxtw #3\]
-.*:    84646000        prfd    pldl1keep, p0, \[x0,z4\.s,sxtw #3\]
-.*:    847f6000        prfd    pldl1keep, p0, \[x0,z31\.s,sxtw #3\]
-.*:    847f6000        prfd    pldl1keep, p0, \[x0,z31\.s,sxtw #3\]
-.*:    8580c000        prfd    pldl1keep, p0, \[x0,x0,lsl #3\]
-.*:    8580c000        prfd    pldl1keep, p0, \[x0,x0,lsl #3\]
-.*:    8580c001        prfd    pldl1strm, p0, \[x0,x0,lsl #3\]
-.*:    8580c001        prfd    pldl1strm, p0, \[x0,x0,lsl #3\]
-.*:    8580c002        prfd    pldl2keep, p0, \[x0,x0,lsl #3\]
-.*:    8580c002        prfd    pldl2keep, p0, \[x0,x0,lsl #3\]
-.*:    8580c003        prfd    pldl2strm, p0, \[x0,x0,lsl #3\]
-.*:    8580c003        prfd    pldl2strm, p0, \[x0,x0,lsl #3\]
-.*:    8580c004        prfd    pldl3keep, p0, \[x0,x0,lsl #3\]
-.*:    8580c004        prfd    pldl3keep, p0, \[x0,x0,lsl #3\]
-.*:    8580c005        prfd    pldl3strm, p0, \[x0,x0,lsl #3\]
-.*:    8580c005        prfd    pldl3strm, p0, \[x0,x0,lsl #3\]
-.*:    8580c006        prfd    #6, p0, \[x0,x0,lsl #3\]
-.*:    8580c006        prfd    #6, p0, \[x0,x0,lsl #3\]
-.*:    8580c007        prfd    #7, p0, \[x0,x0,lsl #3\]
-.*:    8580c007        prfd    #7, p0, \[x0,x0,lsl #3\]
-.*:    8580c008        prfd    pstl1keep, p0, \[x0,x0,lsl #3\]
-.*:    8580c008        prfd    pstl1keep, p0, \[x0,x0,lsl #3\]
-.*:    8580c009        prfd    pstl1strm, p0, \[x0,x0,lsl #3\]
-.*:    8580c009        prfd    pstl1strm, p0, \[x0,x0,lsl #3\]
-.*:    8580c00a        prfd    pstl2keep, p0, \[x0,x0,lsl #3\]
-.*:    8580c00a        prfd    pstl2keep, p0, \[x0,x0,lsl #3\]
-.*:    8580c00b        prfd    pstl2strm, p0, \[x0,x0,lsl #3\]
-.*:    8580c00b        prfd    pstl2strm, p0, \[x0,x0,lsl #3\]
-.*:    8580c00c        prfd    pstl3keep, p0, \[x0,x0,lsl #3\]
-.*:    8580c00c        prfd    pstl3keep, p0, \[x0,x0,lsl #3\]
-.*:    8580c00d        prfd    pstl3strm, p0, \[x0,x0,lsl #3\]
-.*:    8580c00d        prfd    pstl3strm, p0, \[x0,x0,lsl #3\]
-.*:    8580c00e        prfd    #14, p0, \[x0,x0,lsl #3\]
-.*:    8580c00e        prfd    #14, p0, \[x0,x0,lsl #3\]
-.*:    8580c00f        prfd    #15, p0, \[x0,x0,lsl #3\]
-.*:    8580c00f        prfd    #15, p0, \[x0,x0,lsl #3\]
-.*:    8580c800        prfd    pldl1keep, p2, \[x0,x0,lsl #3\]
-.*:    8580c800        prfd    pldl1keep, p2, \[x0,x0,lsl #3\]
-.*:    8580dc00        prfd    pldl1keep, p7, \[x0,x0,lsl #3\]
-.*:    8580dc00        prfd    pldl1keep, p7, \[x0,x0,lsl #3\]
-.*:    8580c060        prfd    pldl1keep, p0, \[x3,x0,lsl #3\]
-.*:    8580c060        prfd    pldl1keep, p0, \[x3,x0,lsl #3\]
-.*:    8580c3e0        prfd    pldl1keep, p0, \[sp,x0,lsl #3\]
-.*:    8580c3e0        prfd    pldl1keep, p0, \[sp,x0,lsl #3\]
-.*:    8584c000        prfd    pldl1keep, p0, \[x0,x4,lsl #3\]
-.*:    8584c000        prfd    pldl1keep, p0, \[x0,x4,lsl #3\]
-.*:    859ec000        prfd    pldl1keep, p0, \[x0,x30,lsl #3\]
-.*:    859ec000        prfd    pldl1keep, p0, \[x0,x30,lsl #3\]
-.*:    c4206000        prfd    pldl1keep, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206000        prfd    pldl1keep, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206001        prfd    pldl1strm, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206001        prfd    pldl1strm, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206002        prfd    pldl2keep, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206002        prfd    pldl2keep, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206003        prfd    pldl2strm, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206003        prfd    pldl2strm, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206004        prfd    pldl3keep, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206004        prfd    pldl3keep, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206005        prfd    pldl3strm, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206005        prfd    pldl3strm, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206006        prfd    #6, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206006        prfd    #6, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206007        prfd    #7, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206007        prfd    #7, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206008        prfd    pstl1keep, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206008        prfd    pstl1keep, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206009        prfd    pstl1strm, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206009        prfd    pstl1strm, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c420600a        prfd    pstl2keep, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c420600a        prfd    pstl2keep, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c420600b        prfd    pstl2strm, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c420600b        prfd    pstl2strm, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c420600c        prfd    pstl3keep, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c420600c        prfd    pstl3keep, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c420600d        prfd    pstl3strm, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c420600d        prfd    pstl3strm, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c420600e        prfd    #14, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c420600e        prfd    #14, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c420600f        prfd    #15, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c420600f        prfd    #15, p0, \[x0,z0\.d,uxtw #3\]
-.*:    c4206800        prfd    pldl1keep, p2, \[x0,z0\.d,uxtw #3\]
-.*:    c4206800        prfd    pldl1keep, p2, \[x0,z0\.d,uxtw #3\]
-.*:    c4207c00        prfd    pldl1keep, p7, \[x0,z0\.d,uxtw #3\]
-.*:    c4207c00        prfd    pldl1keep, p7, \[x0,z0\.d,uxtw #3\]
-.*:    c4206060        prfd    pldl1keep, p0, \[x3,z0\.d,uxtw #3\]
-.*:    c4206060        prfd    pldl1keep, p0, \[x3,z0\.d,uxtw #3\]
-.*:    c42063e0        prfd    pldl1keep, p0, \[sp,z0\.d,uxtw #3\]
-.*:    c42063e0        prfd    pldl1keep, p0, \[sp,z0\.d,uxtw #3\]
-.*:    c4246000        prfd    pldl1keep, p0, \[x0,z4\.d,uxtw #3\]
-.*:    c4246000        prfd    pldl1keep, p0, \[x0,z4\.d,uxtw #3\]
-.*:    c43f6000        prfd    pldl1keep, p0, \[x0,z31\.d,uxtw #3\]
-.*:    c43f6000        prfd    pldl1keep, p0, \[x0,z31\.d,uxtw #3\]
-.*:    c4606000        prfd    pldl1keep, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606000        prfd    pldl1keep, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606001        prfd    pldl1strm, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606001        prfd    pldl1strm, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606002        prfd    pldl2keep, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606002        prfd    pldl2keep, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606003        prfd    pldl2strm, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606003        prfd    pldl2strm, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606004        prfd    pldl3keep, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606004        prfd    pldl3keep, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606005        prfd    pldl3strm, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606005        prfd    pldl3strm, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606006        prfd    #6, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606006        prfd    #6, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606007        prfd    #7, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606007        prfd    #7, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606008        prfd    pstl1keep, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606008        prfd    pstl1keep, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606009        prfd    pstl1strm, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606009        prfd    pstl1strm, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c460600a        prfd    pstl2keep, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c460600a        prfd    pstl2keep, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c460600b        prfd    pstl2strm, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c460600b        prfd    pstl2strm, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c460600c        prfd    pstl3keep, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c460600c        prfd    pstl3keep, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c460600d        prfd    pstl3strm, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c460600d        prfd    pstl3strm, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c460600e        prfd    #14, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c460600e        prfd    #14, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c460600f        prfd    #15, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c460600f        prfd    #15, p0, \[x0,z0\.d,sxtw #3\]
-.*:    c4606800        prfd    pldl1keep, p2, \[x0,z0\.d,sxtw #3\]
-.*:    c4606800        prfd    pldl1keep, p2, \[x0,z0\.d,sxtw #3\]
-.*:    c4607c00        prfd    pldl1keep, p7, \[x0,z0\.d,sxtw #3\]
-.*:    c4607c00        prfd    pldl1keep, p7, \[x0,z0\.d,sxtw #3\]
-.*:    c4606060        prfd    pldl1keep, p0, \[x3,z0\.d,sxtw #3\]
-.*:    c4606060        prfd    pldl1keep, p0, \[x3,z0\.d,sxtw #3\]
-.*:    c46063e0        prfd    pldl1keep, p0, \[sp,z0\.d,sxtw #3\]
-.*:    c46063e0        prfd    pldl1keep, p0, \[sp,z0\.d,sxtw #3\]
-.*:    c4646000        prfd    pldl1keep, p0, \[x0,z4\.d,sxtw #3\]
-.*:    c4646000        prfd    pldl1keep, p0, \[x0,z4\.d,sxtw #3\]
-.*:    c47f6000        prfd    pldl1keep, p0, \[x0,z31\.d,sxtw #3\]
-.*:    c47f6000        prfd    pldl1keep, p0, \[x0,z31\.d,sxtw #3\]
-.*:    c460e000        prfd    pldl1keep, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e000        prfd    pldl1keep, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e001        prfd    pldl1strm, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e001        prfd    pldl1strm, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e002        prfd    pldl2keep, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e002        prfd    pldl2keep, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e003        prfd    pldl2strm, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e003        prfd    pldl2strm, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e004        prfd    pldl3keep, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e004        prfd    pldl3keep, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e005        prfd    pldl3strm, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e005        prfd    pldl3strm, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e006        prfd    #6, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e006        prfd    #6, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e007        prfd    #7, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e007        prfd    #7, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e008        prfd    pstl1keep, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e008        prfd    pstl1keep, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e009        prfd    pstl1strm, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e009        prfd    pstl1strm, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e00a        prfd    pstl2keep, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e00a        prfd    pstl2keep, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e00b        prfd    pstl2strm, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e00b        prfd    pstl2strm, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e00c        prfd    pstl3keep, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e00c        prfd    pstl3keep, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e00d        prfd    pstl3strm, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e00d        prfd    pstl3strm, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e00e        prfd    #14, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e00e        prfd    #14, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e00f        prfd    #15, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e00f        prfd    #15, p0, \[x0,z0\.d,lsl #3\]
-.*:    c460e800        prfd    pldl1keep, p2, \[x0,z0\.d,lsl #3\]
-.*:    c460e800        prfd    pldl1keep, p2, \[x0,z0\.d,lsl #3\]
-.*:    c460fc00        prfd    pldl1keep, p7, \[x0,z0\.d,lsl #3\]
-.*:    c460fc00        prfd    pldl1keep, p7, \[x0,z0\.d,lsl #3\]
-.*:    c460e060        prfd    pldl1keep, p0, \[x3,z0\.d,lsl #3\]
-.*:    c460e060        prfd    pldl1keep, p0, \[x3,z0\.d,lsl #3\]
-.*:    c460e3e0        prfd    pldl1keep, p0, \[sp,z0\.d,lsl #3\]
-.*:    c460e3e0        prfd    pldl1keep, p0, \[sp,z0\.d,lsl #3\]
-.*:    c464e000        prfd    pldl1keep, p0, \[x0,z4\.d,lsl #3\]
-.*:    c464e000        prfd    pldl1keep, p0, \[x0,z4\.d,lsl #3\]
-.*:    c47fe000        prfd    pldl1keep, p0, \[x0,z31\.d,lsl #3\]
-.*:    c47fe000        prfd    pldl1keep, p0, \[x0,z31\.d,lsl #3\]
+.*:    c40fe000        prfb    pldl1keep, p0, \[z0\.d, #15\]
+.*:    c40fe000        prfb    pldl1keep, p0, \[z0\.d, #15\]
+.*:    c410e000        prfb    pldl1keep, p0, \[z0\.d, #16\]
+.*:    c410e000        prfb    pldl1keep, p0, \[z0\.d, #16\]
+.*:    c411e000        prfb    pldl1keep, p0, \[z0\.d, #17\]
+.*:    c411e000        prfb    pldl1keep, p0, \[z0\.d, #17\]
+.*:    c41fe000        prfb    pldl1keep, p0, \[z0\.d, #31\]
+.*:    c41fe000        prfb    pldl1keep, p0, \[z0\.d, #31\]
+.*:    84206000        prfd    pldl1keep, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206000        prfd    pldl1keep, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206001        prfd    pldl1strm, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206001        prfd    pldl1strm, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206002        prfd    pldl2keep, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206002        prfd    pldl2keep, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206003        prfd    pldl2strm, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206003        prfd    pldl2strm, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206004        prfd    pldl3keep, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206004        prfd    pldl3keep, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206005        prfd    pldl3strm, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206005        prfd    pldl3strm, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206006        prfd    #6, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206006        prfd    #6, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206007        prfd    #7, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206007        prfd    #7, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206008        prfd    pstl1keep, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206008        prfd    pstl1keep, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206009        prfd    pstl1strm, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206009        prfd    pstl1strm, p0, \[x0, z0\.s, uxtw #3\]
+.*:    8420600a        prfd    pstl2keep, p0, \[x0, z0\.s, uxtw #3\]
+.*:    8420600a        prfd    pstl2keep, p0, \[x0, z0\.s, uxtw #3\]
+.*:    8420600b        prfd    pstl2strm, p0, \[x0, z0\.s, uxtw #3\]
+.*:    8420600b        prfd    pstl2strm, p0, \[x0, z0\.s, uxtw #3\]
+.*:    8420600c        prfd    pstl3keep, p0, \[x0, z0\.s, uxtw #3\]
+.*:    8420600c        prfd    pstl3keep, p0, \[x0, z0\.s, uxtw #3\]
+.*:    8420600d        prfd    pstl3strm, p0, \[x0, z0\.s, uxtw #3\]
+.*:    8420600d        prfd    pstl3strm, p0, \[x0, z0\.s, uxtw #3\]
+.*:    8420600e        prfd    #14, p0, \[x0, z0\.s, uxtw #3\]
+.*:    8420600e        prfd    #14, p0, \[x0, z0\.s, uxtw #3\]
+.*:    8420600f        prfd    #15, p0, \[x0, z0\.s, uxtw #3\]
+.*:    8420600f        prfd    #15, p0, \[x0, z0\.s, uxtw #3\]
+.*:    84206800        prfd    pldl1keep, p2, \[x0, z0\.s, uxtw #3\]
+.*:    84206800        prfd    pldl1keep, p2, \[x0, z0\.s, uxtw #3\]
+.*:    84207c00        prfd    pldl1keep, p7, \[x0, z0\.s, uxtw #3\]
+.*:    84207c00        prfd    pldl1keep, p7, \[x0, z0\.s, uxtw #3\]
+.*:    84206060        prfd    pldl1keep, p0, \[x3, z0\.s, uxtw #3\]
+.*:    84206060        prfd    pldl1keep, p0, \[x3, z0\.s, uxtw #3\]
+.*:    842063e0        prfd    pldl1keep, p0, \[sp, z0\.s, uxtw #3\]
+.*:    842063e0        prfd    pldl1keep, p0, \[sp, z0\.s, uxtw #3\]
+.*:    84246000        prfd    pldl1keep, p0, \[x0, z4\.s, uxtw #3\]
+.*:    84246000        prfd    pldl1keep, p0, \[x0, z4\.s, uxtw #3\]
+.*:    843f6000        prfd    pldl1keep, p0, \[x0, z31\.s, uxtw #3\]
+.*:    843f6000        prfd    pldl1keep, p0, \[x0, z31\.s, uxtw #3\]
+.*:    84606000        prfd    pldl1keep, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606000        prfd    pldl1keep, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606001        prfd    pldl1strm, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606001        prfd    pldl1strm, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606002        prfd    pldl2keep, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606002        prfd    pldl2keep, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606003        prfd    pldl2strm, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606003        prfd    pldl2strm, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606004        prfd    pldl3keep, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606004        prfd    pldl3keep, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606005        prfd    pldl3strm, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606005        prfd    pldl3strm, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606006        prfd    #6, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606006        prfd    #6, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606007        prfd    #7, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606007        prfd    #7, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606008        prfd    pstl1keep, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606008        prfd    pstl1keep, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606009        prfd    pstl1strm, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606009        prfd    pstl1strm, p0, \[x0, z0\.s, sxtw #3\]
+.*:    8460600a        prfd    pstl2keep, p0, \[x0, z0\.s, sxtw #3\]
+.*:    8460600a        prfd    pstl2keep, p0, \[x0, z0\.s, sxtw #3\]
+.*:    8460600b        prfd    pstl2strm, p0, \[x0, z0\.s, sxtw #3\]
+.*:    8460600b        prfd    pstl2strm, p0, \[x0, z0\.s, sxtw #3\]
+.*:    8460600c        prfd    pstl3keep, p0, \[x0, z0\.s, sxtw #3\]
+.*:    8460600c        prfd    pstl3keep, p0, \[x0, z0\.s, sxtw #3\]
+.*:    8460600d        prfd    pstl3strm, p0, \[x0, z0\.s, sxtw #3\]
+.*:    8460600d        prfd    pstl3strm, p0, \[x0, z0\.s, sxtw #3\]
+.*:    8460600e        prfd    #14, p0, \[x0, z0\.s, sxtw #3\]
+.*:    8460600e        prfd    #14, p0, \[x0, z0\.s, sxtw #3\]
+.*:    8460600f        prfd    #15, p0, \[x0, z0\.s, sxtw #3\]
+.*:    8460600f        prfd    #15, p0, \[x0, z0\.s, sxtw #3\]
+.*:    84606800        prfd    pldl1keep, p2, \[x0, z0\.s, sxtw #3\]
+.*:    84606800        prfd    pldl1keep, p2, \[x0, z0\.s, sxtw #3\]
+.*:    84607c00        prfd    pldl1keep, p7, \[x0, z0\.s, sxtw #3\]
+.*:    84607c00        prfd    pldl1keep, p7, \[x0, z0\.s, sxtw #3\]
+.*:    84606060        prfd    pldl1keep, p0, \[x3, z0\.s, sxtw #3\]
+.*:    84606060        prfd    pldl1keep, p0, \[x3, z0\.s, sxtw #3\]
+.*:    846063e0        prfd    pldl1keep, p0, \[sp, z0\.s, sxtw #3\]
+.*:    846063e0        prfd    pldl1keep, p0, \[sp, z0\.s, sxtw #3\]
+.*:    84646000        prfd    pldl1keep, p0, \[x0, z4\.s, sxtw #3\]
+.*:    84646000        prfd    pldl1keep, p0, \[x0, z4\.s, sxtw #3\]
+.*:    847f6000        prfd    pldl1keep, p0, \[x0, z31\.s, sxtw #3\]
+.*:    847f6000        prfd    pldl1keep, p0, \[x0, z31\.s, sxtw #3\]
+.*:    8580c000        prfd    pldl1keep, p0, \[x0, x0, lsl #3\]
+.*:    8580c000        prfd    pldl1keep, p0, \[x0, x0, lsl #3\]
+.*:    8580c001        prfd    pldl1strm, p0, \[x0, x0, lsl #3\]
+.*:    8580c001        prfd    pldl1strm, p0, \[x0, x0, lsl #3\]
+.*:    8580c002        prfd    pldl2keep, p0, \[x0, x0, lsl #3\]
+.*:    8580c002        prfd    pldl2keep, p0, \[x0, x0, lsl #3\]
+.*:    8580c003        prfd    pldl2strm, p0, \[x0, x0, lsl #3\]
+.*:    8580c003        prfd    pldl2strm, p0, \[x0, x0, lsl #3\]
+.*:    8580c004        prfd    pldl3keep, p0, \[x0, x0, lsl #3\]
+.*:    8580c004        prfd    pldl3keep, p0, \[x0, x0, lsl #3\]
+.*:    8580c005        prfd    pldl3strm, p0, \[x0, x0, lsl #3\]
+.*:    8580c005        prfd    pldl3strm, p0, \[x0, x0, lsl #3\]
+.*:    8580c006        prfd    #6, p0, \[x0, x0, lsl #3\]
+.*:    8580c006        prfd    #6, p0, \[x0, x0, lsl #3\]
+.*:    8580c007        prfd    #7, p0, \[x0, x0, lsl #3\]
+.*:    8580c007        prfd    #7, p0, \[x0, x0, lsl #3\]
+.*:    8580c008        prfd    pstl1keep, p0, \[x0, x0, lsl #3\]
+.*:    8580c008        prfd    pstl1keep, p0, \[x0, x0, lsl #3\]
+.*:    8580c009        prfd    pstl1strm, p0, \[x0, x0, lsl #3\]
+.*:    8580c009        prfd    pstl1strm, p0, \[x0, x0, lsl #3\]
+.*:    8580c00a        prfd    pstl2keep, p0, \[x0, x0, lsl #3\]
+.*:    8580c00a        prfd    pstl2keep, p0, \[x0, x0, lsl #3\]
+.*:    8580c00b        prfd    pstl2strm, p0, \[x0, x0, lsl #3\]
+.*:    8580c00b        prfd    pstl2strm, p0, \[x0, x0, lsl #3\]
+.*:    8580c00c        prfd    pstl3keep, p0, \[x0, x0, lsl #3\]
+.*:    8580c00c        prfd    pstl3keep, p0, \[x0, x0, lsl #3\]
+.*:    8580c00d        prfd    pstl3strm, p0, \[x0, x0, lsl #3\]
+.*:    8580c00d        prfd    pstl3strm, p0, \[x0, x0, lsl #3\]
+.*:    8580c00e        prfd    #14, p0, \[x0, x0, lsl #3\]
+.*:    8580c00e        prfd    #14, p0, \[x0, x0, lsl #3\]
+.*:    8580c00f        prfd    #15, p0, \[x0, x0, lsl #3\]
+.*:    8580c00f        prfd    #15, p0, \[x0, x0, lsl #3\]
+.*:    8580c800        prfd    pldl1keep, p2, \[x0, x0, lsl #3\]
+.*:    8580c800        prfd    pldl1keep, p2, \[x0, x0, lsl #3\]
+.*:    8580dc00        prfd    pldl1keep, p7, \[x0, x0, lsl #3\]
+.*:    8580dc00        prfd    pldl1keep, p7, \[x0, x0, lsl #3\]
+.*:    8580c060        prfd    pldl1keep, p0, \[x3, x0, lsl #3\]
+.*:    8580c060        prfd    pldl1keep, p0, \[x3, x0, lsl #3\]
+.*:    8580c3e0        prfd    pldl1keep, p0, \[sp, x0, lsl #3\]
+.*:    8580c3e0        prfd    pldl1keep, p0, \[sp, x0, lsl #3\]
+.*:    8584c000        prfd    pldl1keep, p0, \[x0, x4, lsl #3\]
+.*:    8584c000        prfd    pldl1keep, p0, \[x0, x4, lsl #3\]
+.*:    859ec000        prfd    pldl1keep, p0, \[x0, x30, lsl #3\]
+.*:    859ec000        prfd    pldl1keep, p0, \[x0, x30, lsl #3\]
+.*:    c4206000        prfd    pldl1keep, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206000        prfd    pldl1keep, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206001        prfd    pldl1strm, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206001        prfd    pldl1strm, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206002        prfd    pldl2keep, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206002        prfd    pldl2keep, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206003        prfd    pldl2strm, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206003        prfd    pldl2strm, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206004        prfd    pldl3keep, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206004        prfd    pldl3keep, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206005        prfd    pldl3strm, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206005        prfd    pldl3strm, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206006        prfd    #6, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206006        prfd    #6, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206007        prfd    #7, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206007        prfd    #7, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206008        prfd    pstl1keep, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206008        prfd    pstl1keep, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206009        prfd    pstl1strm, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206009        prfd    pstl1strm, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c420600a        prfd    pstl2keep, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c420600a        prfd    pstl2keep, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c420600b        prfd    pstl2strm, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c420600b        prfd    pstl2strm, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c420600c        prfd    pstl3keep, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c420600c        prfd    pstl3keep, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c420600d        prfd    pstl3strm, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c420600d        prfd    pstl3strm, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c420600e        prfd    #14, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c420600e        prfd    #14, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c420600f        prfd    #15, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c420600f        prfd    #15, p0, \[x0, z0\.d, uxtw #3\]
+.*:    c4206800        prfd    pldl1keep, p2, \[x0, z0\.d, uxtw #3\]
+.*:    c4206800        prfd    pldl1keep, p2, \[x0, z0\.d, uxtw #3\]
+.*:    c4207c00        prfd    pldl1keep, p7, \[x0, z0\.d, uxtw #3\]
+.*:    c4207c00        prfd    pldl1keep, p7, \[x0, z0\.d, uxtw #3\]
+.*:    c4206060        prfd    pldl1keep, p0, \[x3, z0\.d, uxtw #3\]
+.*:    c4206060        prfd    pldl1keep, p0, \[x3, z0\.d, uxtw #3\]
+.*:    c42063e0        prfd    pldl1keep, p0, \[sp, z0\.d, uxtw #3\]
+.*:    c42063e0        prfd    pldl1keep, p0, \[sp, z0\.d, uxtw #3\]
+.*:    c4246000        prfd    pldl1keep, p0, \[x0, z4\.d, uxtw #3\]
+.*:    c4246000        prfd    pldl1keep, p0, \[x0, z4\.d, uxtw #3\]
+.*:    c43f6000        prfd    pldl1keep, p0, \[x0, z31\.d, uxtw #3\]
+.*:    c43f6000        prfd    pldl1keep, p0, \[x0, z31\.d, uxtw #3\]
+.*:    c4606000        prfd    pldl1keep, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606000        prfd    pldl1keep, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606001        prfd    pldl1strm, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606001        prfd    pldl1strm, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606002        prfd    pldl2keep, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606002        prfd    pldl2keep, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606003        prfd    pldl2strm, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606003        prfd    pldl2strm, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606004        prfd    pldl3keep, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606004        prfd    pldl3keep, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606005        prfd    pldl3strm, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606005        prfd    pldl3strm, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606006        prfd    #6, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606006        prfd    #6, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606007        prfd    #7, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606007        prfd    #7, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606008        prfd    pstl1keep, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606008        prfd    pstl1keep, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606009        prfd    pstl1strm, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606009        prfd    pstl1strm, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c460600a        prfd    pstl2keep, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c460600a        prfd    pstl2keep, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c460600b        prfd    pstl2strm, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c460600b        prfd    pstl2strm, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c460600c        prfd    pstl3keep, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c460600c        prfd    pstl3keep, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c460600d        prfd    pstl3strm, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c460600d        prfd    pstl3strm, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c460600e        prfd    #14, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c460600e        prfd    #14, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c460600f        prfd    #15, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c460600f        prfd    #15, p0, \[x0, z0\.d, sxtw #3\]
+.*:    c4606800        prfd    pldl1keep, p2, \[x0, z0\.d, sxtw #3\]
+.*:    c4606800        prfd    pldl1keep, p2, \[x0, z0\.d, sxtw #3\]
+.*:    c4607c00        prfd    pldl1keep, p7, \[x0, z0\.d, sxtw #3\]
+.*:    c4607c00        prfd    pldl1keep, p7, \[x0, z0\.d, sxtw #3\]
+.*:    c4606060        prfd    pldl1keep, p0, \[x3, z0\.d, sxtw #3\]
+.*:    c4606060        prfd    pldl1keep, p0, \[x3, z0\.d, sxtw #3\]
+.*:    c46063e0        prfd    pldl1keep, p0, \[sp, z0\.d, sxtw #3\]
+.*:    c46063e0        prfd    pldl1keep, p0, \[sp, z0\.d, sxtw #3\]
+.*:    c4646000        prfd    pldl1keep, p0, \[x0, z4\.d, sxtw #3\]
+.*:    c4646000        prfd    pldl1keep, p0, \[x0, z4\.d, sxtw #3\]
+.*:    c47f6000        prfd    pldl1keep, p0, \[x0, z31\.d, sxtw #3\]
+.*:    c47f6000        prfd    pldl1keep, p0, \[x0, z31\.d, sxtw #3\]
+.*:    c460e000        prfd    pldl1keep, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e000        prfd    pldl1keep, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e001        prfd    pldl1strm, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e001        prfd    pldl1strm, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e002        prfd    pldl2keep, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e002        prfd    pldl2keep, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e003        prfd    pldl2strm, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e003        prfd    pldl2strm, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e004        prfd    pldl3keep, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e004        prfd    pldl3keep, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e005        prfd    pldl3strm, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e005        prfd    pldl3strm, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e006        prfd    #6, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e006        prfd    #6, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e007        prfd    #7, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e007        prfd    #7, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e008        prfd    pstl1keep, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e008        prfd    pstl1keep, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e009        prfd    pstl1strm, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e009        prfd    pstl1strm, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e00a        prfd    pstl2keep, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e00a        prfd    pstl2keep, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e00b        prfd    pstl2strm, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e00b        prfd    pstl2strm, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e00c        prfd    pstl3keep, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e00c        prfd    pstl3keep, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e00d        prfd    pstl3strm, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e00d        prfd    pstl3strm, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e00e        prfd    #14, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e00e        prfd    #14, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e00f        prfd    #15, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e00f        prfd    #15, p0, \[x0, z0\.d, lsl #3\]
+.*:    c460e800        prfd    pldl1keep, p2, \[x0, z0\.d, lsl #3\]
+.*:    c460e800        prfd    pldl1keep, p2, \[x0, z0\.d, lsl #3\]
+.*:    c460fc00        prfd    pldl1keep, p7, \[x0, z0\.d, lsl #3\]
+.*:    c460fc00        prfd    pldl1keep, p7, \[x0, z0\.d, lsl #3\]
+.*:    c460e060        prfd    pldl1keep, p0, \[x3, z0\.d, lsl #3\]
+.*:    c460e060        prfd    pldl1keep, p0, \[x3, z0\.d, lsl #3\]
+.*:    c460e3e0        prfd    pldl1keep, p0, \[sp, z0\.d, lsl #3\]
+.*:    c460e3e0        prfd    pldl1keep, p0, \[sp, z0\.d, lsl #3\]
+.*:    c464e000        prfd    pldl1keep, p0, \[x0, z4\.d, lsl #3\]
+.*:    c464e000        prfd    pldl1keep, p0, \[x0, z4\.d, lsl #3\]
+.*:    c47fe000        prfd    pldl1keep, p0, \[x0, z31\.d, lsl #3\]
+.*:    c47fe000        prfd    pldl1keep, p0, \[x0, z31\.d, lsl #3\]
 .*:    8580e000        prfd    pldl1keep, p0, \[z0\.s\]
 .*:    8580e000        prfd    pldl1keep, p0, \[z0\.s\]
 .*:    8580e000        prfd    pldl1keep, p0, \[z0\.s\]
@@ -22930,14 +22930,14 @@ Disassembly of section .*:
 .*:    8580e3e0        prfd    pldl1keep, p0, \[z31\.s\]
 .*:    8580e3e0        prfd    pldl1keep, p0, \[z31\.s\]
 .*:    8580e3e0        prfd    pldl1keep, p0, \[z31\.s\]
-.*:    858fe000        prfd    pldl1keep, p0, \[z0\.s,#120\]
-.*:    858fe000        prfd    pldl1keep, p0, \[z0\.s,#120\]
-.*:    8590e000        prfd    pldl1keep, p0, \[z0\.s,#128\]
-.*:    8590e000        prfd    pldl1keep, p0, \[z0\.s,#128\]
-.*:    8591e000        prfd    pldl1keep, p0, \[z0\.s,#136\]
-.*:    8591e000        prfd    pldl1keep, p0, \[z0\.s,#136\]
-.*:    859fe000        prfd    pldl1keep, p0, \[z0\.s,#248\]
-.*:    859fe000        prfd    pldl1keep, p0, \[z0\.s,#248\]
+.*:    858fe000        prfd    pldl1keep, p0, \[z0\.s, #120\]
+.*:    858fe000        prfd    pldl1keep, p0, \[z0\.s, #120\]
+.*:    8590e000        prfd    pldl1keep, p0, \[z0\.s, #128\]
+.*:    8590e000        prfd    pldl1keep, p0, \[z0\.s, #128\]
+.*:    8591e000        prfd    pldl1keep, p0, \[z0\.s, #136\]
+.*:    8591e000        prfd    pldl1keep, p0, \[z0\.s, #136\]
+.*:    859fe000        prfd    pldl1keep, p0, \[z0\.s, #248\]
+.*:    859fe000        prfd    pldl1keep, p0, \[z0\.s, #248\]
 .*:    85c06000        prfd    pldl1keep, p0, \[x0\]
 .*:    85c06000        prfd    pldl1keep, p0, \[x0\]
 .*:    85c06000        prfd    pldl1keep, p0, \[x0\]
@@ -23018,14 +23018,14 @@ Disassembly of section .*:
 .*:    85c063e0        prfd    pldl1keep, p0, \[sp\]
 .*:    85c063e0        prfd    pldl1keep, p0, \[sp\]
 .*:    85c063e0        prfd    pldl1keep, p0, \[sp\]
-.*:    85df6000        prfd    pldl1keep, p0, \[x0,#31,mul vl\]
-.*:    85df6000        prfd    pldl1keep, p0, \[x0,#31,mul vl\]
-.*:    85e06000        prfd    pldl1keep, p0, \[x0,#-32,mul vl\]
-.*:    85e06000        prfd    pldl1keep, p0, \[x0,#-32,mul vl\]
-.*:    85e16000        prfd    pldl1keep, p0, \[x0,#-31,mul vl\]
-.*:    85e16000        prfd    pldl1keep, p0, \[x0,#-31,mul vl\]
-.*:    85ff6000        prfd    pldl1keep, p0, \[x0,#-1,mul vl\]
-.*:    85ff6000        prfd    pldl1keep, p0, \[x0,#-1,mul vl\]
+.*:    85df6000        prfd    pldl1keep, p0, \[x0, #31, mul vl\]
+.*:    85df6000        prfd    pldl1keep, p0, \[x0, #31, mul vl\]
+.*:    85e06000        prfd    pldl1keep, p0, \[x0, #-32, mul vl\]
+.*:    85e06000        prfd    pldl1keep, p0, \[x0, #-32, mul vl\]
+.*:    85e16000        prfd    pldl1keep, p0, \[x0, #-31, mul vl\]
+.*:    85e16000        prfd    pldl1keep, p0, \[x0, #-31, mul vl\]
+.*:    85ff6000        prfd    pldl1keep, p0, \[x0, #-1, mul vl\]
+.*:    85ff6000        prfd    pldl1keep, p0, \[x0, #-1, mul vl\]
 .*:    c580e000        prfd    pldl1keep, p0, \[z0\.d\]
 .*:    c580e000        prfd    pldl1keep, p0, \[z0\.d\]
 .*:    c580e000        prfd    pldl1keep, p0, \[z0\.d\]
@@ -23086,278 +23086,278 @@ Disassembly of section .*:
 .*:    c580e3e0        prfd    pldl1keep, p0, \[z31\.d\]
 .*:    c580e3e0        prfd    pldl1keep, p0, \[z31\.d\]
 .*:    c580e3e0        prfd    pldl1keep, p0, \[z31\.d\]
-.*:    c58fe000        prfd    pldl1keep, p0, \[z0\.d,#120\]
-.*:    c58fe000        prfd    pldl1keep, p0, \[z0\.d,#120\]
-.*:    c590e000        prfd    pldl1keep, p0, \[z0\.d,#128\]
-.*:    c590e000        prfd    pldl1keep, p0, \[z0\.d,#128\]
-.*:    c591e000        prfd    pldl1keep, p0, \[z0\.d,#136\]
-.*:    c591e000        prfd    pldl1keep, p0, \[z0\.d,#136\]
-.*:    c59fe000        prfd    pldl1keep, p0, \[z0\.d,#248\]
-.*:    c59fe000        prfd    pldl1keep, p0, \[z0\.d,#248\]
-.*:    84202000        prfh    pldl1keep, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202000        prfh    pldl1keep, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202001        prfh    pldl1strm, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202001        prfh    pldl1strm, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202002        prfh    pldl2keep, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202002        prfh    pldl2keep, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202003        prfh    pldl2strm, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202003        prfh    pldl2strm, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202004        prfh    pldl3keep, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202004        prfh    pldl3keep, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202005        prfh    pldl3strm, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202005        prfh    pldl3strm, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202006        prfh    #6, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202006        prfh    #6, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202007        prfh    #7, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202007        prfh    #7, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202008        prfh    pstl1keep, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202008        prfh    pstl1keep, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202009        prfh    pstl1strm, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202009        prfh    pstl1strm, p0, \[x0,z0\.s,uxtw #1\]
-.*:    8420200a        prfh    pstl2keep, p0, \[x0,z0\.s,uxtw #1\]
-.*:    8420200a        prfh    pstl2keep, p0, \[x0,z0\.s,uxtw #1\]
-.*:    8420200b        prfh    pstl2strm, p0, \[x0,z0\.s,uxtw #1\]
-.*:    8420200b        prfh    pstl2strm, p0, \[x0,z0\.s,uxtw #1\]
-.*:    8420200c        prfh    pstl3keep, p0, \[x0,z0\.s,uxtw #1\]
-.*:    8420200c        prfh    pstl3keep, p0, \[x0,z0\.s,uxtw #1\]
-.*:    8420200d        prfh    pstl3strm, p0, \[x0,z0\.s,uxtw #1\]
-.*:    8420200d        prfh    pstl3strm, p0, \[x0,z0\.s,uxtw #1\]
-.*:    8420200e        prfh    #14, p0, \[x0,z0\.s,uxtw #1\]
-.*:    8420200e        prfh    #14, p0, \[x0,z0\.s,uxtw #1\]
-.*:    8420200f        prfh    #15, p0, \[x0,z0\.s,uxtw #1\]
-.*:    8420200f        prfh    #15, p0, \[x0,z0\.s,uxtw #1\]
-.*:    84202800        prfh    pldl1keep, p2, \[x0,z0\.s,uxtw #1\]
-.*:    84202800        prfh    pldl1keep, p2, \[x0,z0\.s,uxtw #1\]
-.*:    84203c00        prfh    pldl1keep, p7, \[x0,z0\.s,uxtw #1\]
-.*:    84203c00        prfh    pldl1keep, p7, \[x0,z0\.s,uxtw #1\]
-.*:    84202060        prfh    pldl1keep, p0, \[x3,z0\.s,uxtw #1\]
-.*:    84202060        prfh    pldl1keep, p0, \[x3,z0\.s,uxtw #1\]
-.*:    842023e0        prfh    pldl1keep, p0, \[sp,z0\.s,uxtw #1\]
-.*:    842023e0        prfh    pldl1keep, p0, \[sp,z0\.s,uxtw #1\]
-.*:    84242000        prfh    pldl1keep, p0, \[x0,z4\.s,uxtw #1\]
-.*:    84242000        prfh    pldl1keep, p0, \[x0,z4\.s,uxtw #1\]
-.*:    843f2000        prfh    pldl1keep, p0, \[x0,z31\.s,uxtw #1\]
-.*:    843f2000        prfh    pldl1keep, p0, \[x0,z31\.s,uxtw #1\]
-.*:    84602000        prfh    pldl1keep, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602000        prfh    pldl1keep, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602001        prfh    pldl1strm, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602001        prfh    pldl1strm, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602002        prfh    pldl2keep, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602002        prfh    pldl2keep, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602003        prfh    pldl2strm, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602003        prfh    pldl2strm, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602004        prfh    pldl3keep, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602004        prfh    pldl3keep, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602005        prfh    pldl3strm, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602005        prfh    pldl3strm, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602006        prfh    #6, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602006        prfh    #6, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602007        prfh    #7, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602007        prfh    #7, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602008        prfh    pstl1keep, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602008        prfh    pstl1keep, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602009        prfh    pstl1strm, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602009        prfh    pstl1strm, p0, \[x0,z0\.s,sxtw #1\]
-.*:    8460200a        prfh    pstl2keep, p0, \[x0,z0\.s,sxtw #1\]
-.*:    8460200a        prfh    pstl2keep, p0, \[x0,z0\.s,sxtw #1\]
-.*:    8460200b        prfh    pstl2strm, p0, \[x0,z0\.s,sxtw #1\]
-.*:    8460200b        prfh    pstl2strm, p0, \[x0,z0\.s,sxtw #1\]
-.*:    8460200c        prfh    pstl3keep, p0, \[x0,z0\.s,sxtw #1\]
-.*:    8460200c        prfh    pstl3keep, p0, \[x0,z0\.s,sxtw #1\]
-.*:    8460200d        prfh    pstl3strm, p0, \[x0,z0\.s,sxtw #1\]
-.*:    8460200d        prfh    pstl3strm, p0, \[x0,z0\.s,sxtw #1\]
-.*:    8460200e        prfh    #14, p0, \[x0,z0\.s,sxtw #1\]
-.*:    8460200e        prfh    #14, p0, \[x0,z0\.s,sxtw #1\]
-.*:    8460200f        prfh    #15, p0, \[x0,z0\.s,sxtw #1\]
-.*:    8460200f        prfh    #15, p0, \[x0,z0\.s,sxtw #1\]
-.*:    84602800        prfh    pldl1keep, p2, \[x0,z0\.s,sxtw #1\]
-.*:    84602800        prfh    pldl1keep, p2, \[x0,z0\.s,sxtw #1\]
-.*:    84603c00        prfh    pldl1keep, p7, \[x0,z0\.s,sxtw #1\]
-.*:    84603c00        prfh    pldl1keep, p7, \[x0,z0\.s,sxtw #1\]
-.*:    84602060        prfh    pldl1keep, p0, \[x3,z0\.s,sxtw #1\]
-.*:    84602060        prfh    pldl1keep, p0, \[x3,z0\.s,sxtw #1\]
-.*:    846023e0        prfh    pldl1keep, p0, \[sp,z0\.s,sxtw #1\]
-.*:    846023e0        prfh    pldl1keep, p0, \[sp,z0\.s,sxtw #1\]
-.*:    84642000        prfh    pldl1keep, p0, \[x0,z4\.s,sxtw #1\]
-.*:    84642000        prfh    pldl1keep, p0, \[x0,z4\.s,sxtw #1\]
-.*:    847f2000        prfh    pldl1keep, p0, \[x0,z31\.s,sxtw #1\]
-.*:    847f2000        prfh    pldl1keep, p0, \[x0,z31\.s,sxtw #1\]
-.*:    8480c000        prfh    pldl1keep, p0, \[x0,x0,lsl #1\]
-.*:    8480c000        prfh    pldl1keep, p0, \[x0,x0,lsl #1\]
-.*:    8480c001        prfh    pldl1strm, p0, \[x0,x0,lsl #1\]
-.*:    8480c001        prfh    pldl1strm, p0, \[x0,x0,lsl #1\]
-.*:    8480c002        prfh    pldl2keep, p0, \[x0,x0,lsl #1\]
-.*:    8480c002        prfh    pldl2keep, p0, \[x0,x0,lsl #1\]
-.*:    8480c003        prfh    pldl2strm, p0, \[x0,x0,lsl #1\]
-.*:    8480c003        prfh    pldl2strm, p0, \[x0,x0,lsl #1\]
-.*:    8480c004        prfh    pldl3keep, p0, \[x0,x0,lsl #1\]
-.*:    8480c004        prfh    pldl3keep, p0, \[x0,x0,lsl #1\]
-.*:    8480c005        prfh    pldl3strm, p0, \[x0,x0,lsl #1\]
-.*:    8480c005        prfh    pldl3strm, p0, \[x0,x0,lsl #1\]
-.*:    8480c006        prfh    #6, p0, \[x0,x0,lsl #1\]
-.*:    8480c006        prfh    #6, p0, \[x0,x0,lsl #1\]
-.*:    8480c007        prfh    #7, p0, \[x0,x0,lsl #1\]
-.*:    8480c007        prfh    #7, p0, \[x0,x0,lsl #1\]
-.*:    8480c008        prfh    pstl1keep, p0, \[x0,x0,lsl #1\]
-.*:    8480c008        prfh    pstl1keep, p0, \[x0,x0,lsl #1\]
-.*:    8480c009        prfh    pstl1strm, p0, \[x0,x0,lsl #1\]
-.*:    8480c009        prfh    pstl1strm, p0, \[x0,x0,lsl #1\]
-.*:    8480c00a        prfh    pstl2keep, p0, \[x0,x0,lsl #1\]
-.*:    8480c00a        prfh    pstl2keep, p0, \[x0,x0,lsl #1\]
-.*:    8480c00b        prfh    pstl2strm, p0, \[x0,x0,lsl #1\]
-.*:    8480c00b        prfh    pstl2strm, p0, \[x0,x0,lsl #1\]
-.*:    8480c00c        prfh    pstl3keep, p0, \[x0,x0,lsl #1\]
-.*:    8480c00c        prfh    pstl3keep, p0, \[x0,x0,lsl #1\]
-.*:    8480c00d        prfh    pstl3strm, p0, \[x0,x0,lsl #1\]
-.*:    8480c00d        prfh    pstl3strm, p0, \[x0,x0,lsl #1\]
-.*:    8480c00e        prfh    #14, p0, \[x0,x0,lsl #1\]
-.*:    8480c00e        prfh    #14, p0, \[x0,x0,lsl #1\]
-.*:    8480c00f        prfh    #15, p0, \[x0,x0,lsl #1\]
-.*:    8480c00f        prfh    #15, p0, \[x0,x0,lsl #1\]
-.*:    8480c800        prfh    pldl1keep, p2, \[x0,x0,lsl #1\]
-.*:    8480c800        prfh    pldl1keep, p2, \[x0,x0,lsl #1\]
-.*:    8480dc00        prfh    pldl1keep, p7, \[x0,x0,lsl #1\]
-.*:    8480dc00        prfh    pldl1keep, p7, \[x0,x0,lsl #1\]
-.*:    8480c060        prfh    pldl1keep, p0, \[x3,x0,lsl #1\]
-.*:    8480c060        prfh    pldl1keep, p0, \[x3,x0,lsl #1\]
-.*:    8480c3e0        prfh    pldl1keep, p0, \[sp,x0,lsl #1\]
-.*:    8480c3e0        prfh    pldl1keep, p0, \[sp,x0,lsl #1\]
-.*:    8484c000        prfh    pldl1keep, p0, \[x0,x4,lsl #1\]
-.*:    8484c000        prfh    pldl1keep, p0, \[x0,x4,lsl #1\]
-.*:    849ec000        prfh    pldl1keep, p0, \[x0,x30,lsl #1\]
-.*:    849ec000        prfh    pldl1keep, p0, \[x0,x30,lsl #1\]
-.*:    c4202000        prfh    pldl1keep, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202000        prfh    pldl1keep, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202001        prfh    pldl1strm, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202001        prfh    pldl1strm, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202002        prfh    pldl2keep, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202002        prfh    pldl2keep, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202003        prfh    pldl2strm, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202003        prfh    pldl2strm, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202004        prfh    pldl3keep, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202004        prfh    pldl3keep, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202005        prfh    pldl3strm, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202005        prfh    pldl3strm, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202006        prfh    #6, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202006        prfh    #6, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202007        prfh    #7, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202007        prfh    #7, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202008        prfh    pstl1keep, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202008        prfh    pstl1keep, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202009        prfh    pstl1strm, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202009        prfh    pstl1strm, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c420200a        prfh    pstl2keep, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c420200a        prfh    pstl2keep, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c420200b        prfh    pstl2strm, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c420200b        prfh    pstl2strm, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c420200c        prfh    pstl3keep, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c420200c        prfh    pstl3keep, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c420200d        prfh    pstl3strm, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c420200d        prfh    pstl3strm, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c420200e        prfh    #14, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c420200e        prfh    #14, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c420200f        prfh    #15, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c420200f        prfh    #15, p0, \[x0,z0\.d,uxtw #1\]
-.*:    c4202800        prfh    pldl1keep, p2, \[x0,z0\.d,uxtw #1\]
-.*:    c4202800        prfh    pldl1keep, p2, \[x0,z0\.d,uxtw #1\]
-.*:    c4203c00        prfh    pldl1keep, p7, \[x0,z0\.d,uxtw #1\]
-.*:    c4203c00        prfh    pldl1keep, p7, \[x0,z0\.d,uxtw #1\]
-.*:    c4202060        prfh    pldl1keep, p0, \[x3,z0\.d,uxtw #1\]
-.*:    c4202060        prfh    pldl1keep, p0, \[x3,z0\.d,uxtw #1\]
-.*:    c42023e0        prfh    pldl1keep, p0, \[sp,z0\.d,uxtw #1\]
-.*:    c42023e0        prfh    pldl1keep, p0, \[sp,z0\.d,uxtw #1\]
-.*:    c4242000        prfh    pldl1keep, p0, \[x0,z4\.d,uxtw #1\]
-.*:    c4242000        prfh    pldl1keep, p0, \[x0,z4\.d,uxtw #1\]
-.*:    c43f2000        prfh    pldl1keep, p0, \[x0,z31\.d,uxtw #1\]
-.*:    c43f2000        prfh    pldl1keep, p0, \[x0,z31\.d,uxtw #1\]
-.*:    c4602000        prfh    pldl1keep, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602000        prfh    pldl1keep, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602001        prfh    pldl1strm, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602001        prfh    pldl1strm, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602002        prfh    pldl2keep, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602002        prfh    pldl2keep, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602003        prfh    pldl2strm, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602003        prfh    pldl2strm, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602004        prfh    pldl3keep, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602004        prfh    pldl3keep, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602005        prfh    pldl3strm, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602005        prfh    pldl3strm, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602006        prfh    #6, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602006        prfh    #6, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602007        prfh    #7, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602007        prfh    #7, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602008        prfh    pstl1keep, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602008        prfh    pstl1keep, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602009        prfh    pstl1strm, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602009        prfh    pstl1strm, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c460200a        prfh    pstl2keep, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c460200a        prfh    pstl2keep, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c460200b        prfh    pstl2strm, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c460200b        prfh    pstl2strm, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c460200c        prfh    pstl3keep, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c460200c        prfh    pstl3keep, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c460200d        prfh    pstl3strm, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c460200d        prfh    pstl3strm, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c460200e        prfh    #14, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c460200e        prfh    #14, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c460200f        prfh    #15, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c460200f        prfh    #15, p0, \[x0,z0\.d,sxtw #1\]
-.*:    c4602800        prfh    pldl1keep, p2, \[x0,z0\.d,sxtw #1\]
-.*:    c4602800        prfh    pldl1keep, p2, \[x0,z0\.d,sxtw #1\]
-.*:    c4603c00        prfh    pldl1keep, p7, \[x0,z0\.d,sxtw #1\]
-.*:    c4603c00        prfh    pldl1keep, p7, \[x0,z0\.d,sxtw #1\]
-.*:    c4602060        prfh    pldl1keep, p0, \[x3,z0\.d,sxtw #1\]
-.*:    c4602060        prfh    pldl1keep, p0, \[x3,z0\.d,sxtw #1\]
-.*:    c46023e0        prfh    pldl1keep, p0, \[sp,z0\.d,sxtw #1\]
-.*:    c46023e0        prfh    pldl1keep, p0, \[sp,z0\.d,sxtw #1\]
-.*:    c4642000        prfh    pldl1keep, p0, \[x0,z4\.d,sxtw #1\]
-.*:    c4642000        prfh    pldl1keep, p0, \[x0,z4\.d,sxtw #1\]
-.*:    c47f2000        prfh    pldl1keep, p0, \[x0,z31\.d,sxtw #1\]
-.*:    c47f2000        prfh    pldl1keep, p0, \[x0,z31\.d,sxtw #1\]
-.*:    c460a000        prfh    pldl1keep, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a000        prfh    pldl1keep, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a001        prfh    pldl1strm, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a001        prfh    pldl1strm, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a002        prfh    pldl2keep, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a002        prfh    pldl2keep, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a003        prfh    pldl2strm, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a003        prfh    pldl2strm, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a004        prfh    pldl3keep, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a004        prfh    pldl3keep, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a005        prfh    pldl3strm, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a005        prfh    pldl3strm, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a006        prfh    #6, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a006        prfh    #6, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a007        prfh    #7, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a007        prfh    #7, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a008        prfh    pstl1keep, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a008        prfh    pstl1keep, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a009        prfh    pstl1strm, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a009        prfh    pstl1strm, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a00a        prfh    pstl2keep, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a00a        prfh    pstl2keep, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a00b        prfh    pstl2strm, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a00b        prfh    pstl2strm, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a00c        prfh    pstl3keep, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a00c        prfh    pstl3keep, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a00d        prfh    pstl3strm, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a00d        prfh    pstl3strm, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a00e        prfh    #14, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a00e        prfh    #14, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a00f        prfh    #15, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a00f        prfh    #15, p0, \[x0,z0\.d,lsl #1\]
-.*:    c460a800        prfh    pldl1keep, p2, \[x0,z0\.d,lsl #1\]
-.*:    c460a800        prfh    pldl1keep, p2, \[x0,z0\.d,lsl #1\]
-.*:    c460bc00        prfh    pldl1keep, p7, \[x0,z0\.d,lsl #1\]
-.*:    c460bc00        prfh    pldl1keep, p7, \[x0,z0\.d,lsl #1\]
-.*:    c460a060        prfh    pldl1keep, p0, \[x3,z0\.d,lsl #1\]
-.*:    c460a060        prfh    pldl1keep, p0, \[x3,z0\.d,lsl #1\]
-.*:    c460a3e0        prfh    pldl1keep, p0, \[sp,z0\.d,lsl #1\]
-.*:    c460a3e0        prfh    pldl1keep, p0, \[sp,z0\.d,lsl #1\]
-.*:    c464a000        prfh    pldl1keep, p0, \[x0,z4\.d,lsl #1\]
-.*:    c464a000        prfh    pldl1keep, p0, \[x0,z4\.d,lsl #1\]
-.*:    c47fa000        prfh    pldl1keep, p0, \[x0,z31\.d,lsl #1\]
-.*:    c47fa000        prfh    pldl1keep, p0, \[x0,z31\.d,lsl #1\]
+.*:    c58fe000        prfd    pldl1keep, p0, \[z0\.d, #120\]
+.*:    c58fe000        prfd    pldl1keep, p0, \[z0\.d, #120\]
+.*:    c590e000        prfd    pldl1keep, p0, \[z0\.d, #128\]
+.*:    c590e000        prfd    pldl1keep, p0, \[z0\.d, #128\]
+.*:    c591e000        prfd    pldl1keep, p0, \[z0\.d, #136\]
+.*:    c591e000        prfd    pldl1keep, p0, \[z0\.d, #136\]
+.*:    c59fe000        prfd    pldl1keep, p0, \[z0\.d, #248\]
+.*:    c59fe000        prfd    pldl1keep, p0, \[z0\.d, #248\]
+.*:    84202000        prfh    pldl1keep, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202000        prfh    pldl1keep, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202001        prfh    pldl1strm, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202001        prfh    pldl1strm, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202002        prfh    pldl2keep, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202002        prfh    pldl2keep, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202003        prfh    pldl2strm, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202003        prfh    pldl2strm, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202004        prfh    pldl3keep, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202004        prfh    pldl3keep, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202005        prfh    pldl3strm, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202005        prfh    pldl3strm, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202006        prfh    #6, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202006        prfh    #6, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202007        prfh    #7, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202007        prfh    #7, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202008        prfh    pstl1keep, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202008        prfh    pstl1keep, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202009        prfh    pstl1strm, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202009        prfh    pstl1strm, p0, \[x0, z0\.s, uxtw #1\]
+.*:    8420200a        prfh    pstl2keep, p0, \[x0, z0\.s, uxtw #1\]
+.*:    8420200a        prfh    pstl2keep, p0, \[x0, z0\.s, uxtw #1\]
+.*:    8420200b        prfh    pstl2strm, p0, \[x0, z0\.s, uxtw #1\]
+.*:    8420200b        prfh    pstl2strm, p0, \[x0, z0\.s, uxtw #1\]
+.*:    8420200c        prfh    pstl3keep, p0, \[x0, z0\.s, uxtw #1\]
+.*:    8420200c        prfh    pstl3keep, p0, \[x0, z0\.s, uxtw #1\]
+.*:    8420200d        prfh    pstl3strm, p0, \[x0, z0\.s, uxtw #1\]
+.*:    8420200d        prfh    pstl3strm, p0, \[x0, z0\.s, uxtw #1\]
+.*:    8420200e        prfh    #14, p0, \[x0, z0\.s, uxtw #1\]
+.*:    8420200e        prfh    #14, p0, \[x0, z0\.s, uxtw #1\]
+.*:    8420200f        prfh    #15, p0, \[x0, z0\.s, uxtw #1\]
+.*:    8420200f        prfh    #15, p0, \[x0, z0\.s, uxtw #1\]
+.*:    84202800        prfh    pldl1keep, p2, \[x0, z0\.s, uxtw #1\]
+.*:    84202800        prfh    pldl1keep, p2, \[x0, z0\.s, uxtw #1\]
+.*:    84203c00        prfh    pldl1keep, p7, \[x0, z0\.s, uxtw #1\]
+.*:    84203c00        prfh    pldl1keep, p7, \[x0, z0\.s, uxtw #1\]
+.*:    84202060        prfh    pldl1keep, p0, \[x3, z0\.s, uxtw #1\]
+.*:    84202060        prfh    pldl1keep, p0, \[x3, z0\.s, uxtw #1\]
+.*:    842023e0        prfh    pldl1keep, p0, \[sp, z0\.s, uxtw #1\]
+.*:    842023e0        prfh    pldl1keep, p0, \[sp, z0\.s, uxtw #1\]
+.*:    84242000        prfh    pldl1keep, p0, \[x0, z4\.s, uxtw #1\]
+.*:    84242000        prfh    pldl1keep, p0, \[x0, z4\.s, uxtw #1\]
+.*:    843f2000        prfh    pldl1keep, p0, \[x0, z31\.s, uxtw #1\]
+.*:    843f2000        prfh    pldl1keep, p0, \[x0, z31\.s, uxtw #1\]
+.*:    84602000        prfh    pldl1keep, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602000        prfh    pldl1keep, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602001        prfh    pldl1strm, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602001        prfh    pldl1strm, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602002        prfh    pldl2keep, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602002        prfh    pldl2keep, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602003        prfh    pldl2strm, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602003        prfh    pldl2strm, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602004        prfh    pldl3keep, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602004        prfh    pldl3keep, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602005        prfh    pldl3strm, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602005        prfh    pldl3strm, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602006        prfh    #6, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602006        prfh    #6, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602007        prfh    #7, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602007        prfh    #7, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602008        prfh    pstl1keep, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602008        prfh    pstl1keep, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602009        prfh    pstl1strm, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602009        prfh    pstl1strm, p0, \[x0, z0\.s, sxtw #1\]
+.*:    8460200a        prfh    pstl2keep, p0, \[x0, z0\.s, sxtw #1\]
+.*:    8460200a        prfh    pstl2keep, p0, \[x0, z0\.s, sxtw #1\]
+.*:    8460200b        prfh    pstl2strm, p0, \[x0, z0\.s, sxtw #1\]
+.*:    8460200b        prfh    pstl2strm, p0, \[x0, z0\.s, sxtw #1\]
+.*:    8460200c        prfh    pstl3keep, p0, \[x0, z0\.s, sxtw #1\]
+.*:    8460200c        prfh    pstl3keep, p0, \[x0, z0\.s, sxtw #1\]
+.*:    8460200d        prfh    pstl3strm, p0, \[x0, z0\.s, sxtw #1\]
+.*:    8460200d        prfh    pstl3strm, p0, \[x0, z0\.s, sxtw #1\]
+.*:    8460200e        prfh    #14, p0, \[x0, z0\.s, sxtw #1\]
+.*:    8460200e        prfh    #14, p0, \[x0, z0\.s, sxtw #1\]
+.*:    8460200f        prfh    #15, p0, \[x0, z0\.s, sxtw #1\]
+.*:    8460200f        prfh    #15, p0, \[x0, z0\.s, sxtw #1\]
+.*:    84602800        prfh    pldl1keep, p2, \[x0, z0\.s, sxtw #1\]
+.*:    84602800        prfh    pldl1keep, p2, \[x0, z0\.s, sxtw #1\]
+.*:    84603c00        prfh    pldl1keep, p7, \[x0, z0\.s, sxtw #1\]
+.*:    84603c00        prfh    pldl1keep, p7, \[x0, z0\.s, sxtw #1\]
+.*:    84602060        prfh    pldl1keep, p0, \[x3, z0\.s, sxtw #1\]
+.*:    84602060        prfh    pldl1keep, p0, \[x3, z0\.s, sxtw #1\]
+.*:    846023e0        prfh    pldl1keep, p0, \[sp, z0\.s, sxtw #1\]
+.*:    846023e0        prfh    pldl1keep, p0, \[sp, z0\.s, sxtw #1\]
+.*:    84642000        prfh    pldl1keep, p0, \[x0, z4\.s, sxtw #1\]
+.*:    84642000        prfh    pldl1keep, p0, \[x0, z4\.s, sxtw #1\]
+.*:    847f2000        prfh    pldl1keep, p0, \[x0, z31\.s, sxtw #1\]
+.*:    847f2000        prfh    pldl1keep, p0, \[x0, z31\.s, sxtw #1\]
+.*:    8480c000        prfh    pldl1keep, p0, \[x0, x0, lsl #1\]
+.*:    8480c000        prfh    pldl1keep, p0, \[x0, x0, lsl #1\]
+.*:    8480c001        prfh    pldl1strm, p0, \[x0, x0, lsl #1\]
+.*:    8480c001        prfh    pldl1strm, p0, \[x0, x0, lsl #1\]
+.*:    8480c002        prfh    pldl2keep, p0, \[x0, x0, lsl #1\]
+.*:    8480c002        prfh    pldl2keep, p0, \[x0, x0, lsl #1\]
+.*:    8480c003        prfh    pldl2strm, p0, \[x0, x0, lsl #1\]
+.*:    8480c003        prfh    pldl2strm, p0, \[x0, x0, lsl #1\]
+.*:    8480c004        prfh    pldl3keep, p0, \[x0, x0, lsl #1\]
+.*:    8480c004        prfh    pldl3keep, p0, \[x0, x0, lsl #1\]
+.*:    8480c005        prfh    pldl3strm, p0, \[x0, x0, lsl #1\]
+.*:    8480c005        prfh    pldl3strm, p0, \[x0, x0, lsl #1\]
+.*:    8480c006        prfh    #6, p0, \[x0, x0, lsl #1\]
+.*:    8480c006        prfh    #6, p0, \[x0, x0, lsl #1\]
+.*:    8480c007        prfh    #7, p0, \[x0, x0, lsl #1\]
+.*:    8480c007        prfh    #7, p0, \[x0, x0, lsl #1\]
+.*:    8480c008        prfh    pstl1keep, p0, \[x0, x0, lsl #1\]
+.*:    8480c008        prfh    pstl1keep, p0, \[x0, x0, lsl #1\]
+.*:    8480c009        prfh    pstl1strm, p0, \[x0, x0, lsl #1\]
+.*:    8480c009        prfh    pstl1strm, p0, \[x0, x0, lsl #1\]
+.*:    8480c00a        prfh    pstl2keep, p0, \[x0, x0, lsl #1\]
+.*:    8480c00a        prfh    pstl2keep, p0, \[x0, x0, lsl #1\]
+.*:    8480c00b        prfh    pstl2strm, p0, \[x0, x0, lsl #1\]
+.*:    8480c00b        prfh    pstl2strm, p0, \[x0, x0, lsl #1\]
+.*:    8480c00c        prfh    pstl3keep, p0, \[x0, x0, lsl #1\]
+.*:    8480c00c        prfh    pstl3keep, p0, \[x0, x0, lsl #1\]
+.*:    8480c00d        prfh    pstl3strm, p0, \[x0, x0, lsl #1\]
+.*:    8480c00d        prfh    pstl3strm, p0, \[x0, x0, lsl #1\]
+.*:    8480c00e        prfh    #14, p0, \[x0, x0, lsl #1\]
+.*:    8480c00e        prfh    #14, p0, \[x0, x0, lsl #1\]
+.*:    8480c00f        prfh    #15, p0, \[x0, x0, lsl #1\]
+.*:    8480c00f        prfh    #15, p0, \[x0, x0, lsl #1\]
+.*:    8480c800        prfh    pldl1keep, p2, \[x0, x0, lsl #1\]
+.*:    8480c800        prfh    pldl1keep, p2, \[x0, x0, lsl #1\]
+.*:    8480dc00        prfh    pldl1keep, p7, \[x0, x0, lsl #1\]
+.*:    8480dc00        prfh    pldl1keep, p7, \[x0, x0, lsl #1\]
+.*:    8480c060        prfh    pldl1keep, p0, \[x3, x0, lsl #1\]
+.*:    8480c060        prfh    pldl1keep, p0, \[x3, x0, lsl #1\]
+.*:    8480c3e0        prfh    pldl1keep, p0, \[sp, x0, lsl #1\]
+.*:    8480c3e0        prfh    pldl1keep, p0, \[sp, x0, lsl #1\]
+.*:    8484c000        prfh    pldl1keep, p0, \[x0, x4, lsl #1\]
+.*:    8484c000        prfh    pldl1keep, p0, \[x0, x4, lsl #1\]
+.*:    849ec000        prfh    pldl1keep, p0, \[x0, x30, lsl #1\]
+.*:    849ec000        prfh    pldl1keep, p0, \[x0, x30, lsl #1\]
+.*:    c4202000        prfh    pldl1keep, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202000        prfh    pldl1keep, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202001        prfh    pldl1strm, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202001        prfh    pldl1strm, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202002        prfh    pldl2keep, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202002        prfh    pldl2keep, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202003        prfh    pldl2strm, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202003        prfh    pldl2strm, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202004        prfh    pldl3keep, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202004        prfh    pldl3keep, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202005        prfh    pldl3strm, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202005        prfh    pldl3strm, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202006        prfh    #6, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202006        prfh    #6, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202007        prfh    #7, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202007        prfh    #7, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202008        prfh    pstl1keep, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202008        prfh    pstl1keep, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202009        prfh    pstl1strm, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202009        prfh    pstl1strm, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c420200a        prfh    pstl2keep, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c420200a        prfh    pstl2keep, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c420200b        prfh    pstl2strm, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c420200b        prfh    pstl2strm, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c420200c        prfh    pstl3keep, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c420200c        prfh    pstl3keep, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c420200d        prfh    pstl3strm, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c420200d        prfh    pstl3strm, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c420200e        prfh    #14, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c420200e        prfh    #14, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c420200f        prfh    #15, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c420200f        prfh    #15, p0, \[x0, z0\.d, uxtw #1\]
+.*:    c4202800        prfh    pldl1keep, p2, \[x0, z0\.d, uxtw #1\]
+.*:    c4202800        prfh    pldl1keep, p2, \[x0, z0\.d, uxtw #1\]
+.*:    c4203c00        prfh    pldl1keep, p7, \[x0, z0\.d, uxtw #1\]
+.*:    c4203c00        prfh    pldl1keep, p7, \[x0, z0\.d, uxtw #1\]
+.*:    c4202060        prfh    pldl1keep, p0, \[x3, z0\.d, uxtw #1\]
+.*:    c4202060        prfh    pldl1keep, p0, \[x3, z0\.d, uxtw #1\]
+.*:    c42023e0        prfh    pldl1keep, p0, \[sp, z0\.d, uxtw #1\]
+.*:    c42023e0        prfh    pldl1keep, p0, \[sp, z0\.d, uxtw #1\]
+.*:    c4242000        prfh    pldl1keep, p0, \[x0, z4\.d, uxtw #1\]
+.*:    c4242000        prfh    pldl1keep, p0, \[x0, z4\.d, uxtw #1\]
+.*:    c43f2000        prfh    pldl1keep, p0, \[x0, z31\.d, uxtw #1\]
+.*:    c43f2000        prfh    pldl1keep, p0, \[x0, z31\.d, uxtw #1\]
+.*:    c4602000        prfh    pldl1keep, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602000        prfh    pldl1keep, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602001        prfh    pldl1strm, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602001        prfh    pldl1strm, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602002        prfh    pldl2keep, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602002        prfh    pldl2keep, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602003        prfh    pldl2strm, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602003        prfh    pldl2strm, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602004        prfh    pldl3keep, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602004        prfh    pldl3keep, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602005        prfh    pldl3strm, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602005        prfh    pldl3strm, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602006        prfh    #6, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602006        prfh    #6, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602007        prfh    #7, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602007        prfh    #7, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602008        prfh    pstl1keep, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602008        prfh    pstl1keep, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602009        prfh    pstl1strm, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602009        prfh    pstl1strm, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c460200a        prfh    pstl2keep, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c460200a        prfh    pstl2keep, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c460200b        prfh    pstl2strm, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c460200b        prfh    pstl2strm, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c460200c        prfh    pstl3keep, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c460200c        prfh    pstl3keep, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c460200d        prfh    pstl3strm, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c460200d        prfh    pstl3strm, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c460200e        prfh    #14, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c460200e        prfh    #14, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c460200f        prfh    #15, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c460200f        prfh    #15, p0, \[x0, z0\.d, sxtw #1\]
+.*:    c4602800        prfh    pldl1keep, p2, \[x0, z0\.d, sxtw #1\]
+.*:    c4602800        prfh    pldl1keep, p2, \[x0, z0\.d, sxtw #1\]
+.*:    c4603c00        prfh    pldl1keep, p7, \[x0, z0\.d, sxtw #1\]
+.*:    c4603c00        prfh    pldl1keep, p7, \[x0, z0\.d, sxtw #1\]
+.*:    c4602060        prfh    pldl1keep, p0, \[x3, z0\.d, sxtw #1\]
+.*:    c4602060        prfh    pldl1keep, p0, \[x3, z0\.d, sxtw #1\]
+.*:    c46023e0        prfh    pldl1keep, p0, \[sp, z0\.d, sxtw #1\]
+.*:    c46023e0        prfh    pldl1keep, p0, \[sp, z0\.d, sxtw #1\]
+.*:    c4642000        prfh    pldl1keep, p0, \[x0, z4\.d, sxtw #1\]
+.*:    c4642000        prfh    pldl1keep, p0, \[x0, z4\.d, sxtw #1\]
+.*:    c47f2000        prfh    pldl1keep, p0, \[x0, z31\.d, sxtw #1\]
+.*:    c47f2000        prfh    pldl1keep, p0, \[x0, z31\.d, sxtw #1\]
+.*:    c460a000        prfh    pldl1keep, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a000        prfh    pldl1keep, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a001        prfh    pldl1strm, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a001        prfh    pldl1strm, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a002        prfh    pldl2keep, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a002        prfh    pldl2keep, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a003        prfh    pldl2strm, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a003        prfh    pldl2strm, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a004        prfh    pldl3keep, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a004        prfh    pldl3keep, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a005        prfh    pldl3strm, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a005        prfh    pldl3strm, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a006        prfh    #6, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a006        prfh    #6, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a007        prfh    #7, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a007        prfh    #7, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a008        prfh    pstl1keep, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a008        prfh    pstl1keep, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a009        prfh    pstl1strm, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a009        prfh    pstl1strm, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a00a        prfh    pstl2keep, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a00a        prfh    pstl2keep, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a00b        prfh    pstl2strm, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a00b        prfh    pstl2strm, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a00c        prfh    pstl3keep, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a00c        prfh    pstl3keep, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a00d        prfh    pstl3strm, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a00d        prfh    pstl3strm, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a00e        prfh    #14, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a00e        prfh    #14, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a00f        prfh    #15, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a00f        prfh    #15, p0, \[x0, z0\.d, lsl #1\]
+.*:    c460a800        prfh    pldl1keep, p2, \[x0, z0\.d, lsl #1\]
+.*:    c460a800        prfh    pldl1keep, p2, \[x0, z0\.d, lsl #1\]
+.*:    c460bc00        prfh    pldl1keep, p7, \[x0, z0\.d, lsl #1\]
+.*:    c460bc00        prfh    pldl1keep, p7, \[x0, z0\.d, lsl #1\]
+.*:    c460a060        prfh    pldl1keep, p0, \[x3, z0\.d, lsl #1\]
+.*:    c460a060        prfh    pldl1keep, p0, \[x3, z0\.d, lsl #1\]
+.*:    c460a3e0        prfh    pldl1keep, p0, \[sp, z0\.d, lsl #1\]
+.*:    c460a3e0        prfh    pldl1keep, p0, \[sp, z0\.d, lsl #1\]
+.*:    c464a000        prfh    pldl1keep, p0, \[x0, z4\.d, lsl #1\]
+.*:    c464a000        prfh    pldl1keep, p0, \[x0, z4\.d, lsl #1\]
+.*:    c47fa000        prfh    pldl1keep, p0, \[x0, z31\.d, lsl #1\]
+.*:    c47fa000        prfh    pldl1keep, p0, \[x0, z31\.d, lsl #1\]
 .*:    8480e000        prfh    pldl1keep, p0, \[z0\.s\]
 .*:    8480e000        prfh    pldl1keep, p0, \[z0\.s\]
 .*:    8480e000        prfh    pldl1keep, p0, \[z0\.s\]
@@ -23418,14 +23418,14 @@ Disassembly of section .*:
 .*:    8480e3e0        prfh    pldl1keep, p0, \[z31\.s\]
 .*:    8480e3e0        prfh    pldl1keep, p0, \[z31\.s\]
 .*:    8480e3e0        prfh    pldl1keep, p0, \[z31\.s\]
-.*:    848fe000        prfh    pldl1keep, p0, \[z0\.s,#30\]
-.*:    848fe000        prfh    pldl1keep, p0, \[z0\.s,#30\]
-.*:    8490e000        prfh    pldl1keep, p0, \[z0\.s,#32\]
-.*:    8490e000        prfh    pldl1keep, p0, \[z0\.s,#32\]
-.*:    8491e000        prfh    pldl1keep, p0, \[z0\.s,#34\]
-.*:    8491e000        prfh    pldl1keep, p0, \[z0\.s,#34\]
-.*:    849fe000        prfh    pldl1keep, p0, \[z0\.s,#62\]
-.*:    849fe000        prfh    pldl1keep, p0, \[z0\.s,#62\]
+.*:    848fe000        prfh    pldl1keep, p0, \[z0\.s, #30\]
+.*:    848fe000        prfh    pldl1keep, p0, \[z0\.s, #30\]
+.*:    8490e000        prfh    pldl1keep, p0, \[z0\.s, #32\]
+.*:    8490e000        prfh    pldl1keep, p0, \[z0\.s, #32\]
+.*:    8491e000        prfh    pldl1keep, p0, \[z0\.s, #34\]
+.*:    8491e000        prfh    pldl1keep, p0, \[z0\.s, #34\]
+.*:    849fe000        prfh    pldl1keep, p0, \[z0\.s, #62\]
+.*:    849fe000        prfh    pldl1keep, p0, \[z0\.s, #62\]
 .*:    85c02000        prfh    pldl1keep, p0, \[x0\]
 .*:    85c02000        prfh    pldl1keep, p0, \[x0\]
 .*:    85c02000        prfh    pldl1keep, p0, \[x0\]
@@ -23506,14 +23506,14 @@ Disassembly of section .*:
 .*:    85c023e0        prfh    pldl1keep, p0, \[sp\]
 .*:    85c023e0        prfh    pldl1keep, p0, \[sp\]
 .*:    85c023e0        prfh    pldl1keep, p0, \[sp\]
-.*:    85df2000        prfh    pldl1keep, p0, \[x0,#31,mul vl\]
-.*:    85df2000        prfh    pldl1keep, p0, \[x0,#31,mul vl\]
-.*:    85e02000        prfh    pldl1keep, p0, \[x0,#-32,mul vl\]
-.*:    85e02000        prfh    pldl1keep, p0, \[x0,#-32,mul vl\]
-.*:    85e12000        prfh    pldl1keep, p0, \[x0,#-31,mul vl\]
-.*:    85e12000        prfh    pldl1keep, p0, \[x0,#-31,mul vl\]
-.*:    85ff2000        prfh    pldl1keep, p0, \[x0,#-1,mul vl\]
-.*:    85ff2000        prfh    pldl1keep, p0, \[x0,#-1,mul vl\]
+.*:    85df2000        prfh    pldl1keep, p0, \[x0, #31, mul vl\]
+.*:    85df2000        prfh    pldl1keep, p0, \[x0, #31, mul vl\]
+.*:    85e02000        prfh    pldl1keep, p0, \[x0, #-32, mul vl\]
+.*:    85e02000        prfh    pldl1keep, p0, \[x0, #-32, mul vl\]
+.*:    85e12000        prfh    pldl1keep, p0, \[x0, #-31, mul vl\]
+.*:    85e12000        prfh    pldl1keep, p0, \[x0, #-31, mul vl\]
+.*:    85ff2000        prfh    pldl1keep, p0, \[x0, #-1, mul vl\]
+.*:    85ff2000        prfh    pldl1keep, p0, \[x0, #-1, mul vl\]
 .*:    c480e000        prfh    pldl1keep, p0, \[z0\.d\]
 .*:    c480e000        prfh    pldl1keep, p0, \[z0\.d\]
 .*:    c480e000        prfh    pldl1keep, p0, \[z0\.d\]
@@ -23574,278 +23574,278 @@ Disassembly of section .*:
 .*:    c480e3e0        prfh    pldl1keep, p0, \[z31\.d\]
 .*:    c480e3e0        prfh    pldl1keep, p0, \[z31\.d\]
 .*:    c480e3e0        prfh    pldl1keep, p0, \[z31\.d\]
-.*:    c48fe000        prfh    pldl1keep, p0, \[z0\.d,#30\]
-.*:    c48fe000        prfh    pldl1keep, p0, \[z0\.d,#30\]
-.*:    c490e000        prfh    pldl1keep, p0, \[z0\.d,#32\]
-.*:    c490e000        prfh    pldl1keep, p0, \[z0\.d,#32\]
-.*:    c491e000        prfh    pldl1keep, p0, \[z0\.d,#34\]
-.*:    c491e000        prfh    pldl1keep, p0, \[z0\.d,#34\]
-.*:    c49fe000        prfh    pldl1keep, p0, \[z0\.d,#62\]
-.*:    c49fe000        prfh    pldl1keep, p0, \[z0\.d,#62\]
-.*:    84204000        prfw    pldl1keep, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204000        prfw    pldl1keep, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204001        prfw    pldl1strm, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204001        prfw    pldl1strm, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204002        prfw    pldl2keep, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204002        prfw    pldl2keep, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204003        prfw    pldl2strm, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204003        prfw    pldl2strm, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204004        prfw    pldl3keep, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204004        prfw    pldl3keep, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204005        prfw    pldl3strm, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204005        prfw    pldl3strm, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204006        prfw    #6, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204006        prfw    #6, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204007        prfw    #7, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204007        prfw    #7, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204008        prfw    pstl1keep, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204008        prfw    pstl1keep, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204009        prfw    pstl1strm, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204009        prfw    pstl1strm, p0, \[x0,z0\.s,uxtw #2\]
-.*:    8420400a        prfw    pstl2keep, p0, \[x0,z0\.s,uxtw #2\]
-.*:    8420400a        prfw    pstl2keep, p0, \[x0,z0\.s,uxtw #2\]
-.*:    8420400b        prfw    pstl2strm, p0, \[x0,z0\.s,uxtw #2\]
-.*:    8420400b        prfw    pstl2strm, p0, \[x0,z0\.s,uxtw #2\]
-.*:    8420400c        prfw    pstl3keep, p0, \[x0,z0\.s,uxtw #2\]
-.*:    8420400c        prfw    pstl3keep, p0, \[x0,z0\.s,uxtw #2\]
-.*:    8420400d        prfw    pstl3strm, p0, \[x0,z0\.s,uxtw #2\]
-.*:    8420400d        prfw    pstl3strm, p0, \[x0,z0\.s,uxtw #2\]
-.*:    8420400e        prfw    #14, p0, \[x0,z0\.s,uxtw #2\]
-.*:    8420400e        prfw    #14, p0, \[x0,z0\.s,uxtw #2\]
-.*:    8420400f        prfw    #15, p0, \[x0,z0\.s,uxtw #2\]
-.*:    8420400f        prfw    #15, p0, \[x0,z0\.s,uxtw #2\]
-.*:    84204800        prfw    pldl1keep, p2, \[x0,z0\.s,uxtw #2\]
-.*:    84204800        prfw    pldl1keep, p2, \[x0,z0\.s,uxtw #2\]
-.*:    84205c00        prfw    pldl1keep, p7, \[x0,z0\.s,uxtw #2\]
-.*:    84205c00        prfw    pldl1keep, p7, \[x0,z0\.s,uxtw #2\]
-.*:    84204060        prfw    pldl1keep, p0, \[x3,z0\.s,uxtw #2\]
-.*:    84204060        prfw    pldl1keep, p0, \[x3,z0\.s,uxtw #2\]
-.*:    842043e0        prfw    pldl1keep, p0, \[sp,z0\.s,uxtw #2\]
-.*:    842043e0        prfw    pldl1keep, p0, \[sp,z0\.s,uxtw #2\]
-.*:    84244000        prfw    pldl1keep, p0, \[x0,z4\.s,uxtw #2\]
-.*:    84244000        prfw    pldl1keep, p0, \[x0,z4\.s,uxtw #2\]
-.*:    843f4000        prfw    pldl1keep, p0, \[x0,z31\.s,uxtw #2\]
-.*:    843f4000        prfw    pldl1keep, p0, \[x0,z31\.s,uxtw #2\]
-.*:    84604000        prfw    pldl1keep, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604000        prfw    pldl1keep, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604001        prfw    pldl1strm, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604001        prfw    pldl1strm, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604002        prfw    pldl2keep, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604002        prfw    pldl2keep, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604003        prfw    pldl2strm, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604003        prfw    pldl2strm, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604004        prfw    pldl3keep, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604004        prfw    pldl3keep, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604005        prfw    pldl3strm, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604005        prfw    pldl3strm, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604006        prfw    #6, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604006        prfw    #6, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604007        prfw    #7, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604007        prfw    #7, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604008        prfw    pstl1keep, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604008        prfw    pstl1keep, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604009        prfw    pstl1strm, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604009        prfw    pstl1strm, p0, \[x0,z0\.s,sxtw #2\]
-.*:    8460400a        prfw    pstl2keep, p0, \[x0,z0\.s,sxtw #2\]
-.*:    8460400a        prfw    pstl2keep, p0, \[x0,z0\.s,sxtw #2\]
-.*:    8460400b        prfw    pstl2strm, p0, \[x0,z0\.s,sxtw #2\]
-.*:    8460400b        prfw    pstl2strm, p0, \[x0,z0\.s,sxtw #2\]
-.*:    8460400c        prfw    pstl3keep, p0, \[x0,z0\.s,sxtw #2\]
-.*:    8460400c        prfw    pstl3keep, p0, \[x0,z0\.s,sxtw #2\]
-.*:    8460400d        prfw    pstl3strm, p0, \[x0,z0\.s,sxtw #2\]
-.*:    8460400d        prfw    pstl3strm, p0, \[x0,z0\.s,sxtw #2\]
-.*:    8460400e        prfw    #14, p0, \[x0,z0\.s,sxtw #2\]
-.*:    8460400e        prfw    #14, p0, \[x0,z0\.s,sxtw #2\]
-.*:    8460400f        prfw    #15, p0, \[x0,z0\.s,sxtw #2\]
-.*:    8460400f        prfw    #15, p0, \[x0,z0\.s,sxtw #2\]
-.*:    84604800        prfw    pldl1keep, p2, \[x0,z0\.s,sxtw #2\]
-.*:    84604800        prfw    pldl1keep, p2, \[x0,z0\.s,sxtw #2\]
-.*:    84605c00        prfw    pldl1keep, p7, \[x0,z0\.s,sxtw #2\]
-.*:    84605c00        prfw    pldl1keep, p7, \[x0,z0\.s,sxtw #2\]
-.*:    84604060        prfw    pldl1keep, p0, \[x3,z0\.s,sxtw #2\]
-.*:    84604060        prfw    pldl1keep, p0, \[x3,z0\.s,sxtw #2\]
-.*:    846043e0        prfw    pldl1keep, p0, \[sp,z0\.s,sxtw #2\]
-.*:    846043e0        prfw    pldl1keep, p0, \[sp,z0\.s,sxtw #2\]
-.*:    84644000        prfw    pldl1keep, p0, \[x0,z4\.s,sxtw #2\]
-.*:    84644000        prfw    pldl1keep, p0, \[x0,z4\.s,sxtw #2\]
-.*:    847f4000        prfw    pldl1keep, p0, \[x0,z31\.s,sxtw #2\]
-.*:    847f4000        prfw    pldl1keep, p0, \[x0,z31\.s,sxtw #2\]
-.*:    8500c000        prfw    pldl1keep, p0, \[x0,x0,lsl #2\]
-.*:    8500c000        prfw    pldl1keep, p0, \[x0,x0,lsl #2\]
-.*:    8500c001        prfw    pldl1strm, p0, \[x0,x0,lsl #2\]
-.*:    8500c001        prfw    pldl1strm, p0, \[x0,x0,lsl #2\]
-.*:    8500c002        prfw    pldl2keep, p0, \[x0,x0,lsl #2\]
-.*:    8500c002        prfw    pldl2keep, p0, \[x0,x0,lsl #2\]
-.*:    8500c003        prfw    pldl2strm, p0, \[x0,x0,lsl #2\]
-.*:    8500c003        prfw    pldl2strm, p0, \[x0,x0,lsl #2\]
-.*:    8500c004        prfw    pldl3keep, p0, \[x0,x0,lsl #2\]
-.*:    8500c004        prfw    pldl3keep, p0, \[x0,x0,lsl #2\]
-.*:    8500c005        prfw    pldl3strm, p0, \[x0,x0,lsl #2\]
-.*:    8500c005        prfw    pldl3strm, p0, \[x0,x0,lsl #2\]
-.*:    8500c006        prfw    #6, p0, \[x0,x0,lsl #2\]
-.*:    8500c006        prfw    #6, p0, \[x0,x0,lsl #2\]
-.*:    8500c007        prfw    #7, p0, \[x0,x0,lsl #2\]
-.*:    8500c007        prfw    #7, p0, \[x0,x0,lsl #2\]
-.*:    8500c008        prfw    pstl1keep, p0, \[x0,x0,lsl #2\]
-.*:    8500c008        prfw    pstl1keep, p0, \[x0,x0,lsl #2\]
-.*:    8500c009        prfw    pstl1strm, p0, \[x0,x0,lsl #2\]
-.*:    8500c009        prfw    pstl1strm, p0, \[x0,x0,lsl #2\]
-.*:    8500c00a        prfw    pstl2keep, p0, \[x0,x0,lsl #2\]
-.*:    8500c00a        prfw    pstl2keep, p0, \[x0,x0,lsl #2\]
-.*:    8500c00b        prfw    pstl2strm, p0, \[x0,x0,lsl #2\]
-.*:    8500c00b        prfw    pstl2strm, p0, \[x0,x0,lsl #2\]
-.*:    8500c00c        prfw    pstl3keep, p0, \[x0,x0,lsl #2\]
-.*:    8500c00c        prfw    pstl3keep, p0, \[x0,x0,lsl #2\]
-.*:    8500c00d        prfw    pstl3strm, p0, \[x0,x0,lsl #2\]
-.*:    8500c00d        prfw    pstl3strm, p0, \[x0,x0,lsl #2\]
-.*:    8500c00e        prfw    #14, p0, \[x0,x0,lsl #2\]
-.*:    8500c00e        prfw    #14, p0, \[x0,x0,lsl #2\]
-.*:    8500c00f        prfw    #15, p0, \[x0,x0,lsl #2\]
-.*:    8500c00f        prfw    #15, p0, \[x0,x0,lsl #2\]
-.*:    8500c800        prfw    pldl1keep, p2, \[x0,x0,lsl #2\]
-.*:    8500c800        prfw    pldl1keep, p2, \[x0,x0,lsl #2\]
-.*:    8500dc00        prfw    pldl1keep, p7, \[x0,x0,lsl #2\]
-.*:    8500dc00        prfw    pldl1keep, p7, \[x0,x0,lsl #2\]
-.*:    8500c060        prfw    pldl1keep, p0, \[x3,x0,lsl #2\]
-.*:    8500c060        prfw    pldl1keep, p0, \[x3,x0,lsl #2\]
-.*:    8500c3e0        prfw    pldl1keep, p0, \[sp,x0,lsl #2\]
-.*:    8500c3e0        prfw    pldl1keep, p0, \[sp,x0,lsl #2\]
-.*:    8504c000        prfw    pldl1keep, p0, \[x0,x4,lsl #2\]
-.*:    8504c000        prfw    pldl1keep, p0, \[x0,x4,lsl #2\]
-.*:    851ec000        prfw    pldl1keep, p0, \[x0,x30,lsl #2\]
-.*:    851ec000        prfw    pldl1keep, p0, \[x0,x30,lsl #2\]
-.*:    c4204000        prfw    pldl1keep, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204000        prfw    pldl1keep, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204001        prfw    pldl1strm, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204001        prfw    pldl1strm, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204002        prfw    pldl2keep, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204002        prfw    pldl2keep, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204003        prfw    pldl2strm, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204003        prfw    pldl2strm, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204004        prfw    pldl3keep, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204004        prfw    pldl3keep, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204005        prfw    pldl3strm, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204005        prfw    pldl3strm, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204006        prfw    #6, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204006        prfw    #6, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204007        prfw    #7, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204007        prfw    #7, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204008        prfw    pstl1keep, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204008        prfw    pstl1keep, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204009        prfw    pstl1strm, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204009        prfw    pstl1strm, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c420400a        prfw    pstl2keep, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c420400a        prfw    pstl2keep, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c420400b        prfw    pstl2strm, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c420400b        prfw    pstl2strm, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c420400c        prfw    pstl3keep, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c420400c        prfw    pstl3keep, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c420400d        prfw    pstl3strm, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c420400d        prfw    pstl3strm, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c420400e        prfw    #14, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c420400e        prfw    #14, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c420400f        prfw    #15, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c420400f        prfw    #15, p0, \[x0,z0\.d,uxtw #2\]
-.*:    c4204800        prfw    pldl1keep, p2, \[x0,z0\.d,uxtw #2\]
-.*:    c4204800        prfw    pldl1keep, p2, \[x0,z0\.d,uxtw #2\]
-.*:    c4205c00        prfw    pldl1keep, p7, \[x0,z0\.d,uxtw #2\]
-.*:    c4205c00        prfw    pldl1keep, p7, \[x0,z0\.d,uxtw #2\]
-.*:    c4204060        prfw    pldl1keep, p0, \[x3,z0\.d,uxtw #2\]
-.*:    c4204060        prfw    pldl1keep, p0, \[x3,z0\.d,uxtw #2\]
-.*:    c42043e0        prfw    pldl1keep, p0, \[sp,z0\.d,uxtw #2\]
-.*:    c42043e0        prfw    pldl1keep, p0, \[sp,z0\.d,uxtw #2\]
-.*:    c4244000        prfw    pldl1keep, p0, \[x0,z4\.d,uxtw #2\]
-.*:    c4244000        prfw    pldl1keep, p0, \[x0,z4\.d,uxtw #2\]
-.*:    c43f4000        prfw    pldl1keep, p0, \[x0,z31\.d,uxtw #2\]
-.*:    c43f4000        prfw    pldl1keep, p0, \[x0,z31\.d,uxtw #2\]
-.*:    c4604000        prfw    pldl1keep, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604000        prfw    pldl1keep, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604001        prfw    pldl1strm, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604001        prfw    pldl1strm, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604002        prfw    pldl2keep, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604002        prfw    pldl2keep, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604003        prfw    pldl2strm, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604003        prfw    pldl2strm, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604004        prfw    pldl3keep, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604004        prfw    pldl3keep, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604005        prfw    pldl3strm, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604005        prfw    pldl3strm, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604006        prfw    #6, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604006        prfw    #6, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604007        prfw    #7, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604007        prfw    #7, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604008        prfw    pstl1keep, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604008        prfw    pstl1keep, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604009        prfw    pstl1strm, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604009        prfw    pstl1strm, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c460400a        prfw    pstl2keep, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c460400a        prfw    pstl2keep, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c460400b        prfw    pstl2strm, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c460400b        prfw    pstl2strm, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c460400c        prfw    pstl3keep, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c460400c        prfw    pstl3keep, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c460400d        prfw    pstl3strm, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c460400d        prfw    pstl3strm, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c460400e        prfw    #14, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c460400e        prfw    #14, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c460400f        prfw    #15, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c460400f        prfw    #15, p0, \[x0,z0\.d,sxtw #2\]
-.*:    c4604800        prfw    pldl1keep, p2, \[x0,z0\.d,sxtw #2\]
-.*:    c4604800        prfw    pldl1keep, p2, \[x0,z0\.d,sxtw #2\]
-.*:    c4605c00        prfw    pldl1keep, p7, \[x0,z0\.d,sxtw #2\]
-.*:    c4605c00        prfw    pldl1keep, p7, \[x0,z0\.d,sxtw #2\]
-.*:    c4604060        prfw    pldl1keep, p0, \[x3,z0\.d,sxtw #2\]
-.*:    c4604060        prfw    pldl1keep, p0, \[x3,z0\.d,sxtw #2\]
-.*:    c46043e0        prfw    pldl1keep, p0, \[sp,z0\.d,sxtw #2\]
-.*:    c46043e0        prfw    pldl1keep, p0, \[sp,z0\.d,sxtw #2\]
-.*:    c4644000        prfw    pldl1keep, p0, \[x0,z4\.d,sxtw #2\]
-.*:    c4644000        prfw    pldl1keep, p0, \[x0,z4\.d,sxtw #2\]
-.*:    c47f4000        prfw    pldl1keep, p0, \[x0,z31\.d,sxtw #2\]
-.*:    c47f4000        prfw    pldl1keep, p0, \[x0,z31\.d,sxtw #2\]
-.*:    c460c000        prfw    pldl1keep, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c000        prfw    pldl1keep, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c001        prfw    pldl1strm, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c001        prfw    pldl1strm, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c002        prfw    pldl2keep, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c002        prfw    pldl2keep, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c003        prfw    pldl2strm, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c003        prfw    pldl2strm, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c004        prfw    pldl3keep, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c004        prfw    pldl3keep, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c005        prfw    pldl3strm, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c005        prfw    pldl3strm, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c006        prfw    #6, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c006        prfw    #6, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c007        prfw    #7, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c007        prfw    #7, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c008        prfw    pstl1keep, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c008        prfw    pstl1keep, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c009        prfw    pstl1strm, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c009        prfw    pstl1strm, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c00a        prfw    pstl2keep, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c00a        prfw    pstl2keep, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c00b        prfw    pstl2strm, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c00b        prfw    pstl2strm, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c00c        prfw    pstl3keep, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c00c        prfw    pstl3keep, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c00d        prfw    pstl3strm, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c00d        prfw    pstl3strm, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c00e        prfw    #14, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c00e        prfw    #14, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c00f        prfw    #15, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c00f        prfw    #15, p0, \[x0,z0\.d,lsl #2\]
-.*:    c460c800        prfw    pldl1keep, p2, \[x0,z0\.d,lsl #2\]
-.*:    c460c800        prfw    pldl1keep, p2, \[x0,z0\.d,lsl #2\]
-.*:    c460dc00        prfw    pldl1keep, p7, \[x0,z0\.d,lsl #2\]
-.*:    c460dc00        prfw    pldl1keep, p7, \[x0,z0\.d,lsl #2\]
-.*:    c460c060        prfw    pldl1keep, p0, \[x3,z0\.d,lsl #2\]
-.*:    c460c060        prfw    pldl1keep, p0, \[x3,z0\.d,lsl #2\]
-.*:    c460c3e0        prfw    pldl1keep, p0, \[sp,z0\.d,lsl #2\]
-.*:    c460c3e0        prfw    pldl1keep, p0, \[sp,z0\.d,lsl #2\]
-.*:    c464c000        prfw    pldl1keep, p0, \[x0,z4\.d,lsl #2\]
-.*:    c464c000        prfw    pldl1keep, p0, \[x0,z4\.d,lsl #2\]
-.*:    c47fc000        prfw    pldl1keep, p0, \[x0,z31\.d,lsl #2\]
-.*:    c47fc000        prfw    pldl1keep, p0, \[x0,z31\.d,lsl #2\]
+.*:    c48fe000        prfh    pldl1keep, p0, \[z0\.d, #30\]
+.*:    c48fe000        prfh    pldl1keep, p0, \[z0\.d, #30\]
+.*:    c490e000        prfh    pldl1keep, p0, \[z0\.d, #32\]
+.*:    c490e000        prfh    pldl1keep, p0, \[z0\.d, #32\]
+.*:    c491e000        prfh    pldl1keep, p0, \[z0\.d, #34\]
+.*:    c491e000        prfh    pldl1keep, p0, \[z0\.d, #34\]
+.*:    c49fe000        prfh    pldl1keep, p0, \[z0\.d, #62\]
+.*:    c49fe000        prfh    pldl1keep, p0, \[z0\.d, #62\]
+.*:    84204000        prfw    pldl1keep, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204000        prfw    pldl1keep, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204001        prfw    pldl1strm, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204001        prfw    pldl1strm, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204002        prfw    pldl2keep, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204002        prfw    pldl2keep, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204003        prfw    pldl2strm, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204003        prfw    pldl2strm, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204004        prfw    pldl3keep, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204004        prfw    pldl3keep, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204005        prfw    pldl3strm, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204005        prfw    pldl3strm, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204006        prfw    #6, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204006        prfw    #6, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204007        prfw    #7, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204007        prfw    #7, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204008        prfw    pstl1keep, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204008        prfw    pstl1keep, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204009        prfw    pstl1strm, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204009        prfw    pstl1strm, p0, \[x0, z0\.s, uxtw #2\]
+.*:    8420400a        prfw    pstl2keep, p0, \[x0, z0\.s, uxtw #2\]
+.*:    8420400a        prfw    pstl2keep, p0, \[x0, z0\.s, uxtw #2\]
+.*:    8420400b        prfw    pstl2strm, p0, \[x0, z0\.s, uxtw #2\]
+.*:    8420400b        prfw    pstl2strm, p0, \[x0, z0\.s, uxtw #2\]
+.*:    8420400c        prfw    pstl3keep, p0, \[x0, z0\.s, uxtw #2\]
+.*:    8420400c        prfw    pstl3keep, p0, \[x0, z0\.s, uxtw #2\]
+.*:    8420400d        prfw    pstl3strm, p0, \[x0, z0\.s, uxtw #2\]
+.*:    8420400d        prfw    pstl3strm, p0, \[x0, z0\.s, uxtw #2\]
+.*:    8420400e        prfw    #14, p0, \[x0, z0\.s, uxtw #2\]
+.*:    8420400e        prfw    #14, p0, \[x0, z0\.s, uxtw #2\]
+.*:    8420400f        prfw    #15, p0, \[x0, z0\.s, uxtw #2\]
+.*:    8420400f        prfw    #15, p0, \[x0, z0\.s, uxtw #2\]
+.*:    84204800        prfw    pldl1keep, p2, \[x0, z0\.s, uxtw #2\]
+.*:    84204800        prfw    pldl1keep, p2, \[x0, z0\.s, uxtw #2\]
+.*:    84205c00        prfw    pldl1keep, p7, \[x0, z0\.s, uxtw #2\]
+.*:    84205c00        prfw    pldl1keep, p7, \[x0, z0\.s, uxtw #2\]
+.*:    84204060        prfw    pldl1keep, p0, \[x3, z0\.s, uxtw #2\]
+.*:    84204060        prfw    pldl1keep, p0, \[x3, z0\.s, uxtw #2\]
+.*:    842043e0        prfw    pldl1keep, p0, \[sp, z0\.s, uxtw #2\]
+.*:    842043e0        prfw    pldl1keep, p0, \[sp, z0\.s, uxtw #2\]
+.*:    84244000        prfw    pldl1keep, p0, \[x0, z4\.s, uxtw #2\]
+.*:    84244000        prfw    pldl1keep, p0, \[x0, z4\.s, uxtw #2\]
+.*:    843f4000        prfw    pldl1keep, p0, \[x0, z31\.s, uxtw #2\]
+.*:    843f4000        prfw    pldl1keep, p0, \[x0, z31\.s, uxtw #2\]
+.*:    84604000        prfw    pldl1keep, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604000        prfw    pldl1keep, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604001        prfw    pldl1strm, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604001        prfw    pldl1strm, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604002        prfw    pldl2keep, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604002        prfw    pldl2keep, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604003        prfw    pldl2strm, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604003        prfw    pldl2strm, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604004        prfw    pldl3keep, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604004        prfw    pldl3keep, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604005        prfw    pldl3strm, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604005        prfw    pldl3strm, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604006        prfw    #6, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604006        prfw    #6, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604007        prfw    #7, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604007        prfw    #7, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604008        prfw    pstl1keep, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604008        prfw    pstl1keep, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604009        prfw    pstl1strm, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604009        prfw    pstl1strm, p0, \[x0, z0\.s, sxtw #2\]
+.*:    8460400a        prfw    pstl2keep, p0, \[x0, z0\.s, sxtw #2\]
+.*:    8460400a        prfw    pstl2keep, p0, \[x0, z0\.s, sxtw #2\]
+.*:    8460400b        prfw    pstl2strm, p0, \[x0, z0\.s, sxtw #2\]
+.*:    8460400b        prfw    pstl2strm, p0, \[x0, z0\.s, sxtw #2\]
+.*:    8460400c        prfw    pstl3keep, p0, \[x0, z0\.s, sxtw #2\]
+.*:    8460400c        prfw    pstl3keep, p0, \[x0, z0\.s, sxtw #2\]
+.*:    8460400d        prfw    pstl3strm, p0, \[x0, z0\.s, sxtw #2\]
+.*:    8460400d        prfw    pstl3strm, p0, \[x0, z0\.s, sxtw #2\]
+.*:    8460400e        prfw    #14, p0, \[x0, z0\.s, sxtw #2\]
+.*:    8460400e        prfw    #14, p0, \[x0, z0\.s, sxtw #2\]
+.*:    8460400f        prfw    #15, p0, \[x0, z0\.s, sxtw #2\]
+.*:    8460400f        prfw    #15, p0, \[x0, z0\.s, sxtw #2\]
+.*:    84604800        prfw    pldl1keep, p2, \[x0, z0\.s, sxtw #2\]
+.*:    84604800        prfw    pldl1keep, p2, \[x0, z0\.s, sxtw #2\]
+.*:    84605c00        prfw    pldl1keep, p7, \[x0, z0\.s, sxtw #2\]
+.*:    84605c00        prfw    pldl1keep, p7, \[x0, z0\.s, sxtw #2\]
+.*:    84604060        prfw    pldl1keep, p0, \[x3, z0\.s, sxtw #2\]
+.*:    84604060        prfw    pldl1keep, p0, \[x3, z0\.s, sxtw #2\]
+.*:    846043e0        prfw    pldl1keep, p0, \[sp, z0\.s, sxtw #2\]
+.*:    846043e0        prfw    pldl1keep, p0, \[sp, z0\.s, sxtw #2\]
+.*:    84644000        prfw    pldl1keep, p0, \[x0, z4\.s, sxtw #2\]
+.*:    84644000        prfw    pldl1keep, p0, \[x0, z4\.s, sxtw #2\]
+.*:    847f4000        prfw    pldl1keep, p0, \[x0, z31\.s, sxtw #2\]
+.*:    847f4000        prfw    pldl1keep, p0, \[x0, z31\.s, sxtw #2\]
+.*:    8500c000        prfw    pldl1keep, p0, \[x0, x0, lsl #2\]
+.*:    8500c000        prfw    pldl1keep, p0, \[x0, x0, lsl #2\]
+.*:    8500c001        prfw    pldl1strm, p0, \[x0, x0, lsl #2\]
+.*:    8500c001        prfw    pldl1strm, p0, \[x0, x0, lsl #2\]
+.*:    8500c002        prfw    pldl2keep, p0, \[x0, x0, lsl #2\]
+.*:    8500c002        prfw    pldl2keep, p0, \[x0, x0, lsl #2\]
+.*:    8500c003        prfw    pldl2strm, p0, \[x0, x0, lsl #2\]
+.*:    8500c003        prfw    pldl2strm, p0, \[x0, x0, lsl #2\]
+.*:    8500c004        prfw    pldl3keep, p0, \[x0, x0, lsl #2\]
+.*:    8500c004        prfw    pldl3keep, p0, \[x0, x0, lsl #2\]
+.*:    8500c005        prfw    pldl3strm, p0, \[x0, x0, lsl #2\]
+.*:    8500c005        prfw    pldl3strm, p0, \[x0, x0, lsl #2\]
+.*:    8500c006        prfw    #6, p0, \[x0, x0, lsl #2\]
+.*:    8500c006        prfw    #6, p0, \[x0, x0, lsl #2\]
+.*:    8500c007        prfw    #7, p0, \[x0, x0, lsl #2\]
+.*:    8500c007        prfw    #7, p0, \[x0, x0, lsl #2\]
+.*:    8500c008        prfw    pstl1keep, p0, \[x0, x0, lsl #2\]
+.*:    8500c008        prfw    pstl1keep, p0, \[x0, x0, lsl #2\]
+.*:    8500c009        prfw    pstl1strm, p0, \[x0, x0, lsl #2\]
+.*:    8500c009        prfw    pstl1strm, p0, \[x0, x0, lsl #2\]
+.*:    8500c00a        prfw    pstl2keep, p0, \[x0, x0, lsl #2\]
+.*:    8500c00a        prfw    pstl2keep, p0, \[x0, x0, lsl #2\]
+.*:    8500c00b        prfw    pstl2strm, p0, \[x0, x0, lsl #2\]
+.*:    8500c00b        prfw    pstl2strm, p0, \[x0, x0, lsl #2\]
+.*:    8500c00c        prfw    pstl3keep, p0, \[x0, x0, lsl #2\]
+.*:    8500c00c        prfw    pstl3keep, p0, \[x0, x0, lsl #2\]
+.*:    8500c00d        prfw    pstl3strm, p0, \[x0, x0, lsl #2\]
+.*:    8500c00d        prfw    pstl3strm, p0, \[x0, x0, lsl #2\]
+.*:    8500c00e        prfw    #14, p0, \[x0, x0, lsl #2\]
+.*:    8500c00e        prfw    #14, p0, \[x0, x0, lsl #2\]
+.*:    8500c00f        prfw    #15, p0, \[x0, x0, lsl #2\]
+.*:    8500c00f        prfw    #15, p0, \[x0, x0, lsl #2\]
+.*:    8500c800        prfw    pldl1keep, p2, \[x0, x0, lsl #2\]
+.*:    8500c800        prfw    pldl1keep, p2, \[x0, x0, lsl #2\]
+.*:    8500dc00        prfw    pldl1keep, p7, \[x0, x0, lsl #2\]
+.*:    8500dc00        prfw    pldl1keep, p7, \[x0, x0, lsl #2\]
+.*:    8500c060        prfw    pldl1keep, p0, \[x3, x0, lsl #2\]
+.*:    8500c060        prfw    pldl1keep, p0, \[x3, x0, lsl #2\]
+.*:    8500c3e0        prfw    pldl1keep, p0, \[sp, x0, lsl #2\]
+.*:    8500c3e0        prfw    pldl1keep, p0, \[sp, x0, lsl #2\]
+.*:    8504c000        prfw    pldl1keep, p0, \[x0, x4, lsl #2\]
+.*:    8504c000        prfw    pldl1keep, p0, \[x0, x4, lsl #2\]
+.*:    851ec000        prfw    pldl1keep, p0, \[x0, x30, lsl #2\]
+.*:    851ec000        prfw    pldl1keep, p0, \[x0, x30, lsl #2\]
+.*:    c4204000        prfw    pldl1keep, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204000        prfw    pldl1keep, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204001        prfw    pldl1strm, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204001        prfw    pldl1strm, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204002        prfw    pldl2keep, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204002        prfw    pldl2keep, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204003        prfw    pldl2strm, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204003        prfw    pldl2strm, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204004        prfw    pldl3keep, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204004        prfw    pldl3keep, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204005        prfw    pldl3strm, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204005        prfw    pldl3strm, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204006        prfw    #6, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204006        prfw    #6, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204007        prfw    #7, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204007        prfw    #7, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204008        prfw    pstl1keep, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204008        prfw    pstl1keep, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204009        prfw    pstl1strm, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204009        prfw    pstl1strm, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c420400a        prfw    pstl2keep, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c420400a        prfw    pstl2keep, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c420400b        prfw    pstl2strm, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c420400b        prfw    pstl2strm, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c420400c        prfw    pstl3keep, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c420400c        prfw    pstl3keep, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c420400d        prfw    pstl3strm, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c420400d        prfw    pstl3strm, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c420400e        prfw    #14, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c420400e        prfw    #14, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c420400f        prfw    #15, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c420400f        prfw    #15, p0, \[x0, z0\.d, uxtw #2\]
+.*:    c4204800        prfw    pldl1keep, p2, \[x0, z0\.d, uxtw #2\]
+.*:    c4204800        prfw    pldl1keep, p2, \[x0, z0\.d, uxtw #2\]
+.*:    c4205c00        prfw    pldl1keep, p7, \[x0, z0\.d, uxtw #2\]
+.*:    c4205c00        prfw    pldl1keep, p7, \[x0, z0\.d, uxtw #2\]
+.*:    c4204060        prfw    pldl1keep, p0, \[x3, z0\.d, uxtw #2\]
+.*:    c4204060        prfw    pldl1keep, p0, \[x3, z0\.d, uxtw #2\]
+.*:    c42043e0        prfw    pldl1keep, p0, \[sp, z0\.d, uxtw #2\]
+.*:    c42043e0        prfw    pldl1keep, p0, \[sp, z0\.d, uxtw #2\]
+.*:    c4244000        prfw    pldl1keep, p0, \[x0, z4\.d, uxtw #2\]
+.*:    c4244000        prfw    pldl1keep, p0, \[x0, z4\.d, uxtw #2\]
+.*:    c43f4000        prfw    pldl1keep, p0, \[x0, z31\.d, uxtw #2\]
+.*:    c43f4000        prfw    pldl1keep, p0, \[x0, z31\.d, uxtw #2\]
+.*:    c4604000        prfw    pldl1keep, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604000        prfw    pldl1keep, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604001        prfw    pldl1strm, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604001        prfw    pldl1strm, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604002        prfw    pldl2keep, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604002        prfw    pldl2keep, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604003        prfw    pldl2strm, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604003        prfw    pldl2strm, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604004        prfw    pldl3keep, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604004        prfw    pldl3keep, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604005        prfw    pldl3strm, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604005        prfw    pldl3strm, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604006        prfw    #6, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604006        prfw    #6, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604007        prfw    #7, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604007        prfw    #7, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604008        prfw    pstl1keep, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604008        prfw    pstl1keep, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604009        prfw    pstl1strm, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604009        prfw    pstl1strm, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c460400a        prfw    pstl2keep, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c460400a        prfw    pstl2keep, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c460400b        prfw    pstl2strm, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c460400b        prfw    pstl2strm, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c460400c        prfw    pstl3keep, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c460400c        prfw    pstl3keep, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c460400d        prfw    pstl3strm, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c460400d        prfw    pstl3strm, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c460400e        prfw    #14, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c460400e        prfw    #14, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c460400f        prfw    #15, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c460400f        prfw    #15, p0, \[x0, z0\.d, sxtw #2\]
+.*:    c4604800        prfw    pldl1keep, p2, \[x0, z0\.d, sxtw #2\]
+.*:    c4604800        prfw    pldl1keep, p2, \[x0, z0\.d, sxtw #2\]
+.*:    c4605c00        prfw    pldl1keep, p7, \[x0, z0\.d, sxtw #2\]
+.*:    c4605c00        prfw    pldl1keep, p7, \[x0, z0\.d, sxtw #2\]
+.*:    c4604060        prfw    pldl1keep, p0, \[x3, z0\.d, sxtw #2\]
+.*:    c4604060        prfw    pldl1keep, p0, \[x3, z0\.d, sxtw #2\]
+.*:    c46043e0        prfw    pldl1keep, p0, \[sp, z0\.d, sxtw #2\]
+.*:    c46043e0        prfw    pldl1keep, p0, \[sp, z0\.d, sxtw #2\]
+.*:    c4644000        prfw    pldl1keep, p0, \[x0, z4\.d, sxtw #2\]
+.*:    c4644000        prfw    pldl1keep, p0, \[x0, z4\.d, sxtw #2\]
+.*:    c47f4000        prfw    pldl1keep, p0, \[x0, z31\.d, sxtw #2\]
+.*:    c47f4000        prfw    pldl1keep, p0, \[x0, z31\.d, sxtw #2\]
+.*:    c460c000        prfw    pldl1keep, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c000        prfw    pldl1keep, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c001        prfw    pldl1strm, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c001        prfw    pldl1strm, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c002        prfw    pldl2keep, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c002        prfw    pldl2keep, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c003        prfw    pldl2strm, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c003        prfw    pldl2strm, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c004        prfw    pldl3keep, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c004        prfw    pldl3keep, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c005        prfw    pldl3strm, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c005        prfw    pldl3strm, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c006        prfw    #6, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c006        prfw    #6, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c007        prfw    #7, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c007        prfw    #7, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c008        prfw    pstl1keep, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c008        prfw    pstl1keep, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c009        prfw    pstl1strm, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c009        prfw    pstl1strm, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c00a        prfw    pstl2keep, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c00a        prfw    pstl2keep, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c00b        prfw    pstl2strm, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c00b        prfw    pstl2strm, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c00c        prfw    pstl3keep, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c00c        prfw    pstl3keep, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c00d        prfw    pstl3strm, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c00d        prfw    pstl3strm, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c00e        prfw    #14, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c00e        prfw    #14, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c00f        prfw    #15, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c00f        prfw    #15, p0, \[x0, z0\.d, lsl #2\]
+.*:    c460c800        prfw    pldl1keep, p2, \[x0, z0\.d, lsl #2\]
+.*:    c460c800        prfw    pldl1keep, p2, \[x0, z0\.d, lsl #2\]
+.*:    c460dc00        prfw    pldl1keep, p7, \[x0, z0\.d, lsl #2\]
+.*:    c460dc00        prfw    pldl1keep, p7, \[x0, z0\.d, lsl #2\]
+.*:    c460c060        prfw    pldl1keep, p0, \[x3, z0\.d, lsl #2\]
+.*:    c460c060        prfw    pldl1keep, p0, \[x3, z0\.d, lsl #2\]
+.*:    c460c3e0        prfw    pldl1keep, p0, \[sp, z0\.d, lsl #2\]
+.*:    c460c3e0        prfw    pldl1keep, p0, \[sp, z0\.d, lsl #2\]
+.*:    c464c000        prfw    pldl1keep, p0, \[x0, z4\.d, lsl #2\]
+.*:    c464c000        prfw    pldl1keep, p0, \[x0, z4\.d, lsl #2\]
+.*:    c47fc000        prfw    pldl1keep, p0, \[x0, z31\.d, lsl #2\]
+.*:    c47fc000        prfw    pldl1keep, p0, \[x0, z31\.d, lsl #2\]
 .*:    8500e000        prfw    pldl1keep, p0, \[z0\.s\]
 .*:    8500e000        prfw    pldl1keep, p0, \[z0\.s\]
 .*:    8500e000        prfw    pldl1keep, p0, \[z0\.s\]
@@ -23906,14 +23906,14 @@ Disassembly of section .*:
 .*:    8500e3e0        prfw    pldl1keep, p0, \[z31\.s\]
 .*:    8500e3e0        prfw    pldl1keep, p0, \[z31\.s\]
 .*:    8500e3e0        prfw    pldl1keep, p0, \[z31\.s\]
-.*:    850fe000        prfw    pldl1keep, p0, \[z0\.s,#60\]
-.*:    850fe000        prfw    pldl1keep, p0, \[z0\.s,#60\]
-.*:    8510e000        prfw    pldl1keep, p0, \[z0\.s,#64\]
-.*:    8510e000        prfw    pldl1keep, p0, \[z0\.s,#64\]
-.*:    8511e000        prfw    pldl1keep, p0, \[z0\.s,#68\]
-.*:    8511e000        prfw    pldl1keep, p0, \[z0\.s,#68\]
-.*:    851fe000        prfw    pldl1keep, p0, \[z0\.s,#124\]
-.*:    851fe000        prfw    pldl1keep, p0, \[z0\.s,#124\]
+.*:    850fe000        prfw    pldl1keep, p0, \[z0\.s, #60\]
+.*:    850fe000        prfw    pldl1keep, p0, \[z0\.s, #60\]
+.*:    8510e000        prfw    pldl1keep, p0, \[z0\.s, #64\]
+.*:    8510e000        prfw    pldl1keep, p0, \[z0\.s, #64\]
+.*:    8511e000        prfw    pldl1keep, p0, \[z0\.s, #68\]
+.*:    8511e000        prfw    pldl1keep, p0, \[z0\.s, #68\]
+.*:    851fe000        prfw    pldl1keep, p0, \[z0\.s, #124\]
+.*:    851fe000        prfw    pldl1keep, p0, \[z0\.s, #124\]
 .*:    85c04000        prfw    pldl1keep, p0, \[x0\]
 .*:    85c04000        prfw    pldl1keep, p0, \[x0\]
 .*:    85c04000        prfw    pldl1keep, p0, \[x0\]
@@ -23994,14 +23994,14 @@ Disassembly of section .*:
 .*:    85c043e0        prfw    pldl1keep, p0, \[sp\]
 .*:    85c043e0        prfw    pldl1keep, p0, \[sp\]
 .*:    85c043e0        prfw    pldl1keep, p0, \[sp\]
-.*:    85df4000        prfw    pldl1keep, p0, \[x0,#31,mul vl\]
-.*:    85df4000        prfw    pldl1keep, p0, \[x0,#31,mul vl\]
-.*:    85e04000        prfw    pldl1keep, p0, \[x0,#-32,mul vl\]
-.*:    85e04000        prfw    pldl1keep, p0, \[x0,#-32,mul vl\]
-.*:    85e14000        prfw    pldl1keep, p0, \[x0,#-31,mul vl\]
-.*:    85e14000        prfw    pldl1keep, p0, \[x0,#-31,mul vl\]
-.*:    85ff4000        prfw    pldl1keep, p0, \[x0,#-1,mul vl\]
-.*:    85ff4000        prfw    pldl1keep, p0, \[x0,#-1,mul vl\]
+.*:    85df4000        prfw    pldl1keep, p0, \[x0, #31, mul vl\]
+.*:    85df4000        prfw    pldl1keep, p0, \[x0, #31, mul vl\]
+.*:    85e04000        prfw    pldl1keep, p0, \[x0, #-32, mul vl\]
+.*:    85e04000        prfw    pldl1keep, p0, \[x0, #-32, mul vl\]
+.*:    85e14000        prfw    pldl1keep, p0, \[x0, #-31, mul vl\]
+.*:    85e14000        prfw    pldl1keep, p0, \[x0, #-31, mul vl\]
+.*:    85ff4000        prfw    pldl1keep, p0, \[x0, #-1, mul vl\]
+.*:    85ff4000        prfw    pldl1keep, p0, \[x0, #-1, mul vl\]
 .*:    c500e000        prfw    pldl1keep, p0, \[z0\.d\]
 .*:    c500e000        prfw    pldl1keep, p0, \[z0\.d\]
 .*:    c500e000        prfw    pldl1keep, p0, \[z0\.d\]
@@ -24062,14 +24062,14 @@ Disassembly of section .*:
 .*:    c500e3e0        prfw    pldl1keep, p0, \[z31\.d\]
 .*:    c500e3e0        prfw    pldl1keep, p0, \[z31\.d\]
 .*:    c500e3e0        prfw    pldl1keep, p0, \[z31\.d\]
-.*:    c50fe000        prfw    pldl1keep, p0, \[z0\.d,#60\]
-.*:    c50fe000        prfw    pldl1keep, p0, \[z0\.d,#60\]
-.*:    c510e000        prfw    pldl1keep, p0, \[z0\.d,#64\]
-.*:    c510e000        prfw    pldl1keep, p0, \[z0\.d,#64\]
-.*:    c511e000        prfw    pldl1keep, p0, \[z0\.d,#68\]
-.*:    c511e000        prfw    pldl1keep, p0, \[z0\.d,#68\]
-.*:    c51fe000        prfw    pldl1keep, p0, \[z0\.d,#124\]
-.*:    c51fe000        prfw    pldl1keep, p0, \[z0\.d,#124\]
+.*:    c50fe000        prfw    pldl1keep, p0, \[z0\.d, #60\]
+.*:    c50fe000        prfw    pldl1keep, p0, \[z0\.d, #60\]
+.*:    c510e000        prfw    pldl1keep, p0, \[z0\.d, #64\]
+.*:    c510e000        prfw    pldl1keep, p0, \[z0\.d, #64\]
+.*:    c511e000        prfw    pldl1keep, p0, \[z0\.d, #68\]
+.*:    c511e000        prfw    pldl1keep, p0, \[z0\.d, #68\]
+.*:    c51fe000        prfw    pldl1keep, p0, \[z0\.d, #124\]
+.*:    c51fe000        prfw    pldl1keep, p0, \[z0\.d, #124\]
 .*:    2550c000        ptest   p0, p0\.b
 .*:    2550c000        ptest   p0, p0\.b
 .*:    2550c400        ptest   p1, p0\.b
@@ -28840,276 +28840,276 @@ Disassembly of section .*:
 .*:    25e6ffe0        sqsub   z0\.d, z0\.d, #65280
 .*:    25e6ffe0        sqsub   z0\.d, z0\.d, #65280
 .*:    25e6ffe0        sqsub   z0\.d, z0\.d, #65280
-.*:    e4004000        st1b    \{z0\.b\}, p0, \[x0,x0\]
-.*:    e4004000        st1b    \{z0\.b\}, p0, \[x0,x0\]
-.*:    e4004000        st1b    \{z0\.b\}, p0, \[x0,x0\]
-.*:    e4004000        st1b    \{z0\.b\}, p0, \[x0,x0\]
-.*:    e4004001        st1b    \{z1\.b\}, p0, \[x0,x0\]
-.*:    e4004001        st1b    \{z1\.b\}, p0, \[x0,x0\]
-.*:    e4004001        st1b    \{z1\.b\}, p0, \[x0,x0\]
-.*:    e4004001        st1b    \{z1\.b\}, p0, \[x0,x0\]
-.*:    e400401f        st1b    \{z31\.b\}, p0, \[x0,x0\]
-.*:    e400401f        st1b    \{z31\.b\}, p0, \[x0,x0\]
-.*:    e400401f        st1b    \{z31\.b\}, p0, \[x0,x0\]
-.*:    e400401f        st1b    \{z31\.b\}, p0, \[x0,x0\]
-.*:    e4004800        st1b    \{z0\.b\}, p2, \[x0,x0\]
-.*:    e4004800        st1b    \{z0\.b\}, p2, \[x0,x0\]
-.*:    e4004800        st1b    \{z0\.b\}, p2, \[x0,x0\]
-.*:    e4005c00        st1b    \{z0\.b\}, p7, \[x0,x0\]
-.*:    e4005c00        st1b    \{z0\.b\}, p7, \[x0,x0\]
-.*:    e4005c00        st1b    \{z0\.b\}, p7, \[x0,x0\]
-.*:    e4004060        st1b    \{z0\.b\}, p0, \[x3,x0\]
-.*:    e4004060        st1b    \{z0\.b\}, p0, \[x3,x0\]
-.*:    e4004060        st1b    \{z0\.b\}, p0, \[x3,x0\]
-.*:    e40043e0        st1b    \{z0\.b\}, p0, \[sp,x0\]
-.*:    e40043e0        st1b    \{z0\.b\}, p0, \[sp,x0\]
-.*:    e40043e0        st1b    \{z0\.b\}, p0, \[sp,x0\]
-.*:    e4044000        st1b    \{z0\.b\}, p0, \[x0,x4\]
-.*:    e4044000        st1b    \{z0\.b\}, p0, \[x0,x4\]
-.*:    e4044000        st1b    \{z0\.b\}, p0, \[x0,x4\]
-.*:    e41e4000        st1b    \{z0\.b\}, p0, \[x0,x30\]
-.*:    e41e4000        st1b    \{z0\.b\}, p0, \[x0,x30\]
-.*:    e41e4000        st1b    \{z0\.b\}, p0, \[x0,x30\]
-.*:    e4008000        st1b    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4008000        st1b    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4008000        st1b    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4008000        st1b    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4008001        st1b    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4008001        st1b    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4008001        st1b    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4008001        st1b    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e400801f        st1b    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e400801f        st1b    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e400801f        st1b    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e400801f        st1b    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4008800        st1b    \{z0\.d\}, p2, \[x0,z0\.d,uxtw\]
-.*:    e4008800        st1b    \{z0\.d\}, p2, \[x0,z0\.d,uxtw\]
-.*:    e4008800        st1b    \{z0\.d\}, p2, \[x0,z0\.d,uxtw\]
-.*:    e4009c00        st1b    \{z0\.d\}, p7, \[x0,z0\.d,uxtw\]
-.*:    e4009c00        st1b    \{z0\.d\}, p7, \[x0,z0\.d,uxtw\]
-.*:    e4009c00        st1b    \{z0\.d\}, p7, \[x0,z0\.d,uxtw\]
-.*:    e4008060        st1b    \{z0\.d\}, p0, \[x3,z0\.d,uxtw\]
-.*:    e4008060        st1b    \{z0\.d\}, p0, \[x3,z0\.d,uxtw\]
-.*:    e4008060        st1b    \{z0\.d\}, p0, \[x3,z0\.d,uxtw\]
-.*:    e40083e0        st1b    \{z0\.d\}, p0, \[sp,z0\.d,uxtw\]
-.*:    e40083e0        st1b    \{z0\.d\}, p0, \[sp,z0\.d,uxtw\]
-.*:    e40083e0        st1b    \{z0\.d\}, p0, \[sp,z0\.d,uxtw\]
-.*:    e4048000        st1b    \{z0\.d\}, p0, \[x0,z4\.d,uxtw\]
-.*:    e4048000        st1b    \{z0\.d\}, p0, \[x0,z4\.d,uxtw\]
-.*:    e4048000        st1b    \{z0\.d\}, p0, \[x0,z4\.d,uxtw\]
-.*:    e41f8000        st1b    \{z0\.d\}, p0, \[x0,z31\.d,uxtw\]
-.*:    e41f8000        st1b    \{z0\.d\}, p0, \[x0,z31\.d,uxtw\]
-.*:    e41f8000        st1b    \{z0\.d\}, p0, \[x0,z31\.d,uxtw\]
-.*:    e400c000        st1b    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e400c000        st1b    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e400c000        st1b    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e400c000        st1b    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e400c001        st1b    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e400c001        st1b    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e400c001        st1b    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e400c001        st1b    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e400c01f        st1b    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e400c01f        st1b    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e400c01f        st1b    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e400c01f        st1b    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e400c800        st1b    \{z0\.d\}, p2, \[x0,z0\.d,sxtw\]
-.*:    e400c800        st1b    \{z0\.d\}, p2, \[x0,z0\.d,sxtw\]
-.*:    e400c800        st1b    \{z0\.d\}, p2, \[x0,z0\.d,sxtw\]
-.*:    e400dc00        st1b    \{z0\.d\}, p7, \[x0,z0\.d,sxtw\]
-.*:    e400dc00        st1b    \{z0\.d\}, p7, \[x0,z0\.d,sxtw\]
-.*:    e400dc00        st1b    \{z0\.d\}, p7, \[x0,z0\.d,sxtw\]
-.*:    e400c060        st1b    \{z0\.d\}, p0, \[x3,z0\.d,sxtw\]
-.*:    e400c060        st1b    \{z0\.d\}, p0, \[x3,z0\.d,sxtw\]
-.*:    e400c060        st1b    \{z0\.d\}, p0, \[x3,z0\.d,sxtw\]
-.*:    e400c3e0        st1b    \{z0\.d\}, p0, \[sp,z0\.d,sxtw\]
-.*:    e400c3e0        st1b    \{z0\.d\}, p0, \[sp,z0\.d,sxtw\]
-.*:    e400c3e0        st1b    \{z0\.d\}, p0, \[sp,z0\.d,sxtw\]
-.*:    e404c000        st1b    \{z0\.d\}, p0, \[x0,z4\.d,sxtw\]
-.*:    e404c000        st1b    \{z0\.d\}, p0, \[x0,z4\.d,sxtw\]
-.*:    e404c000        st1b    \{z0\.d\}, p0, \[x0,z4\.d,sxtw\]
-.*:    e41fc000        st1b    \{z0\.d\}, p0, \[x0,z31\.d,sxtw\]
-.*:    e41fc000        st1b    \{z0\.d\}, p0, \[x0,z31\.d,sxtw\]
-.*:    e41fc000        st1b    \{z0\.d\}, p0, \[x0,z31\.d,sxtw\]
-.*:    e400a000        st1b    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e400a000        st1b    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e400a000        st1b    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e400a000        st1b    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e400a001        st1b    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e400a001        st1b    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e400a001        st1b    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e400a001        st1b    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e400a01f        st1b    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e400a01f        st1b    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e400a01f        st1b    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e400a01f        st1b    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e400a800        st1b    \{z0\.d\}, p2, \[x0,z0\.d\]
-.*:    e400a800        st1b    \{z0\.d\}, p2, \[x0,z0\.d\]
-.*:    e400a800        st1b    \{z0\.d\}, p2, \[x0,z0\.d\]
-.*:    e400bc00        st1b    \{z0\.d\}, p7, \[x0,z0\.d\]
-.*:    e400bc00        st1b    \{z0\.d\}, p7, \[x0,z0\.d\]
-.*:    e400bc00        st1b    \{z0\.d\}, p7, \[x0,z0\.d\]
-.*:    e400a060        st1b    \{z0\.d\}, p0, \[x3,z0\.d\]
-.*:    e400a060        st1b    \{z0\.d\}, p0, \[x3,z0\.d\]
-.*:    e400a060        st1b    \{z0\.d\}, p0, \[x3,z0\.d\]
-.*:    e400a3e0        st1b    \{z0\.d\}, p0, \[sp,z0\.d\]
-.*:    e400a3e0        st1b    \{z0\.d\}, p0, \[sp,z0\.d\]
-.*:    e400a3e0        st1b    \{z0\.d\}, p0, \[sp,z0\.d\]
-.*:    e404a000        st1b    \{z0\.d\}, p0, \[x0,z4\.d\]
-.*:    e404a000        st1b    \{z0\.d\}, p0, \[x0,z4\.d\]
-.*:    e404a000        st1b    \{z0\.d\}, p0, \[x0,z4\.d\]
-.*:    e41fa000        st1b    \{z0\.d\}, p0, \[x0,z31\.d\]
-.*:    e41fa000        st1b    \{z0\.d\}, p0, \[x0,z31\.d\]
-.*:    e41fa000        st1b    \{z0\.d\}, p0, \[x0,z31\.d\]
-.*:    e4204000        st1b    \{z0\.h\}, p0, \[x0,x0\]
-.*:    e4204000        st1b    \{z0\.h\}, p0, \[x0,x0\]
-.*:    e4204000        st1b    \{z0\.h\}, p0, \[x0,x0\]
-.*:    e4204000        st1b    \{z0\.h\}, p0, \[x0,x0\]
-.*:    e4204001        st1b    \{z1\.h\}, p0, \[x0,x0\]
-.*:    e4204001        st1b    \{z1\.h\}, p0, \[x0,x0\]
-.*:    e4204001        st1b    \{z1\.h\}, p0, \[x0,x0\]
-.*:    e4204001        st1b    \{z1\.h\}, p0, \[x0,x0\]
-.*:    e420401f        st1b    \{z31\.h\}, p0, \[x0,x0\]
-.*:    e420401f        st1b    \{z31\.h\}, p0, \[x0,x0\]
-.*:    e420401f        st1b    \{z31\.h\}, p0, \[x0,x0\]
-.*:    e420401f        st1b    \{z31\.h\}, p0, \[x0,x0\]
-.*:    e4204800        st1b    \{z0\.h\}, p2, \[x0,x0\]
-.*:    e4204800        st1b    \{z0\.h\}, p2, \[x0,x0\]
-.*:    e4204800        st1b    \{z0\.h\}, p2, \[x0,x0\]
-.*:    e4205c00        st1b    \{z0\.h\}, p7, \[x0,x0\]
-.*:    e4205c00        st1b    \{z0\.h\}, p7, \[x0,x0\]
-.*:    e4205c00        st1b    \{z0\.h\}, p7, \[x0,x0\]
-.*:    e4204060        st1b    \{z0\.h\}, p0, \[x3,x0\]
-.*:    e4204060        st1b    \{z0\.h\}, p0, \[x3,x0\]
-.*:    e4204060        st1b    \{z0\.h\}, p0, \[x3,x0\]
-.*:    e42043e0        st1b    \{z0\.h\}, p0, \[sp,x0\]
-.*:    e42043e0        st1b    \{z0\.h\}, p0, \[sp,x0\]
-.*:    e42043e0        st1b    \{z0\.h\}, p0, \[sp,x0\]
-.*:    e4244000        st1b    \{z0\.h\}, p0, \[x0,x4\]
-.*:    e4244000        st1b    \{z0\.h\}, p0, \[x0,x4\]
-.*:    e4244000        st1b    \{z0\.h\}, p0, \[x0,x4\]
-.*:    e43e4000        st1b    \{z0\.h\}, p0, \[x0,x30\]
-.*:    e43e4000        st1b    \{z0\.h\}, p0, \[x0,x30\]
-.*:    e43e4000        st1b    \{z0\.h\}, p0, \[x0,x30\]
-.*:    e4404000        st1b    \{z0\.s\}, p0, \[x0,x0\]
-.*:    e4404000        st1b    \{z0\.s\}, p0, \[x0,x0\]
-.*:    e4404000        st1b    \{z0\.s\}, p0, \[x0,x0\]
-.*:    e4404000        st1b    \{z0\.s\}, p0, \[x0,x0\]
-.*:    e4404001        st1b    \{z1\.s\}, p0, \[x0,x0\]
-.*:    e4404001        st1b    \{z1\.s\}, p0, \[x0,x0\]
-.*:    e4404001        st1b    \{z1\.s\}, p0, \[x0,x0\]
-.*:    e4404001        st1b    \{z1\.s\}, p0, \[x0,x0\]
-.*:    e440401f        st1b    \{z31\.s\}, p0, \[x0,x0\]
-.*:    e440401f        st1b    \{z31\.s\}, p0, \[x0,x0\]
-.*:    e440401f        st1b    \{z31\.s\}, p0, \[x0,x0\]
-.*:    e440401f        st1b    \{z31\.s\}, p0, \[x0,x0\]
-.*:    e4404800        st1b    \{z0\.s\}, p2, \[x0,x0\]
-.*:    e4404800        st1b    \{z0\.s\}, p2, \[x0,x0\]
-.*:    e4404800        st1b    \{z0\.s\}, p2, \[x0,x0\]
-.*:    e4405c00        st1b    \{z0\.s\}, p7, \[x0,x0\]
-.*:    e4405c00        st1b    \{z0\.s\}, p7, \[x0,x0\]
-.*:    e4405c00        st1b    \{z0\.s\}, p7, \[x0,x0\]
-.*:    e4404060        st1b    \{z0\.s\}, p0, \[x3,x0\]
-.*:    e4404060        st1b    \{z0\.s\}, p0, \[x3,x0\]
-.*:    e4404060        st1b    \{z0\.s\}, p0, \[x3,x0\]
-.*:    e44043e0        st1b    \{z0\.s\}, p0, \[sp,x0\]
-.*:    e44043e0        st1b    \{z0\.s\}, p0, \[sp,x0\]
-.*:    e44043e0        st1b    \{z0\.s\}, p0, \[sp,x0\]
-.*:    e4444000        st1b    \{z0\.s\}, p0, \[x0,x4\]
-.*:    e4444000        st1b    \{z0\.s\}, p0, \[x0,x4\]
-.*:    e4444000        st1b    \{z0\.s\}, p0, \[x0,x4\]
-.*:    e45e4000        st1b    \{z0\.s\}, p0, \[x0,x30\]
-.*:    e45e4000        st1b    \{z0\.s\}, p0, \[x0,x30\]
-.*:    e45e4000        st1b    \{z0\.s\}, p0, \[x0,x30\]
-.*:    e4408000        st1b    \{z0\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4408000        st1b    \{z0\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4408000        st1b    \{z0\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4408000        st1b    \{z0\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4408001        st1b    \{z1\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4408001        st1b    \{z1\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4408001        st1b    \{z1\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4408001        st1b    \{z1\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e440801f        st1b    \{z31\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e440801f        st1b    \{z31\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e440801f        st1b    \{z31\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e440801f        st1b    \{z31\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4408800        st1b    \{z0\.s\}, p2, \[x0,z0\.s,uxtw\]
-.*:    e4408800        st1b    \{z0\.s\}, p2, \[x0,z0\.s,uxtw\]
-.*:    e4408800        st1b    \{z0\.s\}, p2, \[x0,z0\.s,uxtw\]
-.*:    e4409c00        st1b    \{z0\.s\}, p7, \[x0,z0\.s,uxtw\]
-.*:    e4409c00        st1b    \{z0\.s\}, p7, \[x0,z0\.s,uxtw\]
-.*:    e4409c00        st1b    \{z0\.s\}, p7, \[x0,z0\.s,uxtw\]
-.*:    e4408060        st1b    \{z0\.s\}, p0, \[x3,z0\.s,uxtw\]
-.*:    e4408060        st1b    \{z0\.s\}, p0, \[x3,z0\.s,uxtw\]
-.*:    e4408060        st1b    \{z0\.s\}, p0, \[x3,z0\.s,uxtw\]
-.*:    e44083e0        st1b    \{z0\.s\}, p0, \[sp,z0\.s,uxtw\]
-.*:    e44083e0        st1b    \{z0\.s\}, p0, \[sp,z0\.s,uxtw\]
-.*:    e44083e0        st1b    \{z0\.s\}, p0, \[sp,z0\.s,uxtw\]
-.*:    e4448000        st1b    \{z0\.s\}, p0, \[x0,z4\.s,uxtw\]
-.*:    e4448000        st1b    \{z0\.s\}, p0, \[x0,z4\.s,uxtw\]
-.*:    e4448000        st1b    \{z0\.s\}, p0, \[x0,z4\.s,uxtw\]
-.*:    e45f8000        st1b    \{z0\.s\}, p0, \[x0,z31\.s,uxtw\]
-.*:    e45f8000        st1b    \{z0\.s\}, p0, \[x0,z31\.s,uxtw\]
-.*:    e45f8000        st1b    \{z0\.s\}, p0, \[x0,z31\.s,uxtw\]
-.*:    e440c000        st1b    \{z0\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e440c000        st1b    \{z0\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e440c000        st1b    \{z0\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e440c000        st1b    \{z0\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e440c001        st1b    \{z1\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e440c001        st1b    \{z1\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e440c001        st1b    \{z1\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e440c001        st1b    \{z1\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e440c01f        st1b    \{z31\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e440c01f        st1b    \{z31\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e440c01f        st1b    \{z31\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e440c01f        st1b    \{z31\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e440c800        st1b    \{z0\.s\}, p2, \[x0,z0\.s,sxtw\]
-.*:    e440c800        st1b    \{z0\.s\}, p2, \[x0,z0\.s,sxtw\]
-.*:    e440c800        st1b    \{z0\.s\}, p2, \[x0,z0\.s,sxtw\]
-.*:    e440dc00        st1b    \{z0\.s\}, p7, \[x0,z0\.s,sxtw\]
-.*:    e440dc00        st1b    \{z0\.s\}, p7, \[x0,z0\.s,sxtw\]
-.*:    e440dc00        st1b    \{z0\.s\}, p7, \[x0,z0\.s,sxtw\]
-.*:    e440c060        st1b    \{z0\.s\}, p0, \[x3,z0\.s,sxtw\]
-.*:    e440c060        st1b    \{z0\.s\}, p0, \[x3,z0\.s,sxtw\]
-.*:    e440c060        st1b    \{z0\.s\}, p0, \[x3,z0\.s,sxtw\]
-.*:    e440c3e0        st1b    \{z0\.s\}, p0, \[sp,z0\.s,sxtw\]
-.*:    e440c3e0        st1b    \{z0\.s\}, p0, \[sp,z0\.s,sxtw\]
-.*:    e440c3e0        st1b    \{z0\.s\}, p0, \[sp,z0\.s,sxtw\]
-.*:    e444c000        st1b    \{z0\.s\}, p0, \[x0,z4\.s,sxtw\]
-.*:    e444c000        st1b    \{z0\.s\}, p0, \[x0,z4\.s,sxtw\]
-.*:    e444c000        st1b    \{z0\.s\}, p0, \[x0,z4\.s,sxtw\]
-.*:    e45fc000        st1b    \{z0\.s\}, p0, \[x0,z31\.s,sxtw\]
-.*:    e45fc000        st1b    \{z0\.s\}, p0, \[x0,z31\.s,sxtw\]
-.*:    e45fc000        st1b    \{z0\.s\}, p0, \[x0,z31\.s,sxtw\]
-.*:    e4604000        st1b    \{z0\.d\}, p0, \[x0,x0\]
-.*:    e4604000        st1b    \{z0\.d\}, p0, \[x0,x0\]
-.*:    e4604000        st1b    \{z0\.d\}, p0, \[x0,x0\]
-.*:    e4604000        st1b    \{z0\.d\}, p0, \[x0,x0\]
-.*:    e4604001        st1b    \{z1\.d\}, p0, \[x0,x0\]
-.*:    e4604001        st1b    \{z1\.d\}, p0, \[x0,x0\]
-.*:    e4604001        st1b    \{z1\.d\}, p0, \[x0,x0\]
-.*:    e4604001        st1b    \{z1\.d\}, p0, \[x0,x0\]
-.*:    e460401f        st1b    \{z31\.d\}, p0, \[x0,x0\]
-.*:    e460401f        st1b    \{z31\.d\}, p0, \[x0,x0\]
-.*:    e460401f        st1b    \{z31\.d\}, p0, \[x0,x0\]
-.*:    e460401f        st1b    \{z31\.d\}, p0, \[x0,x0\]
-.*:    e4604800        st1b    \{z0\.d\}, p2, \[x0,x0\]
-.*:    e4604800        st1b    \{z0\.d\}, p2, \[x0,x0\]
-.*:    e4604800        st1b    \{z0\.d\}, p2, \[x0,x0\]
-.*:    e4605c00        st1b    \{z0\.d\}, p7, \[x0,x0\]
-.*:    e4605c00        st1b    \{z0\.d\}, p7, \[x0,x0\]
-.*:    e4605c00        st1b    \{z0\.d\}, p7, \[x0,x0\]
-.*:    e4604060        st1b    \{z0\.d\}, p0, \[x3,x0\]
-.*:    e4604060        st1b    \{z0\.d\}, p0, \[x3,x0\]
-.*:    e4604060        st1b    \{z0\.d\}, p0, \[x3,x0\]
-.*:    e46043e0        st1b    \{z0\.d\}, p0, \[sp,x0\]
-.*:    e46043e0        st1b    \{z0\.d\}, p0, \[sp,x0\]
-.*:    e46043e0        st1b    \{z0\.d\}, p0, \[sp,x0\]
-.*:    e4644000        st1b    \{z0\.d\}, p0, \[x0,x4\]
-.*:    e4644000        st1b    \{z0\.d\}, p0, \[x0,x4\]
-.*:    e4644000        st1b    \{z0\.d\}, p0, \[x0,x4\]
-.*:    e47e4000        st1b    \{z0\.d\}, p0, \[x0,x30\]
-.*:    e47e4000        st1b    \{z0\.d\}, p0, \[x0,x30\]
-.*:    e47e4000        st1b    \{z0\.d\}, p0, \[x0,x30\]
+.*:    e4004000        st1b    \{z0\.b\}, p0, \[x0, x0\]
+.*:    e4004000        st1b    \{z0\.b\}, p0, \[x0, x0\]
+.*:    e4004000        st1b    \{z0\.b\}, p0, \[x0, x0\]
+.*:    e4004000        st1b    \{z0\.b\}, p0, \[x0, x0\]
+.*:    e4004001        st1b    \{z1\.b\}, p0, \[x0, x0\]
+.*:    e4004001        st1b    \{z1\.b\}, p0, \[x0, x0\]
+.*:    e4004001        st1b    \{z1\.b\}, p0, \[x0, x0\]
+.*:    e4004001        st1b    \{z1\.b\}, p0, \[x0, x0\]
+.*:    e400401f        st1b    \{z31\.b\}, p0, \[x0, x0\]
+.*:    e400401f        st1b    \{z31\.b\}, p0, \[x0, x0\]
+.*:    e400401f        st1b    \{z31\.b\}, p0, \[x0, x0\]
+.*:    e400401f        st1b    \{z31\.b\}, p0, \[x0, x0\]
+.*:    e4004800        st1b    \{z0\.b\}, p2, \[x0, x0\]
+.*:    e4004800        st1b    \{z0\.b\}, p2, \[x0, x0\]
+.*:    e4004800        st1b    \{z0\.b\}, p2, \[x0, x0\]
+.*:    e4005c00        st1b    \{z0\.b\}, p7, \[x0, x0\]
+.*:    e4005c00        st1b    \{z0\.b\}, p7, \[x0, x0\]
+.*:    e4005c00        st1b    \{z0\.b\}, p7, \[x0, x0\]
+.*:    e4004060        st1b    \{z0\.b\}, p0, \[x3, x0\]
+.*:    e4004060        st1b    \{z0\.b\}, p0, \[x3, x0\]
+.*:    e4004060        st1b    \{z0\.b\}, p0, \[x3, x0\]
+.*:    e40043e0        st1b    \{z0\.b\}, p0, \[sp, x0\]
+.*:    e40043e0        st1b    \{z0\.b\}, p0, \[sp, x0\]
+.*:    e40043e0        st1b    \{z0\.b\}, p0, \[sp, x0\]
+.*:    e4044000        st1b    \{z0\.b\}, p0, \[x0, x4\]
+.*:    e4044000        st1b    \{z0\.b\}, p0, \[x0, x4\]
+.*:    e4044000        st1b    \{z0\.b\}, p0, \[x0, x4\]
+.*:    e41e4000        st1b    \{z0\.b\}, p0, \[x0, x30\]
+.*:    e41e4000        st1b    \{z0\.b\}, p0, \[x0, x30\]
+.*:    e41e4000        st1b    \{z0\.b\}, p0, \[x0, x30\]
+.*:    e4008000        st1b    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4008000        st1b    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4008000        st1b    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4008000        st1b    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4008001        st1b    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4008001        st1b    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4008001        st1b    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4008001        st1b    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e400801f        st1b    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e400801f        st1b    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e400801f        st1b    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e400801f        st1b    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4008800        st1b    \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
+.*:    e4008800        st1b    \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
+.*:    e4008800        st1b    \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
+.*:    e4009c00        st1b    \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
+.*:    e4009c00        st1b    \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
+.*:    e4009c00        st1b    \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
+.*:    e4008060        st1b    \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
+.*:    e4008060        st1b    \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
+.*:    e4008060        st1b    \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
+.*:    e40083e0        st1b    \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
+.*:    e40083e0        st1b    \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
+.*:    e40083e0        st1b    \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
+.*:    e4048000        st1b    \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
+.*:    e4048000        st1b    \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
+.*:    e4048000        st1b    \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
+.*:    e41f8000        st1b    \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
+.*:    e41f8000        st1b    \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
+.*:    e41f8000        st1b    \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
+.*:    e400c000        st1b    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e400c000        st1b    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e400c000        st1b    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e400c000        st1b    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e400c001        st1b    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e400c001        st1b    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e400c001        st1b    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e400c001        st1b    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e400c01f        st1b    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e400c01f        st1b    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e400c01f        st1b    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e400c01f        st1b    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e400c800        st1b    \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
+.*:    e400c800        st1b    \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
+.*:    e400c800        st1b    \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
+.*:    e400dc00        st1b    \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
+.*:    e400dc00        st1b    \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
+.*:    e400dc00        st1b    \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
+.*:    e400c060        st1b    \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
+.*:    e400c060        st1b    \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
+.*:    e400c060        st1b    \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
+.*:    e400c3e0        st1b    \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
+.*:    e400c3e0        st1b    \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
+.*:    e400c3e0        st1b    \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
+.*:    e404c000        st1b    \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
+.*:    e404c000        st1b    \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
+.*:    e404c000        st1b    \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
+.*:    e41fc000        st1b    \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
+.*:    e41fc000        st1b    \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
+.*:    e41fc000        st1b    \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
+.*:    e400a000        st1b    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e400a000        st1b    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e400a000        st1b    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e400a000        st1b    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e400a001        st1b    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e400a001        st1b    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e400a001        st1b    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e400a001        st1b    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e400a01f        st1b    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e400a01f        st1b    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e400a01f        st1b    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e400a01f        st1b    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e400a800        st1b    \{z0\.d\}, p2, \[x0, z0\.d\]
+.*:    e400a800        st1b    \{z0\.d\}, p2, \[x0, z0\.d\]
+.*:    e400a800        st1b    \{z0\.d\}, p2, \[x0, z0\.d\]
+.*:    e400bc00        st1b    \{z0\.d\}, p7, \[x0, z0\.d\]
+.*:    e400bc00        st1b    \{z0\.d\}, p7, \[x0, z0\.d\]
+.*:    e400bc00        st1b    \{z0\.d\}, p7, \[x0, z0\.d\]
+.*:    e400a060        st1b    \{z0\.d\}, p0, \[x3, z0\.d\]
+.*:    e400a060        st1b    \{z0\.d\}, p0, \[x3, z0\.d\]
+.*:    e400a060        st1b    \{z0\.d\}, p0, \[x3, z0\.d\]
+.*:    e400a3e0        st1b    \{z0\.d\}, p0, \[sp, z0\.d\]
+.*:    e400a3e0        st1b    \{z0\.d\}, p0, \[sp, z0\.d\]
+.*:    e400a3e0        st1b    \{z0\.d\}, p0, \[sp, z0\.d\]
+.*:    e404a000        st1b    \{z0\.d\}, p0, \[x0, z4\.d\]
+.*:    e404a000        st1b    \{z0\.d\}, p0, \[x0, z4\.d\]
+.*:    e404a000        st1b    \{z0\.d\}, p0, \[x0, z4\.d\]
+.*:    e41fa000        st1b    \{z0\.d\}, p0, \[x0, z31\.d\]
+.*:    e41fa000        st1b    \{z0\.d\}, p0, \[x0, z31\.d\]
+.*:    e41fa000        st1b    \{z0\.d\}, p0, \[x0, z31\.d\]
+.*:    e4204000        st1b    \{z0\.h\}, p0, \[x0, x0\]
+.*:    e4204000        st1b    \{z0\.h\}, p0, \[x0, x0\]
+.*:    e4204000        st1b    \{z0\.h\}, p0, \[x0, x0\]
+.*:    e4204000        st1b    \{z0\.h\}, p0, \[x0, x0\]
+.*:    e4204001        st1b    \{z1\.h\}, p0, \[x0, x0\]
+.*:    e4204001        st1b    \{z1\.h\}, p0, \[x0, x0\]
+.*:    e4204001        st1b    \{z1\.h\}, p0, \[x0, x0\]
+.*:    e4204001        st1b    \{z1\.h\}, p0, \[x0, x0\]
+.*:    e420401f        st1b    \{z31\.h\}, p0, \[x0, x0\]
+.*:    e420401f        st1b    \{z31\.h\}, p0, \[x0, x0\]
+.*:    e420401f        st1b    \{z31\.h\}, p0, \[x0, x0\]
+.*:    e420401f        st1b    \{z31\.h\}, p0, \[x0, x0\]
+.*:    e4204800        st1b    \{z0\.h\}, p2, \[x0, x0\]
+.*:    e4204800        st1b    \{z0\.h\}, p2, \[x0, x0\]
+.*:    e4204800        st1b    \{z0\.h\}, p2, \[x0, x0\]
+.*:    e4205c00        st1b    \{z0\.h\}, p7, \[x0, x0\]
+.*:    e4205c00        st1b    \{z0\.h\}, p7, \[x0, x0\]
+.*:    e4205c00        st1b    \{z0\.h\}, p7, \[x0, x0\]
+.*:    e4204060        st1b    \{z0\.h\}, p0, \[x3, x0\]
+.*:    e4204060        st1b    \{z0\.h\}, p0, \[x3, x0\]
+.*:    e4204060        st1b    \{z0\.h\}, p0, \[x3, x0\]
+.*:    e42043e0        st1b    \{z0\.h\}, p0, \[sp, x0\]
+.*:    e42043e0        st1b    \{z0\.h\}, p0, \[sp, x0\]
+.*:    e42043e0        st1b    \{z0\.h\}, p0, \[sp, x0\]
+.*:    e4244000        st1b    \{z0\.h\}, p0, \[x0, x4\]
+.*:    e4244000        st1b    \{z0\.h\}, p0, \[x0, x4\]
+.*:    e4244000        st1b    \{z0\.h\}, p0, \[x0, x4\]
+.*:    e43e4000        st1b    \{z0\.h\}, p0, \[x0, x30\]
+.*:    e43e4000        st1b    \{z0\.h\}, p0, \[x0, x30\]
+.*:    e43e4000        st1b    \{z0\.h\}, p0, \[x0, x30\]
+.*:    e4404000        st1b    \{z0\.s\}, p0, \[x0, x0\]
+.*:    e4404000        st1b    \{z0\.s\}, p0, \[x0, x0\]
+.*:    e4404000        st1b    \{z0\.s\}, p0, \[x0, x0\]
+.*:    e4404000        st1b    \{z0\.s\}, p0, \[x0, x0\]
+.*:    e4404001        st1b    \{z1\.s\}, p0, \[x0, x0\]
+.*:    e4404001        st1b    \{z1\.s\}, p0, \[x0, x0\]
+.*:    e4404001        st1b    \{z1\.s\}, p0, \[x0, x0\]
+.*:    e4404001        st1b    \{z1\.s\}, p0, \[x0, x0\]
+.*:    e440401f        st1b    \{z31\.s\}, p0, \[x0, x0\]
+.*:    e440401f        st1b    \{z31\.s\}, p0, \[x0, x0\]
+.*:    e440401f        st1b    \{z31\.s\}, p0, \[x0, x0\]
+.*:    e440401f        st1b    \{z31\.s\}, p0, \[x0, x0\]
+.*:    e4404800        st1b    \{z0\.s\}, p2, \[x0, x0\]
+.*:    e4404800        st1b    \{z0\.s\}, p2, \[x0, x0\]
+.*:    e4404800        st1b    \{z0\.s\}, p2, \[x0, x0\]
+.*:    e4405c00        st1b    \{z0\.s\}, p7, \[x0, x0\]
+.*:    e4405c00        st1b    \{z0\.s\}, p7, \[x0, x0\]
+.*:    e4405c00        st1b    \{z0\.s\}, p7, \[x0, x0\]
+.*:    e4404060        st1b    \{z0\.s\}, p0, \[x3, x0\]
+.*:    e4404060        st1b    \{z0\.s\}, p0, \[x3, x0\]
+.*:    e4404060        st1b    \{z0\.s\}, p0, \[x3, x0\]
+.*:    e44043e0        st1b    \{z0\.s\}, p0, \[sp, x0\]
+.*:    e44043e0        st1b    \{z0\.s\}, p0, \[sp, x0\]
+.*:    e44043e0        st1b    \{z0\.s\}, p0, \[sp, x0\]
+.*:    e4444000        st1b    \{z0\.s\}, p0, \[x0, x4\]
+.*:    e4444000        st1b    \{z0\.s\}, p0, \[x0, x4\]
+.*:    e4444000        st1b    \{z0\.s\}, p0, \[x0, x4\]
+.*:    e45e4000        st1b    \{z0\.s\}, p0, \[x0, x30\]
+.*:    e45e4000        st1b    \{z0\.s\}, p0, \[x0, x30\]
+.*:    e45e4000        st1b    \{z0\.s\}, p0, \[x0, x30\]
+.*:    e4408000        st1b    \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4408000        st1b    \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4408000        st1b    \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4408000        st1b    \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4408001        st1b    \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4408001        st1b    \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4408001        st1b    \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4408001        st1b    \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e440801f        st1b    \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e440801f        st1b    \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e440801f        st1b    \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e440801f        st1b    \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4408800        st1b    \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
+.*:    e4408800        st1b    \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
+.*:    e4408800        st1b    \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
+.*:    e4409c00        st1b    \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
+.*:    e4409c00        st1b    \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
+.*:    e4409c00        st1b    \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
+.*:    e4408060        st1b    \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
+.*:    e4408060        st1b    \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
+.*:    e4408060        st1b    \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
+.*:    e44083e0        st1b    \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
+.*:    e44083e0        st1b    \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
+.*:    e44083e0        st1b    \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
+.*:    e4448000        st1b    \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
+.*:    e4448000        st1b    \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
+.*:    e4448000        st1b    \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
+.*:    e45f8000        st1b    \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
+.*:    e45f8000        st1b    \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
+.*:    e45f8000        st1b    \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
+.*:    e440c000        st1b    \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e440c000        st1b    \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e440c000        st1b    \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e440c000        st1b    \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e440c001        st1b    \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e440c001        st1b    \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e440c001        st1b    \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e440c001        st1b    \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e440c01f        st1b    \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e440c01f        st1b    \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e440c01f        st1b    \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e440c01f        st1b    \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e440c800        st1b    \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
+.*:    e440c800        st1b    \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
+.*:    e440c800        st1b    \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
+.*:    e440dc00        st1b    \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
+.*:    e440dc00        st1b    \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
+.*:    e440dc00        st1b    \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
+.*:    e440c060        st1b    \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
+.*:    e440c060        st1b    \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
+.*:    e440c060        st1b    \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
+.*:    e440c3e0        st1b    \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
+.*:    e440c3e0        st1b    \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
+.*:    e440c3e0        st1b    \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
+.*:    e444c000        st1b    \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
+.*:    e444c000        st1b    \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
+.*:    e444c000        st1b    \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
+.*:    e45fc000        st1b    \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
+.*:    e45fc000        st1b    \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
+.*:    e45fc000        st1b    \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
+.*:    e4604000        st1b    \{z0\.d\}, p0, \[x0, x0\]
+.*:    e4604000        st1b    \{z0\.d\}, p0, \[x0, x0\]
+.*:    e4604000        st1b    \{z0\.d\}, p0, \[x0, x0\]
+.*:    e4604000        st1b    \{z0\.d\}, p0, \[x0, x0\]
+.*:    e4604001        st1b    \{z1\.d\}, p0, \[x0, x0\]
+.*:    e4604001        st1b    \{z1\.d\}, p0, \[x0, x0\]
+.*:    e4604001        st1b    \{z1\.d\}, p0, \[x0, x0\]
+.*:    e4604001        st1b    \{z1\.d\}, p0, \[x0, x0\]
+.*:    e460401f        st1b    \{z31\.d\}, p0, \[x0, x0\]
+.*:    e460401f        st1b    \{z31\.d\}, p0, \[x0, x0\]
+.*:    e460401f        st1b    \{z31\.d\}, p0, \[x0, x0\]
+.*:    e460401f        st1b    \{z31\.d\}, p0, \[x0, x0\]
+.*:    e4604800        st1b    \{z0\.d\}, p2, \[x0, x0\]
+.*:    e4604800        st1b    \{z0\.d\}, p2, \[x0, x0\]
+.*:    e4604800        st1b    \{z0\.d\}, p2, \[x0, x0\]
+.*:    e4605c00        st1b    \{z0\.d\}, p7, \[x0, x0\]
+.*:    e4605c00        st1b    \{z0\.d\}, p7, \[x0, x0\]
+.*:    e4605c00        st1b    \{z0\.d\}, p7, \[x0, x0\]
+.*:    e4604060        st1b    \{z0\.d\}, p0, \[x3, x0\]
+.*:    e4604060        st1b    \{z0\.d\}, p0, \[x3, x0\]
+.*:    e4604060        st1b    \{z0\.d\}, p0, \[x3, x0\]
+.*:    e46043e0        st1b    \{z0\.d\}, p0, \[sp, x0\]
+.*:    e46043e0        st1b    \{z0\.d\}, p0, \[sp, x0\]
+.*:    e46043e0        st1b    \{z0\.d\}, p0, \[sp, x0\]
+.*:    e4644000        st1b    \{z0\.d\}, p0, \[x0, x4\]
+.*:    e4644000        st1b    \{z0\.d\}, p0, \[x0, x4\]
+.*:    e4644000        st1b    \{z0\.d\}, p0, \[x0, x4\]
+.*:    e47e4000        st1b    \{z0\.d\}, p0, \[x0, x30\]
+.*:    e47e4000        st1b    \{z0\.d\}, p0, \[x0, x30\]
+.*:    e47e4000        st1b    \{z0\.d\}, p0, \[x0, x30\]
 .*:    e400e000        st1b    \{z0\.b\}, p0, \[x0\]
 .*:    e400e000        st1b    \{z0\.b\}, p0, \[x0\]
 .*:    e400e000        st1b    \{z0\.b\}, p0, \[x0\]
@@ -29141,14 +29141,14 @@ Disassembly of section .*:
 .*:    e400e3e0        st1b    \{z0\.b\}, p0, \[sp\]
 .*:    e400e3e0        st1b    \{z0\.b\}, p0, \[sp\]
 .*:    e400e3e0        st1b    \{z0\.b\}, p0, \[sp\]
-.*:    e407e000        st1b    \{z0\.b\}, p0, \[x0,#7,mul vl\]
-.*:    e407e000        st1b    \{z0\.b\}, p0, \[x0,#7,mul vl\]
-.*:    e408e000        st1b    \{z0\.b\}, p0, \[x0,#-8,mul vl\]
-.*:    e408e000        st1b    \{z0\.b\}, p0, \[x0,#-8,mul vl\]
-.*:    e409e000        st1b    \{z0\.b\}, p0, \[x0,#-7,mul vl\]
-.*:    e409e000        st1b    \{z0\.b\}, p0, \[x0,#-7,mul vl\]
-.*:    e40fe000        st1b    \{z0\.b\}, p0, \[x0,#-1,mul vl\]
-.*:    e40fe000        st1b    \{z0\.b\}, p0, \[x0,#-1,mul vl\]
+.*:    e407e000        st1b    \{z0\.b\}, p0, \[x0, #7, mul vl\]
+.*:    e407e000        st1b    \{z0\.b\}, p0, \[x0, #7, mul vl\]
+.*:    e408e000        st1b    \{z0\.b\}, p0, \[x0, #-8, mul vl\]
+.*:    e408e000        st1b    \{z0\.b\}, p0, \[x0, #-8, mul vl\]
+.*:    e409e000        st1b    \{z0\.b\}, p0, \[x0, #-7, mul vl\]
+.*:    e409e000        st1b    \{z0\.b\}, p0, \[x0, #-7, mul vl\]
+.*:    e40fe000        st1b    \{z0\.b\}, p0, \[x0, #-1, mul vl\]
+.*:    e40fe000        st1b    \{z0\.b\}, p0, \[x0, #-1, mul vl\]
 .*:    e420e000        st1b    \{z0\.h\}, p0, \[x0\]
 .*:    e420e000        st1b    \{z0\.h\}, p0, \[x0\]
 .*:    e420e000        st1b    \{z0\.h\}, p0, \[x0\]
@@ -29180,14 +29180,14 @@ Disassembly of section .*:
 .*:    e420e3e0        st1b    \{z0\.h\}, p0, \[sp\]
 .*:    e420e3e0        st1b    \{z0\.h\}, p0, \[sp\]
 .*:    e420e3e0        st1b    \{z0\.h\}, p0, \[sp\]
-.*:    e427e000        st1b    \{z0\.h\}, p0, \[x0,#7,mul vl\]
-.*:    e427e000        st1b    \{z0\.h\}, p0, \[x0,#7,mul vl\]
-.*:    e428e000        st1b    \{z0\.h\}, p0, \[x0,#-8,mul vl\]
-.*:    e428e000        st1b    \{z0\.h\}, p0, \[x0,#-8,mul vl\]
-.*:    e429e000        st1b    \{z0\.h\}, p0, \[x0,#-7,mul vl\]
-.*:    e429e000        st1b    \{z0\.h\}, p0, \[x0,#-7,mul vl\]
-.*:    e42fe000        st1b    \{z0\.h\}, p0, \[x0,#-1,mul vl\]
-.*:    e42fe000        st1b    \{z0\.h\}, p0, \[x0,#-1,mul vl\]
+.*:    e427e000        st1b    \{z0\.h\}, p0, \[x0, #7, mul vl\]
+.*:    e427e000        st1b    \{z0\.h\}, p0, \[x0, #7, mul vl\]
+.*:    e428e000        st1b    \{z0\.h\}, p0, \[x0, #-8, mul vl\]
+.*:    e428e000        st1b    \{z0\.h\}, p0, \[x0, #-8, mul vl\]
+.*:    e429e000        st1b    \{z0\.h\}, p0, \[x0, #-7, mul vl\]
+.*:    e429e000        st1b    \{z0\.h\}, p0, \[x0, #-7, mul vl\]
+.*:    e42fe000        st1b    \{z0\.h\}, p0, \[x0, #-1, mul vl\]
+.*:    e42fe000        st1b    \{z0\.h\}, p0, \[x0, #-1, mul vl\]
 .*:    e440a000        st1b    \{z0\.d\}, p0, \[z0\.d\]
 .*:    e440a000        st1b    \{z0\.d\}, p0, \[z0\.d\]
 .*:    e440a000        st1b    \{z0\.d\}, p0, \[z0\.d\]
@@ -29212,14 +29212,14 @@ Disassembly of section .*:
 .*:    e440a3e0        st1b    \{z0\.d\}, p0, \[z31\.d\]
 .*:    e440a3e0        st1b    \{z0\.d\}, p0, \[z31\.d\]
 .*:    e440a3e0        st1b    \{z0\.d\}, p0, \[z31\.d\]
-.*:    e44fa000        st1b    \{z0\.d\}, p0, \[z0\.d,#15\]
-.*:    e44fa000        st1b    \{z0\.d\}, p0, \[z0\.d,#15\]
-.*:    e450a000        st1b    \{z0\.d\}, p0, \[z0\.d,#16\]
-.*:    e450a000        st1b    \{z0\.d\}, p0, \[z0\.d,#16\]
-.*:    e451a000        st1b    \{z0\.d\}, p0, \[z0\.d,#17\]
-.*:    e451a000        st1b    \{z0\.d\}, p0, \[z0\.d,#17\]
-.*:    e45fa000        st1b    \{z0\.d\}, p0, \[z0\.d,#31\]
-.*:    e45fa000        st1b    \{z0\.d\}, p0, \[z0\.d,#31\]
+.*:    e44fa000        st1b    \{z0\.d\}, p0, \[z0\.d, #15\]
+.*:    e44fa000        st1b    \{z0\.d\}, p0, \[z0\.d, #15\]
+.*:    e450a000        st1b    \{z0\.d\}, p0, \[z0\.d, #16\]
+.*:    e450a000        st1b    \{z0\.d\}, p0, \[z0\.d, #16\]
+.*:    e451a000        st1b    \{z0\.d\}, p0, \[z0\.d, #17\]
+.*:    e451a000        st1b    \{z0\.d\}, p0, \[z0\.d, #17\]
+.*:    e45fa000        st1b    \{z0\.d\}, p0, \[z0\.d, #31\]
+.*:    e45fa000        st1b    \{z0\.d\}, p0, \[z0\.d, #31\]
 .*:    e440e000        st1b    \{z0\.s\}, p0, \[x0\]
 .*:    e440e000        st1b    \{z0\.s\}, p0, \[x0\]
 .*:    e440e000        st1b    \{z0\.s\}, p0, \[x0\]
@@ -29251,14 +29251,14 @@ Disassembly of section .*:
 .*:    e440e3e0        st1b    \{z0\.s\}, p0, \[sp\]
 .*:    e440e3e0        st1b    \{z0\.s\}, p0, \[sp\]
 .*:    e440e3e0        st1b    \{z0\.s\}, p0, \[sp\]
-.*:    e447e000        st1b    \{z0\.s\}, p0, \[x0,#7,mul vl\]
-.*:    e447e000        st1b    \{z0\.s\}, p0, \[x0,#7,mul vl\]
-.*:    e448e000        st1b    \{z0\.s\}, p0, \[x0,#-8,mul vl\]
-.*:    e448e000        st1b    \{z0\.s\}, p0, \[x0,#-8,mul vl\]
-.*:    e449e000        st1b    \{z0\.s\}, p0, \[x0,#-7,mul vl\]
-.*:    e449e000        st1b    \{z0\.s\}, p0, \[x0,#-7,mul vl\]
-.*:    e44fe000        st1b    \{z0\.s\}, p0, \[x0,#-1,mul vl\]
-.*:    e44fe000        st1b    \{z0\.s\}, p0, \[x0,#-1,mul vl\]
+.*:    e447e000        st1b    \{z0\.s\}, p0, \[x0, #7, mul vl\]
+.*:    e447e000        st1b    \{z0\.s\}, p0, \[x0, #7, mul vl\]
+.*:    e448e000        st1b    \{z0\.s\}, p0, \[x0, #-8, mul vl\]
+.*:    e448e000        st1b    \{z0\.s\}, p0, \[x0, #-8, mul vl\]
+.*:    e449e000        st1b    \{z0\.s\}, p0, \[x0, #-7, mul vl\]
+.*:    e449e000        st1b    \{z0\.s\}, p0, \[x0, #-7, mul vl\]
+.*:    e44fe000        st1b    \{z0\.s\}, p0, \[x0, #-1, mul vl\]
+.*:    e44fe000        st1b    \{z0\.s\}, p0, \[x0, #-1, mul vl\]
 .*:    e460a000        st1b    \{z0\.s\}, p0, \[z0\.s\]
 .*:    e460a000        st1b    \{z0\.s\}, p0, \[z0\.s\]
 .*:    e460a000        st1b    \{z0\.s\}, p0, \[z0\.s\]
@@ -29283,14 +29283,14 @@ Disassembly of section .*:
 .*:    e460a3e0        st1b    \{z0\.s\}, p0, \[z31\.s\]
 .*:    e460a3e0        st1b    \{z0\.s\}, p0, \[z31\.s\]
 .*:    e460a3e0        st1b    \{z0\.s\}, p0, \[z31\.s\]
-.*:    e46fa000        st1b    \{z0\.s\}, p0, \[z0\.s,#15\]
-.*:    e46fa000        st1b    \{z0\.s\}, p0, \[z0\.s,#15\]
-.*:    e470a000        st1b    \{z0\.s\}, p0, \[z0\.s,#16\]
-.*:    e470a000        st1b    \{z0\.s\}, p0, \[z0\.s,#16\]
-.*:    e471a000        st1b    \{z0\.s\}, p0, \[z0\.s,#17\]
-.*:    e471a000        st1b    \{z0\.s\}, p0, \[z0\.s,#17\]
-.*:    e47fa000        st1b    \{z0\.s\}, p0, \[z0\.s,#31\]
-.*:    e47fa000        st1b    \{z0\.s\}, p0, \[z0\.s,#31\]
+.*:    e46fa000        st1b    \{z0\.s\}, p0, \[z0\.s, #15\]
+.*:    e46fa000        st1b    \{z0\.s\}, p0, \[z0\.s, #15\]
+.*:    e470a000        st1b    \{z0\.s\}, p0, \[z0\.s, #16\]
+.*:    e470a000        st1b    \{z0\.s\}, p0, \[z0\.s, #16\]
+.*:    e471a000        st1b    \{z0\.s\}, p0, \[z0\.s, #17\]
+.*:    e471a000        st1b    \{z0\.s\}, p0, \[z0\.s, #17\]
+.*:    e47fa000        st1b    \{z0\.s\}, p0, \[z0\.s, #31\]
+.*:    e47fa000        st1b    \{z0\.s\}, p0, \[z0\.s, #31\]
 .*:    e460e000        st1b    \{z0\.d\}, p0, \[x0\]
 .*:    e460e000        st1b    \{z0\.d\}, p0, \[x0\]
 .*:    e460e000        st1b    \{z0\.d\}, p0, \[x0\]
@@ -29322,188 +29322,188 @@ Disassembly of section .*:
 .*:    e460e3e0        st1b    \{z0\.d\}, p0, \[sp\]
 .*:    e460e3e0        st1b    \{z0\.d\}, p0, \[sp\]
 .*:    e460e3e0        st1b    \{z0\.d\}, p0, \[sp\]
-.*:    e467e000        st1b    \{z0\.d\}, p0, \[x0,#7,mul vl\]
-.*:    e467e000        st1b    \{z0\.d\}, p0, \[x0,#7,mul vl\]
-.*:    e468e000        st1b    \{z0\.d\}, p0, \[x0,#-8,mul vl\]
-.*:    e468e000        st1b    \{z0\.d\}, p0, \[x0,#-8,mul vl\]
-.*:    e469e000        st1b    \{z0\.d\}, p0, \[x0,#-7,mul vl\]
-.*:    e469e000        st1b    \{z0\.d\}, p0, \[x0,#-7,mul vl\]
-.*:    e46fe000        st1b    \{z0\.d\}, p0, \[x0,#-1,mul vl\]
-.*:    e46fe000        st1b    \{z0\.d\}, p0, \[x0,#-1,mul vl\]
-.*:    e5808000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5808000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5808000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5808000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5808001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5808001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5808001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5808001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e580801f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e580801f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e580801f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e580801f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5808800        st1d    \{z0\.d\}, p2, \[x0,z0\.d,uxtw\]
-.*:    e5808800        st1d    \{z0\.d\}, p2, \[x0,z0\.d,uxtw\]
-.*:    e5808800        st1d    \{z0\.d\}, p2, \[x0,z0\.d,uxtw\]
-.*:    e5809c00        st1d    \{z0\.d\}, p7, \[x0,z0\.d,uxtw\]
-.*:    e5809c00        st1d    \{z0\.d\}, p7, \[x0,z0\.d,uxtw\]
-.*:    e5809c00        st1d    \{z0\.d\}, p7, \[x0,z0\.d,uxtw\]
-.*:    e5808060        st1d    \{z0\.d\}, p0, \[x3,z0\.d,uxtw\]
-.*:    e5808060        st1d    \{z0\.d\}, p0, \[x3,z0\.d,uxtw\]
-.*:    e5808060        st1d    \{z0\.d\}, p0, \[x3,z0\.d,uxtw\]
-.*:    e58083e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d,uxtw\]
-.*:    e58083e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d,uxtw\]
-.*:    e58083e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d,uxtw\]
-.*:    e5848000        st1d    \{z0\.d\}, p0, \[x0,z4\.d,uxtw\]
-.*:    e5848000        st1d    \{z0\.d\}, p0, \[x0,z4\.d,uxtw\]
-.*:    e5848000        st1d    \{z0\.d\}, p0, \[x0,z4\.d,uxtw\]
-.*:    e59f8000        st1d    \{z0\.d\}, p0, \[x0,z31\.d,uxtw\]
-.*:    e59f8000        st1d    \{z0\.d\}, p0, \[x0,z31\.d,uxtw\]
-.*:    e59f8000        st1d    \{z0\.d\}, p0, \[x0,z31\.d,uxtw\]
-.*:    e580c000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e580c000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e580c000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e580c000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e580c001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e580c001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e580c001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e580c001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e580c01f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e580c01f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e580c01f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e580c01f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e580c800        st1d    \{z0\.d\}, p2, \[x0,z0\.d,sxtw\]
-.*:    e580c800        st1d    \{z0\.d\}, p2, \[x0,z0\.d,sxtw\]
-.*:    e580c800        st1d    \{z0\.d\}, p2, \[x0,z0\.d,sxtw\]
-.*:    e580dc00        st1d    \{z0\.d\}, p7, \[x0,z0\.d,sxtw\]
-.*:    e580dc00        st1d    \{z0\.d\}, p7, \[x0,z0\.d,sxtw\]
-.*:    e580dc00        st1d    \{z0\.d\}, p7, \[x0,z0\.d,sxtw\]
-.*:    e580c060        st1d    \{z0\.d\}, p0, \[x3,z0\.d,sxtw\]
-.*:    e580c060        st1d    \{z0\.d\}, p0, \[x3,z0\.d,sxtw\]
-.*:    e580c060        st1d    \{z0\.d\}, p0, \[x3,z0\.d,sxtw\]
-.*:    e580c3e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d,sxtw\]
-.*:    e580c3e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d,sxtw\]
-.*:    e580c3e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d,sxtw\]
-.*:    e584c000        st1d    \{z0\.d\}, p0, \[x0,z4\.d,sxtw\]
-.*:    e584c000        st1d    \{z0\.d\}, p0, \[x0,z4\.d,sxtw\]
-.*:    e584c000        st1d    \{z0\.d\}, p0, \[x0,z4\.d,sxtw\]
-.*:    e59fc000        st1d    \{z0\.d\}, p0, \[x0,z31\.d,sxtw\]
-.*:    e59fc000        st1d    \{z0\.d\}, p0, \[x0,z31\.d,sxtw\]
-.*:    e59fc000        st1d    \{z0\.d\}, p0, \[x0,z31\.d,sxtw\]
-.*:    e580a000        st1d    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e580a000        st1d    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e580a000        st1d    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e580a000        st1d    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e580a001        st1d    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e580a001        st1d    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e580a001        st1d    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e580a001        st1d    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e580a01f        st1d    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e580a01f        st1d    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e580a01f        st1d    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e580a01f        st1d    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e580a800        st1d    \{z0\.d\}, p2, \[x0,z0\.d\]
-.*:    e580a800        st1d    \{z0\.d\}, p2, \[x0,z0\.d\]
-.*:    e580a800        st1d    \{z0\.d\}, p2, \[x0,z0\.d\]
-.*:    e580bc00        st1d    \{z0\.d\}, p7, \[x0,z0\.d\]
-.*:    e580bc00        st1d    \{z0\.d\}, p7, \[x0,z0\.d\]
-.*:    e580bc00        st1d    \{z0\.d\}, p7, \[x0,z0\.d\]
-.*:    e580a060        st1d    \{z0\.d\}, p0, \[x3,z0\.d\]
-.*:    e580a060        st1d    \{z0\.d\}, p0, \[x3,z0\.d\]
-.*:    e580a060        st1d    \{z0\.d\}, p0, \[x3,z0\.d\]
-.*:    e580a3e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d\]
-.*:    e580a3e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d\]
-.*:    e580a3e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d\]
-.*:    e584a000        st1d    \{z0\.d\}, p0, \[x0,z4\.d\]
-.*:    e584a000        st1d    \{z0\.d\}, p0, \[x0,z4\.d\]
-.*:    e584a000        st1d    \{z0\.d\}, p0, \[x0,z4\.d\]
-.*:    e59fa000        st1d    \{z0\.d\}, p0, \[x0,z31\.d\]
-.*:    e59fa000        st1d    \{z0\.d\}, p0, \[x0,z31\.d\]
-.*:    e59fa000        st1d    \{z0\.d\}, p0, \[x0,z31\.d\]
-.*:    e5a08000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,uxtw #3\]
-.*:    e5a08000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,uxtw #3\]
-.*:    e5a08000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,uxtw #3\]
-.*:    e5a08001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,uxtw #3\]
-.*:    e5a08001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,uxtw #3\]
-.*:    e5a08001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,uxtw #3\]
-.*:    e5a0801f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,uxtw #3\]
-.*:    e5a0801f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,uxtw #3\]
-.*:    e5a0801f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,uxtw #3\]
-.*:    e5a08800        st1d    \{z0\.d\}, p2, \[x0,z0\.d,uxtw #3\]
-.*:    e5a08800        st1d    \{z0\.d\}, p2, \[x0,z0\.d,uxtw #3\]
-.*:    e5a09c00        st1d    \{z0\.d\}, p7, \[x0,z0\.d,uxtw #3\]
-.*:    e5a09c00        st1d    \{z0\.d\}, p7, \[x0,z0\.d,uxtw #3\]
-.*:    e5a08060        st1d    \{z0\.d\}, p0, \[x3,z0\.d,uxtw #3\]
-.*:    e5a08060        st1d    \{z0\.d\}, p0, \[x3,z0\.d,uxtw #3\]
-.*:    e5a083e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d,uxtw #3\]
-.*:    e5a083e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d,uxtw #3\]
-.*:    e5a48000        st1d    \{z0\.d\}, p0, \[x0,z4\.d,uxtw #3\]
-.*:    e5a48000        st1d    \{z0\.d\}, p0, \[x0,z4\.d,uxtw #3\]
-.*:    e5bf8000        st1d    \{z0\.d\}, p0, \[x0,z31\.d,uxtw #3\]
-.*:    e5bf8000        st1d    \{z0\.d\}, p0, \[x0,z31\.d,uxtw #3\]
-.*:    e5a0c000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,sxtw #3\]
-.*:    e5a0c000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,sxtw #3\]
-.*:    e5a0c000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,sxtw #3\]
-.*:    e5a0c001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,sxtw #3\]
-.*:    e5a0c001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,sxtw #3\]
-.*:    e5a0c001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,sxtw #3\]
-.*:    e5a0c01f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,sxtw #3\]
-.*:    e5a0c01f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,sxtw #3\]
-.*:    e5a0c01f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,sxtw #3\]
-.*:    e5a0c800        st1d    \{z0\.d\}, p2, \[x0,z0\.d,sxtw #3\]
-.*:    e5a0c800        st1d    \{z0\.d\}, p2, \[x0,z0\.d,sxtw #3\]
-.*:    e5a0dc00        st1d    \{z0\.d\}, p7, \[x0,z0\.d,sxtw #3\]
-.*:    e5a0dc00        st1d    \{z0\.d\}, p7, \[x0,z0\.d,sxtw #3\]
-.*:    e5a0c060        st1d    \{z0\.d\}, p0, \[x3,z0\.d,sxtw #3\]
-.*:    e5a0c060        st1d    \{z0\.d\}, p0, \[x3,z0\.d,sxtw #3\]
-.*:    e5a0c3e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d,sxtw #3\]
-.*:    e5a0c3e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d,sxtw #3\]
-.*:    e5a4c000        st1d    \{z0\.d\}, p0, \[x0,z4\.d,sxtw #3\]
-.*:    e5a4c000        st1d    \{z0\.d\}, p0, \[x0,z4\.d,sxtw #3\]
-.*:    e5bfc000        st1d    \{z0\.d\}, p0, \[x0,z31\.d,sxtw #3\]
-.*:    e5bfc000        st1d    \{z0\.d\}, p0, \[x0,z31\.d,sxtw #3\]
-.*:    e5a0a000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,lsl #3\]
-.*:    e5a0a000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,lsl #3\]
-.*:    e5a0a000        st1d    \{z0\.d\}, p0, \[x0,z0\.d,lsl #3\]
-.*:    e5a0a001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,lsl #3\]
-.*:    e5a0a001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,lsl #3\]
-.*:    e5a0a001        st1d    \{z1\.d\}, p0, \[x0,z0\.d,lsl #3\]
-.*:    e5a0a01f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,lsl #3\]
-.*:    e5a0a01f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,lsl #3\]
-.*:    e5a0a01f        st1d    \{z31\.d\}, p0, \[x0,z0\.d,lsl #3\]
-.*:    e5a0a800        st1d    \{z0\.d\}, p2, \[x0,z0\.d,lsl #3\]
-.*:    e5a0a800        st1d    \{z0\.d\}, p2, \[x0,z0\.d,lsl #3\]
-.*:    e5a0bc00        st1d    \{z0\.d\}, p7, \[x0,z0\.d,lsl #3\]
-.*:    e5a0bc00        st1d    \{z0\.d\}, p7, \[x0,z0\.d,lsl #3\]
-.*:    e5a0a060        st1d    \{z0\.d\}, p0, \[x3,z0\.d,lsl #3\]
-.*:    e5a0a060        st1d    \{z0\.d\}, p0, \[x3,z0\.d,lsl #3\]
-.*:    e5a0a3e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d,lsl #3\]
-.*:    e5a0a3e0        st1d    \{z0\.d\}, p0, \[sp,z0\.d,lsl #3\]
-.*:    e5a4a000        st1d    \{z0\.d\}, p0, \[x0,z4\.d,lsl #3\]
-.*:    e5a4a000        st1d    \{z0\.d\}, p0, \[x0,z4\.d,lsl #3\]
-.*:    e5bfa000        st1d    \{z0\.d\}, p0, \[x0,z31\.d,lsl #3\]
-.*:    e5bfa000        st1d    \{z0\.d\}, p0, \[x0,z31\.d,lsl #3\]
-.*:    e5e04000        st1d    \{z0\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e04000        st1d    \{z0\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e04000        st1d    \{z0\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e04001        st1d    \{z1\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e04001        st1d    \{z1\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e04001        st1d    \{z1\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e0401f        st1d    \{z31\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e0401f        st1d    \{z31\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e0401f        st1d    \{z31\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e04800        st1d    \{z0\.d\}, p2, \[x0,x0,lsl #3\]
-.*:    e5e04800        st1d    \{z0\.d\}, p2, \[x0,x0,lsl #3\]
-.*:    e5e05c00        st1d    \{z0\.d\}, p7, \[x0,x0,lsl #3\]
-.*:    e5e05c00        st1d    \{z0\.d\}, p7, \[x0,x0,lsl #3\]
-.*:    e5e04060        st1d    \{z0\.d\}, p0, \[x3,x0,lsl #3\]
-.*:    e5e04060        st1d    \{z0\.d\}, p0, \[x3,x0,lsl #3\]
-.*:    e5e043e0        st1d    \{z0\.d\}, p0, \[sp,x0,lsl #3\]
-.*:    e5e043e0        st1d    \{z0\.d\}, p0, \[sp,x0,lsl #3\]
-.*:    e5e44000        st1d    \{z0\.d\}, p0, \[x0,x4,lsl #3\]
-.*:    e5e44000        st1d    \{z0\.d\}, p0, \[x0,x4,lsl #3\]
-.*:    e5fe4000        st1d    \{z0\.d\}, p0, \[x0,x30,lsl #3\]
-.*:    e5fe4000        st1d    \{z0\.d\}, p0, \[x0,x30,lsl #3\]
+.*:    e467e000        st1b    \{z0\.d\}, p0, \[x0, #7, mul vl\]
+.*:    e467e000        st1b    \{z0\.d\}, p0, \[x0, #7, mul vl\]
+.*:    e468e000        st1b    \{z0\.d\}, p0, \[x0, #-8, mul vl\]
+.*:    e468e000        st1b    \{z0\.d\}, p0, \[x0, #-8, mul vl\]
+.*:    e469e000        st1b    \{z0\.d\}, p0, \[x0, #-7, mul vl\]
+.*:    e469e000        st1b    \{z0\.d\}, p0, \[x0, #-7, mul vl\]
+.*:    e46fe000        st1b    \{z0\.d\}, p0, \[x0, #-1, mul vl\]
+.*:    e46fe000        st1b    \{z0\.d\}, p0, \[x0, #-1, mul vl\]
+.*:    e5808000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5808000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5808000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5808000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5808001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5808001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5808001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5808001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e580801f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e580801f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e580801f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e580801f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5808800        st1d    \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
+.*:    e5808800        st1d    \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
+.*:    e5808800        st1d    \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
+.*:    e5809c00        st1d    \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
+.*:    e5809c00        st1d    \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
+.*:    e5809c00        st1d    \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
+.*:    e5808060        st1d    \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
+.*:    e5808060        st1d    \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
+.*:    e5808060        st1d    \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
+.*:    e58083e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
+.*:    e58083e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
+.*:    e58083e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
+.*:    e5848000        st1d    \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
+.*:    e5848000        st1d    \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
+.*:    e5848000        st1d    \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
+.*:    e59f8000        st1d    \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
+.*:    e59f8000        st1d    \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
+.*:    e59f8000        st1d    \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
+.*:    e580c000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e580c000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e580c000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e580c000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e580c001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e580c001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e580c001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e580c001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e580c01f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e580c01f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e580c01f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e580c01f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e580c800        st1d    \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
+.*:    e580c800        st1d    \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
+.*:    e580c800        st1d    \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
+.*:    e580dc00        st1d    \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
+.*:    e580dc00        st1d    \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
+.*:    e580dc00        st1d    \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
+.*:    e580c060        st1d    \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
+.*:    e580c060        st1d    \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
+.*:    e580c060        st1d    \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
+.*:    e580c3e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
+.*:    e580c3e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
+.*:    e580c3e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
+.*:    e584c000        st1d    \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
+.*:    e584c000        st1d    \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
+.*:    e584c000        st1d    \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
+.*:    e59fc000        st1d    \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
+.*:    e59fc000        st1d    \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
+.*:    e59fc000        st1d    \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
+.*:    e580a000        st1d    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e580a000        st1d    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e580a000        st1d    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e580a000        st1d    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e580a001        st1d    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e580a001        st1d    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e580a001        st1d    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e580a001        st1d    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e580a01f        st1d    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e580a01f        st1d    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e580a01f        st1d    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e580a01f        st1d    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e580a800        st1d    \{z0\.d\}, p2, \[x0, z0\.d\]
+.*:    e580a800        st1d    \{z0\.d\}, p2, \[x0, z0\.d\]
+.*:    e580a800        st1d    \{z0\.d\}, p2, \[x0, z0\.d\]
+.*:    e580bc00        st1d    \{z0\.d\}, p7, \[x0, z0\.d\]
+.*:    e580bc00        st1d    \{z0\.d\}, p7, \[x0, z0\.d\]
+.*:    e580bc00        st1d    \{z0\.d\}, p7, \[x0, z0\.d\]
+.*:    e580a060        st1d    \{z0\.d\}, p0, \[x3, z0\.d\]
+.*:    e580a060        st1d    \{z0\.d\}, p0, \[x3, z0\.d\]
+.*:    e580a060        st1d    \{z0\.d\}, p0, \[x3, z0\.d\]
+.*:    e580a3e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d\]
+.*:    e580a3e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d\]
+.*:    e580a3e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d\]
+.*:    e584a000        st1d    \{z0\.d\}, p0, \[x0, z4\.d\]
+.*:    e584a000        st1d    \{z0\.d\}, p0, \[x0, z4\.d\]
+.*:    e584a000        st1d    \{z0\.d\}, p0, \[x0, z4\.d\]
+.*:    e59fa000        st1d    \{z0\.d\}, p0, \[x0, z31\.d\]
+.*:    e59fa000        st1d    \{z0\.d\}, p0, \[x0, z31\.d\]
+.*:    e59fa000        st1d    \{z0\.d\}, p0, \[x0, z31\.d\]
+.*:    e5a08000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, uxtw #3\]
+.*:    e5a08000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, uxtw #3\]
+.*:    e5a08000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, uxtw #3\]
+.*:    e5a08001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, uxtw #3\]
+.*:    e5a08001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, uxtw #3\]
+.*:    e5a08001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, uxtw #3\]
+.*:    e5a0801f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, uxtw #3\]
+.*:    e5a0801f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, uxtw #3\]
+.*:    e5a0801f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, uxtw #3\]
+.*:    e5a08800        st1d    \{z0\.d\}, p2, \[x0, z0\.d, uxtw #3\]
+.*:    e5a08800        st1d    \{z0\.d\}, p2, \[x0, z0\.d, uxtw #3\]
+.*:    e5a09c00        st1d    \{z0\.d\}, p7, \[x0, z0\.d, uxtw #3\]
+.*:    e5a09c00        st1d    \{z0\.d\}, p7, \[x0, z0\.d, uxtw #3\]
+.*:    e5a08060        st1d    \{z0\.d\}, p0, \[x3, z0\.d, uxtw #3\]
+.*:    e5a08060        st1d    \{z0\.d\}, p0, \[x3, z0\.d, uxtw #3\]
+.*:    e5a083e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d, uxtw #3\]
+.*:    e5a083e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d, uxtw #3\]
+.*:    e5a48000        st1d    \{z0\.d\}, p0, \[x0, z4\.d, uxtw #3\]
+.*:    e5a48000        st1d    \{z0\.d\}, p0, \[x0, z4\.d, uxtw #3\]
+.*:    e5bf8000        st1d    \{z0\.d\}, p0, \[x0, z31\.d, uxtw #3\]
+.*:    e5bf8000        st1d    \{z0\.d\}, p0, \[x0, z31\.d, uxtw #3\]
+.*:    e5a0c000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, sxtw #3\]
+.*:    e5a0c000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, sxtw #3\]
+.*:    e5a0c000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, sxtw #3\]
+.*:    e5a0c001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, sxtw #3\]
+.*:    e5a0c001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, sxtw #3\]
+.*:    e5a0c001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, sxtw #3\]
+.*:    e5a0c01f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, sxtw #3\]
+.*:    e5a0c01f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, sxtw #3\]
+.*:    e5a0c01f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, sxtw #3\]
+.*:    e5a0c800        st1d    \{z0\.d\}, p2, \[x0, z0\.d, sxtw #3\]
+.*:    e5a0c800        st1d    \{z0\.d\}, p2, \[x0, z0\.d, sxtw #3\]
+.*:    e5a0dc00        st1d    \{z0\.d\}, p7, \[x0, z0\.d, sxtw #3\]
+.*:    e5a0dc00        st1d    \{z0\.d\}, p7, \[x0, z0\.d, sxtw #3\]
+.*:    e5a0c060        st1d    \{z0\.d\}, p0, \[x3, z0\.d, sxtw #3\]
+.*:    e5a0c060        st1d    \{z0\.d\}, p0, \[x3, z0\.d, sxtw #3\]
+.*:    e5a0c3e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d, sxtw #3\]
+.*:    e5a0c3e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d, sxtw #3\]
+.*:    e5a4c000        st1d    \{z0\.d\}, p0, \[x0, z4\.d, sxtw #3\]
+.*:    e5a4c000        st1d    \{z0\.d\}, p0, \[x0, z4\.d, sxtw #3\]
+.*:    e5bfc000        st1d    \{z0\.d\}, p0, \[x0, z31\.d, sxtw #3\]
+.*:    e5bfc000        st1d    \{z0\.d\}, p0, \[x0, z31\.d, sxtw #3\]
+.*:    e5a0a000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, lsl #3\]
+.*:    e5a0a000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, lsl #3\]
+.*:    e5a0a000        st1d    \{z0\.d\}, p0, \[x0, z0\.d, lsl #3\]
+.*:    e5a0a001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, lsl #3\]
+.*:    e5a0a001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, lsl #3\]
+.*:    e5a0a001        st1d    \{z1\.d\}, p0, \[x0, z0\.d, lsl #3\]
+.*:    e5a0a01f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, lsl #3\]
+.*:    e5a0a01f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, lsl #3\]
+.*:    e5a0a01f        st1d    \{z31\.d\}, p0, \[x0, z0\.d, lsl #3\]
+.*:    e5a0a800        st1d    \{z0\.d\}, p2, \[x0, z0\.d, lsl #3\]
+.*:    e5a0a800        st1d    \{z0\.d\}, p2, \[x0, z0\.d, lsl #3\]
+.*:    e5a0bc00        st1d    \{z0\.d\}, p7, \[x0, z0\.d, lsl #3\]
+.*:    e5a0bc00        st1d    \{z0\.d\}, p7, \[x0, z0\.d, lsl #3\]
+.*:    e5a0a060        st1d    \{z0\.d\}, p0, \[x3, z0\.d, lsl #3\]
+.*:    e5a0a060        st1d    \{z0\.d\}, p0, \[x3, z0\.d, lsl #3\]
+.*:    e5a0a3e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d, lsl #3\]
+.*:    e5a0a3e0        st1d    \{z0\.d\}, p0, \[sp, z0\.d, lsl #3\]
+.*:    e5a4a000        st1d    \{z0\.d\}, p0, \[x0, z4\.d, lsl #3\]
+.*:    e5a4a000        st1d    \{z0\.d\}, p0, \[x0, z4\.d, lsl #3\]
+.*:    e5bfa000        st1d    \{z0\.d\}, p0, \[x0, z31\.d, lsl #3\]
+.*:    e5bfa000        st1d    \{z0\.d\}, p0, \[x0, z31\.d, lsl #3\]
+.*:    e5e04000        st1d    \{z0\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e04000        st1d    \{z0\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e04000        st1d    \{z0\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e04001        st1d    \{z1\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e04001        st1d    \{z1\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e04001        st1d    \{z1\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e0401f        st1d    \{z31\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e0401f        st1d    \{z31\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e0401f        st1d    \{z31\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e04800        st1d    \{z0\.d\}, p2, \[x0, x0, lsl #3\]
+.*:    e5e04800        st1d    \{z0\.d\}, p2, \[x0, x0, lsl #3\]
+.*:    e5e05c00        st1d    \{z0\.d\}, p7, \[x0, x0, lsl #3\]
+.*:    e5e05c00        st1d    \{z0\.d\}, p7, \[x0, x0, lsl #3\]
+.*:    e5e04060        st1d    \{z0\.d\}, p0, \[x3, x0, lsl #3\]
+.*:    e5e04060        st1d    \{z0\.d\}, p0, \[x3, x0, lsl #3\]
+.*:    e5e043e0        st1d    \{z0\.d\}, p0, \[sp, x0, lsl #3\]
+.*:    e5e043e0        st1d    \{z0\.d\}, p0, \[sp, x0, lsl #3\]
+.*:    e5e44000        st1d    \{z0\.d\}, p0, \[x0, x4, lsl #3\]
+.*:    e5e44000        st1d    \{z0\.d\}, p0, \[x0, x4, lsl #3\]
+.*:    e5fe4000        st1d    \{z0\.d\}, p0, \[x0, x30, lsl #3\]
+.*:    e5fe4000        st1d    \{z0\.d\}, p0, \[x0, x30, lsl #3\]
 .*:    e5c0a000        st1d    \{z0\.d\}, p0, \[z0\.d\]
 .*:    e5c0a000        st1d    \{z0\.d\}, p0, \[z0\.d\]
 .*:    e5c0a000        st1d    \{z0\.d\}, p0, \[z0\.d\]
@@ -29528,14 +29528,14 @@ Disassembly of section .*:
 .*:    e5c0a3e0        st1d    \{z0\.d\}, p0, \[z31\.d\]
 .*:    e5c0a3e0        st1d    \{z0\.d\}, p0, \[z31\.d\]
 .*:    e5c0a3e0        st1d    \{z0\.d\}, p0, \[z31\.d\]
-.*:    e5cfa000        st1d    \{z0\.d\}, p0, \[z0\.d,#120\]
-.*:    e5cfa000        st1d    \{z0\.d\}, p0, \[z0\.d,#120\]
-.*:    e5d0a000        st1d    \{z0\.d\}, p0, \[z0\.d,#128\]
-.*:    e5d0a000        st1d    \{z0\.d\}, p0, \[z0\.d,#128\]
-.*:    e5d1a000        st1d    \{z0\.d\}, p0, \[z0\.d,#136\]
-.*:    e5d1a000        st1d    \{z0\.d\}, p0, \[z0\.d,#136\]
-.*:    e5dfa000        st1d    \{z0\.d\}, p0, \[z0\.d,#248\]
-.*:    e5dfa000        st1d    \{z0\.d\}, p0, \[z0\.d,#248\]
+.*:    e5cfa000        st1d    \{z0\.d\}, p0, \[z0\.d, #120\]
+.*:    e5cfa000        st1d    \{z0\.d\}, p0, \[z0\.d, #120\]
+.*:    e5d0a000        st1d    \{z0\.d\}, p0, \[z0\.d, #128\]
+.*:    e5d0a000        st1d    \{z0\.d\}, p0, \[z0\.d, #128\]
+.*:    e5d1a000        st1d    \{z0\.d\}, p0, \[z0\.d, #136\]
+.*:    e5d1a000        st1d    \{z0\.d\}, p0, \[z0\.d, #136\]
+.*:    e5dfa000        st1d    \{z0\.d\}, p0, \[z0\.d, #248\]
+.*:    e5dfa000        st1d    \{z0\.d\}, p0, \[z0\.d, #248\]
 .*:    e5e0e000        st1d    \{z0\.d\}, p0, \[x0\]
 .*:    e5e0e000        st1d    \{z0\.d\}, p0, \[x0\]
 .*:    e5e0e000        st1d    \{z0\.d\}, p0, \[x0\]
@@ -29567,332 +29567,332 @@ Disassembly of section .*:
 .*:    e5e0e3e0        st1d    \{z0\.d\}, p0, \[sp\]
 .*:    e5e0e3e0        st1d    \{z0\.d\}, p0, \[sp\]
 .*:    e5e0e3e0        st1d    \{z0\.d\}, p0, \[sp\]
-.*:    e5e7e000        st1d    \{z0\.d\}, p0, \[x0,#7,mul vl\]
-.*:    e5e7e000        st1d    \{z0\.d\}, p0, \[x0,#7,mul vl\]
-.*:    e5e8e000        st1d    \{z0\.d\}, p0, \[x0,#-8,mul vl\]
-.*:    e5e8e000        st1d    \{z0\.d\}, p0, \[x0,#-8,mul vl\]
-.*:    e5e9e000        st1d    \{z0\.d\}, p0, \[x0,#-7,mul vl\]
-.*:    e5e9e000        st1d    \{z0\.d\}, p0, \[x0,#-7,mul vl\]
-.*:    e5efe000        st1d    \{z0\.d\}, p0, \[x0,#-1,mul vl\]
-.*:    e5efe000        st1d    \{z0\.d\}, p0, \[x0,#-1,mul vl\]
-.*:    e4808000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4808000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4808000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4808000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4808001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4808001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4808001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4808001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e480801f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e480801f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e480801f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e480801f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e4808800        st1h    \{z0\.d\}, p2, \[x0,z0\.d,uxtw\]
-.*:    e4808800        st1h    \{z0\.d\}, p2, \[x0,z0\.d,uxtw\]
-.*:    e4808800        st1h    \{z0\.d\}, p2, \[x0,z0\.d,uxtw\]
-.*:    e4809c00        st1h    \{z0\.d\}, p7, \[x0,z0\.d,uxtw\]
-.*:    e4809c00        st1h    \{z0\.d\}, p7, \[x0,z0\.d,uxtw\]
-.*:    e4809c00        st1h    \{z0\.d\}, p7, \[x0,z0\.d,uxtw\]
-.*:    e4808060        st1h    \{z0\.d\}, p0, \[x3,z0\.d,uxtw\]
-.*:    e4808060        st1h    \{z0\.d\}, p0, \[x3,z0\.d,uxtw\]
-.*:    e4808060        st1h    \{z0\.d\}, p0, \[x3,z0\.d,uxtw\]
-.*:    e48083e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d,uxtw\]
-.*:    e48083e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d,uxtw\]
-.*:    e48083e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d,uxtw\]
-.*:    e4848000        st1h    \{z0\.d\}, p0, \[x0,z4\.d,uxtw\]
-.*:    e4848000        st1h    \{z0\.d\}, p0, \[x0,z4\.d,uxtw\]
-.*:    e4848000        st1h    \{z0\.d\}, p0, \[x0,z4\.d,uxtw\]
-.*:    e49f8000        st1h    \{z0\.d\}, p0, \[x0,z31\.d,uxtw\]
-.*:    e49f8000        st1h    \{z0\.d\}, p0, \[x0,z31\.d,uxtw\]
-.*:    e49f8000        st1h    \{z0\.d\}, p0, \[x0,z31\.d,uxtw\]
-.*:    e480c000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e480c000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e480c000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e480c000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e480c001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e480c001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e480c001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e480c001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e480c01f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e480c01f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e480c01f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e480c01f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e480c800        st1h    \{z0\.d\}, p2, \[x0,z0\.d,sxtw\]
-.*:    e480c800        st1h    \{z0\.d\}, p2, \[x0,z0\.d,sxtw\]
-.*:    e480c800        st1h    \{z0\.d\}, p2, \[x0,z0\.d,sxtw\]
-.*:    e480dc00        st1h    \{z0\.d\}, p7, \[x0,z0\.d,sxtw\]
-.*:    e480dc00        st1h    \{z0\.d\}, p7, \[x0,z0\.d,sxtw\]
-.*:    e480dc00        st1h    \{z0\.d\}, p7, \[x0,z0\.d,sxtw\]
-.*:    e480c060        st1h    \{z0\.d\}, p0, \[x3,z0\.d,sxtw\]
-.*:    e480c060        st1h    \{z0\.d\}, p0, \[x3,z0\.d,sxtw\]
-.*:    e480c060        st1h    \{z0\.d\}, p0, \[x3,z0\.d,sxtw\]
-.*:    e480c3e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d,sxtw\]
-.*:    e480c3e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d,sxtw\]
-.*:    e480c3e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d,sxtw\]
-.*:    e484c000        st1h    \{z0\.d\}, p0, \[x0,z4\.d,sxtw\]
-.*:    e484c000        st1h    \{z0\.d\}, p0, \[x0,z4\.d,sxtw\]
-.*:    e484c000        st1h    \{z0\.d\}, p0, \[x0,z4\.d,sxtw\]
-.*:    e49fc000        st1h    \{z0\.d\}, p0, \[x0,z31\.d,sxtw\]
-.*:    e49fc000        st1h    \{z0\.d\}, p0, \[x0,z31\.d,sxtw\]
-.*:    e49fc000        st1h    \{z0\.d\}, p0, \[x0,z31\.d,sxtw\]
-.*:    e480a000        st1h    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e480a000        st1h    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e480a000        st1h    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e480a000        st1h    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e480a001        st1h    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e480a001        st1h    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e480a001        st1h    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e480a001        st1h    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e480a01f        st1h    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e480a01f        st1h    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e480a01f        st1h    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e480a01f        st1h    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e480a800        st1h    \{z0\.d\}, p2, \[x0,z0\.d\]
-.*:    e480a800        st1h    \{z0\.d\}, p2, \[x0,z0\.d\]
-.*:    e480a800        st1h    \{z0\.d\}, p2, \[x0,z0\.d\]
-.*:    e480bc00        st1h    \{z0\.d\}, p7, \[x0,z0\.d\]
-.*:    e480bc00        st1h    \{z0\.d\}, p7, \[x0,z0\.d\]
-.*:    e480bc00        st1h    \{z0\.d\}, p7, \[x0,z0\.d\]
-.*:    e480a060        st1h    \{z0\.d\}, p0, \[x3,z0\.d\]
-.*:    e480a060        st1h    \{z0\.d\}, p0, \[x3,z0\.d\]
-.*:    e480a060        st1h    \{z0\.d\}, p0, \[x3,z0\.d\]
-.*:    e480a3e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d\]
-.*:    e480a3e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d\]
-.*:    e480a3e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d\]
-.*:    e484a000        st1h    \{z0\.d\}, p0, \[x0,z4\.d\]
-.*:    e484a000        st1h    \{z0\.d\}, p0, \[x0,z4\.d\]
-.*:    e484a000        st1h    \{z0\.d\}, p0, \[x0,z4\.d\]
-.*:    e49fa000        st1h    \{z0\.d\}, p0, \[x0,z31\.d\]
-.*:    e49fa000        st1h    \{z0\.d\}, p0, \[x0,z31\.d\]
-.*:    e49fa000        st1h    \{z0\.d\}, p0, \[x0,z31\.d\]
-.*:    e4a04000        st1h    \{z0\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a04000        st1h    \{z0\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a04000        st1h    \{z0\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a04001        st1h    \{z1\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a04001        st1h    \{z1\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a04001        st1h    \{z1\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a0401f        st1h    \{z31\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a0401f        st1h    \{z31\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a0401f        st1h    \{z31\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a04800        st1h    \{z0\.h\}, p2, \[x0,x0,lsl #1\]
-.*:    e4a04800        st1h    \{z0\.h\}, p2, \[x0,x0,lsl #1\]
-.*:    e4a05c00        st1h    \{z0\.h\}, p7, \[x0,x0,lsl #1\]
-.*:    e4a05c00        st1h    \{z0\.h\}, p7, \[x0,x0,lsl #1\]
-.*:    e4a04060        st1h    \{z0\.h\}, p0, \[x3,x0,lsl #1\]
-.*:    e4a04060        st1h    \{z0\.h\}, p0, \[x3,x0,lsl #1\]
-.*:    e4a043e0        st1h    \{z0\.h\}, p0, \[sp,x0,lsl #1\]
-.*:    e4a043e0        st1h    \{z0\.h\}, p0, \[sp,x0,lsl #1\]
-.*:    e4a44000        st1h    \{z0\.h\}, p0, \[x0,x4,lsl #1\]
-.*:    e4a44000        st1h    \{z0\.h\}, p0, \[x0,x4,lsl #1\]
-.*:    e4be4000        st1h    \{z0\.h\}, p0, \[x0,x30,lsl #1\]
-.*:    e4be4000        st1h    \{z0\.h\}, p0, \[x0,x30,lsl #1\]
-.*:    e4a08000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,uxtw #1\]
-.*:    e4a08000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,uxtw #1\]
-.*:    e4a08000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,uxtw #1\]
-.*:    e4a08001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,uxtw #1\]
-.*:    e4a08001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,uxtw #1\]
-.*:    e4a08001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,uxtw #1\]
-.*:    e4a0801f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,uxtw #1\]
-.*:    e4a0801f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,uxtw #1\]
-.*:    e4a0801f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,uxtw #1\]
-.*:    e4a08800        st1h    \{z0\.d\}, p2, \[x0,z0\.d,uxtw #1\]
-.*:    e4a08800        st1h    \{z0\.d\}, p2, \[x0,z0\.d,uxtw #1\]
-.*:    e4a09c00        st1h    \{z0\.d\}, p7, \[x0,z0\.d,uxtw #1\]
-.*:    e4a09c00        st1h    \{z0\.d\}, p7, \[x0,z0\.d,uxtw #1\]
-.*:    e4a08060        st1h    \{z0\.d\}, p0, \[x3,z0\.d,uxtw #1\]
-.*:    e4a08060        st1h    \{z0\.d\}, p0, \[x3,z0\.d,uxtw #1\]
-.*:    e4a083e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d,uxtw #1\]
-.*:    e4a083e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d,uxtw #1\]
-.*:    e4a48000        st1h    \{z0\.d\}, p0, \[x0,z4\.d,uxtw #1\]
-.*:    e4a48000        st1h    \{z0\.d\}, p0, \[x0,z4\.d,uxtw #1\]
-.*:    e4bf8000        st1h    \{z0\.d\}, p0, \[x0,z31\.d,uxtw #1\]
-.*:    e4bf8000        st1h    \{z0\.d\}, p0, \[x0,z31\.d,uxtw #1\]
-.*:    e4a0c000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,sxtw #1\]
-.*:    e4a0c000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,sxtw #1\]
-.*:    e4a0c000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,sxtw #1\]
-.*:    e4a0c001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,sxtw #1\]
-.*:    e4a0c001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,sxtw #1\]
-.*:    e4a0c001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,sxtw #1\]
-.*:    e4a0c01f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,sxtw #1\]
-.*:    e4a0c01f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,sxtw #1\]
-.*:    e4a0c01f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,sxtw #1\]
-.*:    e4a0c800        st1h    \{z0\.d\}, p2, \[x0,z0\.d,sxtw #1\]
-.*:    e4a0c800        st1h    \{z0\.d\}, p2, \[x0,z0\.d,sxtw #1\]
-.*:    e4a0dc00        st1h    \{z0\.d\}, p7, \[x0,z0\.d,sxtw #1\]
-.*:    e4a0dc00        st1h    \{z0\.d\}, p7, \[x0,z0\.d,sxtw #1\]
-.*:    e4a0c060        st1h    \{z0\.d\}, p0, \[x3,z0\.d,sxtw #1\]
-.*:    e4a0c060        st1h    \{z0\.d\}, p0, \[x3,z0\.d,sxtw #1\]
-.*:    e4a0c3e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d,sxtw #1\]
-.*:    e4a0c3e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d,sxtw #1\]
-.*:    e4a4c000        st1h    \{z0\.d\}, p0, \[x0,z4\.d,sxtw #1\]
-.*:    e4a4c000        st1h    \{z0\.d\}, p0, \[x0,z4\.d,sxtw #1\]
-.*:    e4bfc000        st1h    \{z0\.d\}, p0, \[x0,z31\.d,sxtw #1\]
-.*:    e4bfc000        st1h    \{z0\.d\}, p0, \[x0,z31\.d,sxtw #1\]
-.*:    e4a0a000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,lsl #1\]
-.*:    e4a0a000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,lsl #1\]
-.*:    e4a0a000        st1h    \{z0\.d\}, p0, \[x0,z0\.d,lsl #1\]
-.*:    e4a0a001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,lsl #1\]
-.*:    e4a0a001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,lsl #1\]
-.*:    e4a0a001        st1h    \{z1\.d\}, p0, \[x0,z0\.d,lsl #1\]
-.*:    e4a0a01f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,lsl #1\]
-.*:    e4a0a01f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,lsl #1\]
-.*:    e4a0a01f        st1h    \{z31\.d\}, p0, \[x0,z0\.d,lsl #1\]
-.*:    e4a0a800        st1h    \{z0\.d\}, p2, \[x0,z0\.d,lsl #1\]
-.*:    e4a0a800        st1h    \{z0\.d\}, p2, \[x0,z0\.d,lsl #1\]
-.*:    e4a0bc00        st1h    \{z0\.d\}, p7, \[x0,z0\.d,lsl #1\]
-.*:    e4a0bc00        st1h    \{z0\.d\}, p7, \[x0,z0\.d,lsl #1\]
-.*:    e4a0a060        st1h    \{z0\.d\}, p0, \[x3,z0\.d,lsl #1\]
-.*:    e4a0a060        st1h    \{z0\.d\}, p0, \[x3,z0\.d,lsl #1\]
-.*:    e4a0a3e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d,lsl #1\]
-.*:    e4a0a3e0        st1h    \{z0\.d\}, p0, \[sp,z0\.d,lsl #1\]
-.*:    e4a4a000        st1h    \{z0\.d\}, p0, \[x0,z4\.d,lsl #1\]
-.*:    e4a4a000        st1h    \{z0\.d\}, p0, \[x0,z4\.d,lsl #1\]
-.*:    e4bfa000        st1h    \{z0\.d\}, p0, \[x0,z31\.d,lsl #1\]
-.*:    e4bfa000        st1h    \{z0\.d\}, p0, \[x0,z31\.d,lsl #1\]
-.*:    e4c04000        st1h    \{z0\.s\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c04000        st1h    \{z0\.s\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c04000        st1h    \{z0\.s\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c04001        st1h    \{z1\.s\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c04001        st1h    \{z1\.s\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c04001        st1h    \{z1\.s\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c0401f        st1h    \{z31\.s\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c0401f        st1h    \{z31\.s\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c0401f        st1h    \{z31\.s\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c04800        st1h    \{z0\.s\}, p2, \[x0,x0,lsl #1\]
-.*:    e4c04800        st1h    \{z0\.s\}, p2, \[x0,x0,lsl #1\]
-.*:    e4c05c00        st1h    \{z0\.s\}, p7, \[x0,x0,lsl #1\]
-.*:    e4c05c00        st1h    \{z0\.s\}, p7, \[x0,x0,lsl #1\]
-.*:    e4c04060        st1h    \{z0\.s\}, p0, \[x3,x0,lsl #1\]
-.*:    e4c04060        st1h    \{z0\.s\}, p0, \[x3,x0,lsl #1\]
-.*:    e4c043e0        st1h    \{z0\.s\}, p0, \[sp,x0,lsl #1\]
-.*:    e4c043e0        st1h    \{z0\.s\}, p0, \[sp,x0,lsl #1\]
-.*:    e4c44000        st1h    \{z0\.s\}, p0, \[x0,x4,lsl #1\]
-.*:    e4c44000        st1h    \{z0\.s\}, p0, \[x0,x4,lsl #1\]
-.*:    e4de4000        st1h    \{z0\.s\}, p0, \[x0,x30,lsl #1\]
-.*:    e4de4000        st1h    \{z0\.s\}, p0, \[x0,x30,lsl #1\]
-.*:    e4c08000        st1h    \{z0\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4c08000        st1h    \{z0\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4c08000        st1h    \{z0\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4c08000        st1h    \{z0\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4c08001        st1h    \{z1\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4c08001        st1h    \{z1\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4c08001        st1h    \{z1\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4c08001        st1h    \{z1\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4c0801f        st1h    \{z31\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4c0801f        st1h    \{z31\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4c0801f        st1h    \{z31\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4c0801f        st1h    \{z31\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e4c08800        st1h    \{z0\.s\}, p2, \[x0,z0\.s,uxtw\]
-.*:    e4c08800        st1h    \{z0\.s\}, p2, \[x0,z0\.s,uxtw\]
-.*:    e4c08800        st1h    \{z0\.s\}, p2, \[x0,z0\.s,uxtw\]
-.*:    e4c09c00        st1h    \{z0\.s\}, p7, \[x0,z0\.s,uxtw\]
-.*:    e4c09c00        st1h    \{z0\.s\}, p7, \[x0,z0\.s,uxtw\]
-.*:    e4c09c00        st1h    \{z0\.s\}, p7, \[x0,z0\.s,uxtw\]
-.*:    e4c08060        st1h    \{z0\.s\}, p0, \[x3,z0\.s,uxtw\]
-.*:    e4c08060        st1h    \{z0\.s\}, p0, \[x3,z0\.s,uxtw\]
-.*:    e4c08060        st1h    \{z0\.s\}, p0, \[x3,z0\.s,uxtw\]
-.*:    e4c083e0        st1h    \{z0\.s\}, p0, \[sp,z0\.s,uxtw\]
-.*:    e4c083e0        st1h    \{z0\.s\}, p0, \[sp,z0\.s,uxtw\]
-.*:    e4c083e0        st1h    \{z0\.s\}, p0, \[sp,z0\.s,uxtw\]
-.*:    e4c48000        st1h    \{z0\.s\}, p0, \[x0,z4\.s,uxtw\]
-.*:    e4c48000        st1h    \{z0\.s\}, p0, \[x0,z4\.s,uxtw\]
-.*:    e4c48000        st1h    \{z0\.s\}, p0, \[x0,z4\.s,uxtw\]
-.*:    e4df8000        st1h    \{z0\.s\}, p0, \[x0,z31\.s,uxtw\]
-.*:    e4df8000        st1h    \{z0\.s\}, p0, \[x0,z31\.s,uxtw\]
-.*:    e4df8000        st1h    \{z0\.s\}, p0, \[x0,z31\.s,uxtw\]
-.*:    e4c0c000        st1h    \{z0\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e4c0c000        st1h    \{z0\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e4c0c000        st1h    \{z0\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e4c0c000        st1h    \{z0\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e4c0c001        st1h    \{z1\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e4c0c001        st1h    \{z1\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e4c0c001        st1h    \{z1\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e4c0c001        st1h    \{z1\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e4c0c01f        st1h    \{z31\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e4c0c01f        st1h    \{z31\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e4c0c01f        st1h    \{z31\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e4c0c01f        st1h    \{z31\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e4c0c800        st1h    \{z0\.s\}, p2, \[x0,z0\.s,sxtw\]
-.*:    e4c0c800        st1h    \{z0\.s\}, p2, \[x0,z0\.s,sxtw\]
-.*:    e4c0c800        st1h    \{z0\.s\}, p2, \[x0,z0\.s,sxtw\]
-.*:    e4c0dc00        st1h    \{z0\.s\}, p7, \[x0,z0\.s,sxtw\]
-.*:    e4c0dc00        st1h    \{z0\.s\}, p7, \[x0,z0\.s,sxtw\]
-.*:    e4c0dc00        st1h    \{z0\.s\}, p7, \[x0,z0\.s,sxtw\]
-.*:    e4c0c060        st1h    \{z0\.s\}, p0, \[x3,z0\.s,sxtw\]
-.*:    e4c0c060        st1h    \{z0\.s\}, p0, \[x3,z0\.s,sxtw\]
-.*:    e4c0c060        st1h    \{z0\.s\}, p0, \[x3,z0\.s,sxtw\]
-.*:    e4c0c3e0        st1h    \{z0\.s\}, p0, \[sp,z0\.s,sxtw\]
-.*:    e4c0c3e0        st1h    \{z0\.s\}, p0, \[sp,z0\.s,sxtw\]
-.*:    e4c0c3e0        st1h    \{z0\.s\}, p0, \[sp,z0\.s,sxtw\]
-.*:    e4c4c000        st1h    \{z0\.s\}, p0, \[x0,z4\.s,sxtw\]
-.*:    e4c4c000        st1h    \{z0\.s\}, p0, \[x0,z4\.s,sxtw\]
-.*:    e4c4c000        st1h    \{z0\.s\}, p0, \[x0,z4\.s,sxtw\]
-.*:    e4dfc000        st1h    \{z0\.s\}, p0, \[x0,z31\.s,sxtw\]
-.*:    e4dfc000        st1h    \{z0\.s\}, p0, \[x0,z31\.s,sxtw\]
-.*:    e4dfc000        st1h    \{z0\.s\}, p0, \[x0,z31\.s,sxtw\]
-.*:    e4e04000        st1h    \{z0\.d\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e04000        st1h    \{z0\.d\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e04000        st1h    \{z0\.d\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e04001        st1h    \{z1\.d\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e04001        st1h    \{z1\.d\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e04001        st1h    \{z1\.d\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e0401f        st1h    \{z31\.d\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e0401f        st1h    \{z31\.d\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e0401f        st1h    \{z31\.d\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e04800        st1h    \{z0\.d\}, p2, \[x0,x0,lsl #1\]
-.*:    e4e04800        st1h    \{z0\.d\}, p2, \[x0,x0,lsl #1\]
-.*:    e4e05c00        st1h    \{z0\.d\}, p7, \[x0,x0,lsl #1\]
-.*:    e4e05c00        st1h    \{z0\.d\}, p7, \[x0,x0,lsl #1\]
-.*:    e4e04060        st1h    \{z0\.d\}, p0, \[x3,x0,lsl #1\]
-.*:    e4e04060        st1h    \{z0\.d\}, p0, \[x3,x0,lsl #1\]
-.*:    e4e043e0        st1h    \{z0\.d\}, p0, \[sp,x0,lsl #1\]
-.*:    e4e043e0        st1h    \{z0\.d\}, p0, \[sp,x0,lsl #1\]
-.*:    e4e44000        st1h    \{z0\.d\}, p0, \[x0,x4,lsl #1\]
-.*:    e4e44000        st1h    \{z0\.d\}, p0, \[x0,x4,lsl #1\]
-.*:    e4fe4000        st1h    \{z0\.d\}, p0, \[x0,x30,lsl #1\]
-.*:    e4fe4000        st1h    \{z0\.d\}, p0, \[x0,x30,lsl #1\]
-.*:    e4e08000        st1h    \{z0\.s\}, p0, \[x0,z0\.s,uxtw #1\]
-.*:    e4e08000        st1h    \{z0\.s\}, p0, \[x0,z0\.s,uxtw #1\]
-.*:    e4e08000        st1h    \{z0\.s\}, p0, \[x0,z0\.s,uxtw #1\]
-.*:    e4e08001        st1h    \{z1\.s\}, p0, \[x0,z0\.s,uxtw #1\]
-.*:    e4e08001        st1h    \{z1\.s\}, p0, \[x0,z0\.s,uxtw #1\]
-.*:    e4e08001        st1h    \{z1\.s\}, p0, \[x0,z0\.s,uxtw #1\]
-.*:    e4e0801f        st1h    \{z31\.s\}, p0, \[x0,z0\.s,uxtw #1\]
-.*:    e4e0801f        st1h    \{z31\.s\}, p0, \[x0,z0\.s,uxtw #1\]
-.*:    e4e0801f        st1h    \{z31\.s\}, p0, \[x0,z0\.s,uxtw #1\]
-.*:    e4e08800        st1h    \{z0\.s\}, p2, \[x0,z0\.s,uxtw #1\]
-.*:    e4e08800        st1h    \{z0\.s\}, p2, \[x0,z0\.s,uxtw #1\]
-.*:    e4e09c00        st1h    \{z0\.s\}, p7, \[x0,z0\.s,uxtw #1\]
-.*:    e4e09c00        st1h    \{z0\.s\}, p7, \[x0,z0\.s,uxtw #1\]
-.*:    e4e08060        st1h    \{z0\.s\}, p0, \[x3,z0\.s,uxtw #1\]
-.*:    e4e08060        st1h    \{z0\.s\}, p0, \[x3,z0\.s,uxtw #1\]
-.*:    e4e083e0        st1h    \{z0\.s\}, p0, \[sp,z0\.s,uxtw #1\]
-.*:    e4e083e0        st1h    \{z0\.s\}, p0, \[sp,z0\.s,uxtw #1\]
-.*:    e4e48000        st1h    \{z0\.s\}, p0, \[x0,z4\.s,uxtw #1\]
-.*:    e4e48000        st1h    \{z0\.s\}, p0, \[x0,z4\.s,uxtw #1\]
-.*:    e4ff8000        st1h    \{z0\.s\}, p0, \[x0,z31\.s,uxtw #1\]
-.*:    e4ff8000        st1h    \{z0\.s\}, p0, \[x0,z31\.s,uxtw #1\]
-.*:    e4e0c000        st1h    \{z0\.s\}, p0, \[x0,z0\.s,sxtw #1\]
-.*:    e4e0c000        st1h    \{z0\.s\}, p0, \[x0,z0\.s,sxtw #1\]
-.*:    e4e0c000        st1h    \{z0\.s\}, p0, \[x0,z0\.s,sxtw #1\]
-.*:    e4e0c001        st1h    \{z1\.s\}, p0, \[x0,z0\.s,sxtw #1\]
-.*:    e4e0c001        st1h    \{z1\.s\}, p0, \[x0,z0\.s,sxtw #1\]
-.*:    e4e0c001        st1h    \{z1\.s\}, p0, \[x0,z0\.s,sxtw #1\]
-.*:    e4e0c01f        st1h    \{z31\.s\}, p0, \[x0,z0\.s,sxtw #1\]
-.*:    e4e0c01f        st1h    \{z31\.s\}, p0, \[x0,z0\.s,sxtw #1\]
-.*:    e4e0c01f        st1h    \{z31\.s\}, p0, \[x0,z0\.s,sxtw #1\]
-.*:    e4e0c800        st1h    \{z0\.s\}, p2, \[x0,z0\.s,sxtw #1\]
-.*:    e4e0c800        st1h    \{z0\.s\}, p2, \[x0,z0\.s,sxtw #1\]
-.*:    e4e0dc00        st1h    \{z0\.s\}, p7, \[x0,z0\.s,sxtw #1\]
-.*:    e4e0dc00        st1h    \{z0\.s\}, p7, \[x0,z0\.s,sxtw #1\]
-.*:    e4e0c060        st1h    \{z0\.s\}, p0, \[x3,z0\.s,sxtw #1\]
-.*:    e4e0c060        st1h    \{z0\.s\}, p0, \[x3,z0\.s,sxtw #1\]
-.*:    e4e0c3e0        st1h    \{z0\.s\}, p0, \[sp,z0\.s,sxtw #1\]
-.*:    e4e0c3e0        st1h    \{z0\.s\}, p0, \[sp,z0\.s,sxtw #1\]
-.*:    e4e4c000        st1h    \{z0\.s\}, p0, \[x0,z4\.s,sxtw #1\]
-.*:    e4e4c000        st1h    \{z0\.s\}, p0, \[x0,z4\.s,sxtw #1\]
-.*:    e4ffc000        st1h    \{z0\.s\}, p0, \[x0,z31\.s,sxtw #1\]
-.*:    e4ffc000        st1h    \{z0\.s\}, p0, \[x0,z31\.s,sxtw #1\]
+.*:    e5e7e000        st1d    \{z0\.d\}, p0, \[x0, #7, mul vl\]
+.*:    e5e7e000        st1d    \{z0\.d\}, p0, \[x0, #7, mul vl\]
+.*:    e5e8e000        st1d    \{z0\.d\}, p0, \[x0, #-8, mul vl\]
+.*:    e5e8e000        st1d    \{z0\.d\}, p0, \[x0, #-8, mul vl\]
+.*:    e5e9e000        st1d    \{z0\.d\}, p0, \[x0, #-7, mul vl\]
+.*:    e5e9e000        st1d    \{z0\.d\}, p0, \[x0, #-7, mul vl\]
+.*:    e5efe000        st1d    \{z0\.d\}, p0, \[x0, #-1, mul vl\]
+.*:    e5efe000        st1d    \{z0\.d\}, p0, \[x0, #-1, mul vl\]
+.*:    e4808000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4808000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4808000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4808000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4808001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4808001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4808001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4808001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e480801f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e480801f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e480801f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e480801f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e4808800        st1h    \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
+.*:    e4808800        st1h    \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
+.*:    e4808800        st1h    \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
+.*:    e4809c00        st1h    \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
+.*:    e4809c00        st1h    \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
+.*:    e4809c00        st1h    \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
+.*:    e4808060        st1h    \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
+.*:    e4808060        st1h    \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
+.*:    e4808060        st1h    \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
+.*:    e48083e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
+.*:    e48083e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
+.*:    e48083e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
+.*:    e4848000        st1h    \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
+.*:    e4848000        st1h    \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
+.*:    e4848000        st1h    \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
+.*:    e49f8000        st1h    \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
+.*:    e49f8000        st1h    \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
+.*:    e49f8000        st1h    \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
+.*:    e480c000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e480c000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e480c000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e480c000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e480c001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e480c001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e480c001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e480c001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e480c01f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e480c01f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e480c01f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e480c01f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e480c800        st1h    \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
+.*:    e480c800        st1h    \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
+.*:    e480c800        st1h    \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
+.*:    e480dc00        st1h    \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
+.*:    e480dc00        st1h    \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
+.*:    e480dc00        st1h    \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
+.*:    e480c060        st1h    \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
+.*:    e480c060        st1h    \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
+.*:    e480c060        st1h    \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
+.*:    e480c3e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
+.*:    e480c3e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
+.*:    e480c3e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
+.*:    e484c000        st1h    \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
+.*:    e484c000        st1h    \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
+.*:    e484c000        st1h    \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
+.*:    e49fc000        st1h    \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
+.*:    e49fc000        st1h    \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
+.*:    e49fc000        st1h    \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
+.*:    e480a000        st1h    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e480a000        st1h    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e480a000        st1h    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e480a000        st1h    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e480a001        st1h    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e480a001        st1h    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e480a001        st1h    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e480a001        st1h    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e480a01f        st1h    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e480a01f        st1h    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e480a01f        st1h    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e480a01f        st1h    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e480a800        st1h    \{z0\.d\}, p2, \[x0, z0\.d\]
+.*:    e480a800        st1h    \{z0\.d\}, p2, \[x0, z0\.d\]
+.*:    e480a800        st1h    \{z0\.d\}, p2, \[x0, z0\.d\]
+.*:    e480bc00        st1h    \{z0\.d\}, p7, \[x0, z0\.d\]
+.*:    e480bc00        st1h    \{z0\.d\}, p7, \[x0, z0\.d\]
+.*:    e480bc00        st1h    \{z0\.d\}, p7, \[x0, z0\.d\]
+.*:    e480a060        st1h    \{z0\.d\}, p0, \[x3, z0\.d\]
+.*:    e480a060        st1h    \{z0\.d\}, p0, \[x3, z0\.d\]
+.*:    e480a060        st1h    \{z0\.d\}, p0, \[x3, z0\.d\]
+.*:    e480a3e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d\]
+.*:    e480a3e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d\]
+.*:    e480a3e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d\]
+.*:    e484a000        st1h    \{z0\.d\}, p0, \[x0, z4\.d\]
+.*:    e484a000        st1h    \{z0\.d\}, p0, \[x0, z4\.d\]
+.*:    e484a000        st1h    \{z0\.d\}, p0, \[x0, z4\.d\]
+.*:    e49fa000        st1h    \{z0\.d\}, p0, \[x0, z31\.d\]
+.*:    e49fa000        st1h    \{z0\.d\}, p0, \[x0, z31\.d\]
+.*:    e49fa000        st1h    \{z0\.d\}, p0, \[x0, z31\.d\]
+.*:    e4a04000        st1h    \{z0\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a04000        st1h    \{z0\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a04000        st1h    \{z0\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a04001        st1h    \{z1\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a04001        st1h    \{z1\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a04001        st1h    \{z1\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a0401f        st1h    \{z31\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a0401f        st1h    \{z31\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a0401f        st1h    \{z31\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a04800        st1h    \{z0\.h\}, p2, \[x0, x0, lsl #1\]
+.*:    e4a04800        st1h    \{z0\.h\}, p2, \[x0, x0, lsl #1\]
+.*:    e4a05c00        st1h    \{z0\.h\}, p7, \[x0, x0, lsl #1\]
+.*:    e4a05c00        st1h    \{z0\.h\}, p7, \[x0, x0, lsl #1\]
+.*:    e4a04060        st1h    \{z0\.h\}, p0, \[x3, x0, lsl #1\]
+.*:    e4a04060        st1h    \{z0\.h\}, p0, \[x3, x0, lsl #1\]
+.*:    e4a043e0        st1h    \{z0\.h\}, p0, \[sp, x0, lsl #1\]
+.*:    e4a043e0        st1h    \{z0\.h\}, p0, \[sp, x0, lsl #1\]
+.*:    e4a44000        st1h    \{z0\.h\}, p0, \[x0, x4, lsl #1\]
+.*:    e4a44000        st1h    \{z0\.h\}, p0, \[x0, x4, lsl #1\]
+.*:    e4be4000        st1h    \{z0\.h\}, p0, \[x0, x30, lsl #1\]
+.*:    e4be4000        st1h    \{z0\.h\}, p0, \[x0, x30, lsl #1\]
+.*:    e4a08000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, uxtw #1\]
+.*:    e4a08000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, uxtw #1\]
+.*:    e4a08000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, uxtw #1\]
+.*:    e4a08001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, uxtw #1\]
+.*:    e4a08001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, uxtw #1\]
+.*:    e4a08001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, uxtw #1\]
+.*:    e4a0801f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, uxtw #1\]
+.*:    e4a0801f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, uxtw #1\]
+.*:    e4a0801f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, uxtw #1\]
+.*:    e4a08800        st1h    \{z0\.d\}, p2, \[x0, z0\.d, uxtw #1\]
+.*:    e4a08800        st1h    \{z0\.d\}, p2, \[x0, z0\.d, uxtw #1\]
+.*:    e4a09c00        st1h    \{z0\.d\}, p7, \[x0, z0\.d, uxtw #1\]
+.*:    e4a09c00        st1h    \{z0\.d\}, p7, \[x0, z0\.d, uxtw #1\]
+.*:    e4a08060        st1h    \{z0\.d\}, p0, \[x3, z0\.d, uxtw #1\]
+.*:    e4a08060        st1h    \{z0\.d\}, p0, \[x3, z0\.d, uxtw #1\]
+.*:    e4a083e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d, uxtw #1\]
+.*:    e4a083e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d, uxtw #1\]
+.*:    e4a48000        st1h    \{z0\.d\}, p0, \[x0, z4\.d, uxtw #1\]
+.*:    e4a48000        st1h    \{z0\.d\}, p0, \[x0, z4\.d, uxtw #1\]
+.*:    e4bf8000        st1h    \{z0\.d\}, p0, \[x0, z31\.d, uxtw #1\]
+.*:    e4bf8000        st1h    \{z0\.d\}, p0, \[x0, z31\.d, uxtw #1\]
+.*:    e4a0c000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, sxtw #1\]
+.*:    e4a0c000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, sxtw #1\]
+.*:    e4a0c000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, sxtw #1\]
+.*:    e4a0c001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, sxtw #1\]
+.*:    e4a0c001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, sxtw #1\]
+.*:    e4a0c001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, sxtw #1\]
+.*:    e4a0c01f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, sxtw #1\]
+.*:    e4a0c01f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, sxtw #1\]
+.*:    e4a0c01f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, sxtw #1\]
+.*:    e4a0c800        st1h    \{z0\.d\}, p2, \[x0, z0\.d, sxtw #1\]
+.*:    e4a0c800        st1h    \{z0\.d\}, p2, \[x0, z0\.d, sxtw #1\]
+.*:    e4a0dc00        st1h    \{z0\.d\}, p7, \[x0, z0\.d, sxtw #1\]
+.*:    e4a0dc00        st1h    \{z0\.d\}, p7, \[x0, z0\.d, sxtw #1\]
+.*:    e4a0c060        st1h    \{z0\.d\}, p0, \[x3, z0\.d, sxtw #1\]
+.*:    e4a0c060        st1h    \{z0\.d\}, p0, \[x3, z0\.d, sxtw #1\]
+.*:    e4a0c3e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d, sxtw #1\]
+.*:    e4a0c3e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d, sxtw #1\]
+.*:    e4a4c000        st1h    \{z0\.d\}, p0, \[x0, z4\.d, sxtw #1\]
+.*:    e4a4c000        st1h    \{z0\.d\}, p0, \[x0, z4\.d, sxtw #1\]
+.*:    e4bfc000        st1h    \{z0\.d\}, p0, \[x0, z31\.d, sxtw #1\]
+.*:    e4bfc000        st1h    \{z0\.d\}, p0, \[x0, z31\.d, sxtw #1\]
+.*:    e4a0a000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, lsl #1\]
+.*:    e4a0a000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, lsl #1\]
+.*:    e4a0a000        st1h    \{z0\.d\}, p0, \[x0, z0\.d, lsl #1\]
+.*:    e4a0a001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, lsl #1\]
+.*:    e4a0a001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, lsl #1\]
+.*:    e4a0a001        st1h    \{z1\.d\}, p0, \[x0, z0\.d, lsl #1\]
+.*:    e4a0a01f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, lsl #1\]
+.*:    e4a0a01f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, lsl #1\]
+.*:    e4a0a01f        st1h    \{z31\.d\}, p0, \[x0, z0\.d, lsl #1\]
+.*:    e4a0a800        st1h    \{z0\.d\}, p2, \[x0, z0\.d, lsl #1\]
+.*:    e4a0a800        st1h    \{z0\.d\}, p2, \[x0, z0\.d, lsl #1\]
+.*:    e4a0bc00        st1h    \{z0\.d\}, p7, \[x0, z0\.d, lsl #1\]
+.*:    e4a0bc00        st1h    \{z0\.d\}, p7, \[x0, z0\.d, lsl #1\]
+.*:    e4a0a060        st1h    \{z0\.d\}, p0, \[x3, z0\.d, lsl #1\]
+.*:    e4a0a060        st1h    \{z0\.d\}, p0, \[x3, z0\.d, lsl #1\]
+.*:    e4a0a3e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d, lsl #1\]
+.*:    e4a0a3e0        st1h    \{z0\.d\}, p0, \[sp, z0\.d, lsl #1\]
+.*:    e4a4a000        st1h    \{z0\.d\}, p0, \[x0, z4\.d, lsl #1\]
+.*:    e4a4a000        st1h    \{z0\.d\}, p0, \[x0, z4\.d, lsl #1\]
+.*:    e4bfa000        st1h    \{z0\.d\}, p0, \[x0, z31\.d, lsl #1\]
+.*:    e4bfa000        st1h    \{z0\.d\}, p0, \[x0, z31\.d, lsl #1\]
+.*:    e4c04000        st1h    \{z0\.s\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c04000        st1h    \{z0\.s\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c04000        st1h    \{z0\.s\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c04001        st1h    \{z1\.s\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c04001        st1h    \{z1\.s\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c04001        st1h    \{z1\.s\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c0401f        st1h    \{z31\.s\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c0401f        st1h    \{z31\.s\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c0401f        st1h    \{z31\.s\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c04800        st1h    \{z0\.s\}, p2, \[x0, x0, lsl #1\]
+.*:    e4c04800        st1h    \{z0\.s\}, p2, \[x0, x0, lsl #1\]
+.*:    e4c05c00        st1h    \{z0\.s\}, p7, \[x0, x0, lsl #1\]
+.*:    e4c05c00        st1h    \{z0\.s\}, p7, \[x0, x0, lsl #1\]
+.*:    e4c04060        st1h    \{z0\.s\}, p0, \[x3, x0, lsl #1\]
+.*:    e4c04060        st1h    \{z0\.s\}, p0, \[x3, x0, lsl #1\]
+.*:    e4c043e0        st1h    \{z0\.s\}, p0, \[sp, x0, lsl #1\]
+.*:    e4c043e0        st1h    \{z0\.s\}, p0, \[sp, x0, lsl #1\]
+.*:    e4c44000        st1h    \{z0\.s\}, p0, \[x0, x4, lsl #1\]
+.*:    e4c44000        st1h    \{z0\.s\}, p0, \[x0, x4, lsl #1\]
+.*:    e4de4000        st1h    \{z0\.s\}, p0, \[x0, x30, lsl #1\]
+.*:    e4de4000        st1h    \{z0\.s\}, p0, \[x0, x30, lsl #1\]
+.*:    e4c08000        st1h    \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4c08000        st1h    \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4c08000        st1h    \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4c08000        st1h    \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4c08001        st1h    \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4c08001        st1h    \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4c08001        st1h    \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4c08001        st1h    \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4c0801f        st1h    \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4c0801f        st1h    \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4c0801f        st1h    \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4c0801f        st1h    \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e4c08800        st1h    \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
+.*:    e4c08800        st1h    \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
+.*:    e4c08800        st1h    \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
+.*:    e4c09c00        st1h    \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
+.*:    e4c09c00        st1h    \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
+.*:    e4c09c00        st1h    \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
+.*:    e4c08060        st1h    \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
+.*:    e4c08060        st1h    \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
+.*:    e4c08060        st1h    \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
+.*:    e4c083e0        st1h    \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
+.*:    e4c083e0        st1h    \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
+.*:    e4c083e0        st1h    \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
+.*:    e4c48000        st1h    \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
+.*:    e4c48000        st1h    \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
+.*:    e4c48000        st1h    \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
+.*:    e4df8000        st1h    \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
+.*:    e4df8000        st1h    \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
+.*:    e4df8000        st1h    \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
+.*:    e4c0c000        st1h    \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e4c0c000        st1h    \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e4c0c000        st1h    \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e4c0c000        st1h    \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e4c0c001        st1h    \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e4c0c001        st1h    \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e4c0c001        st1h    \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e4c0c001        st1h    \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e4c0c01f        st1h    \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e4c0c01f        st1h    \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e4c0c01f        st1h    \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e4c0c01f        st1h    \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e4c0c800        st1h    \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
+.*:    e4c0c800        st1h    \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
+.*:    e4c0c800        st1h    \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
+.*:    e4c0dc00        st1h    \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
+.*:    e4c0dc00        st1h    \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
+.*:    e4c0dc00        st1h    \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
+.*:    e4c0c060        st1h    \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
+.*:    e4c0c060        st1h    \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
+.*:    e4c0c060        st1h    \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
+.*:    e4c0c3e0        st1h    \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
+.*:    e4c0c3e0        st1h    \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
+.*:    e4c0c3e0        st1h    \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
+.*:    e4c4c000        st1h    \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
+.*:    e4c4c000        st1h    \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
+.*:    e4c4c000        st1h    \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
+.*:    e4dfc000        st1h    \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
+.*:    e4dfc000        st1h    \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
+.*:    e4dfc000        st1h    \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
+.*:    e4e04000        st1h    \{z0\.d\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e04000        st1h    \{z0\.d\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e04000        st1h    \{z0\.d\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e04001        st1h    \{z1\.d\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e04001        st1h    \{z1\.d\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e04001        st1h    \{z1\.d\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e0401f        st1h    \{z31\.d\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e0401f        st1h    \{z31\.d\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e0401f        st1h    \{z31\.d\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e04800        st1h    \{z0\.d\}, p2, \[x0, x0, lsl #1\]
+.*:    e4e04800        st1h    \{z0\.d\}, p2, \[x0, x0, lsl #1\]
+.*:    e4e05c00        st1h    \{z0\.d\}, p7, \[x0, x0, lsl #1\]
+.*:    e4e05c00        st1h    \{z0\.d\}, p7, \[x0, x0, lsl #1\]
+.*:    e4e04060        st1h    \{z0\.d\}, p0, \[x3, x0, lsl #1\]
+.*:    e4e04060        st1h    \{z0\.d\}, p0, \[x3, x0, lsl #1\]
+.*:    e4e043e0        st1h    \{z0\.d\}, p0, \[sp, x0, lsl #1\]
+.*:    e4e043e0        st1h    \{z0\.d\}, p0, \[sp, x0, lsl #1\]
+.*:    e4e44000        st1h    \{z0\.d\}, p0, \[x0, x4, lsl #1\]
+.*:    e4e44000        st1h    \{z0\.d\}, p0, \[x0, x4, lsl #1\]
+.*:    e4fe4000        st1h    \{z0\.d\}, p0, \[x0, x30, lsl #1\]
+.*:    e4fe4000        st1h    \{z0\.d\}, p0, \[x0, x30, lsl #1\]
+.*:    e4e08000        st1h    \{z0\.s\}, p0, \[x0, z0\.s, uxtw #1\]
+.*:    e4e08000        st1h    \{z0\.s\}, p0, \[x0, z0\.s, uxtw #1\]
+.*:    e4e08000        st1h    \{z0\.s\}, p0, \[x0, z0\.s, uxtw #1\]
+.*:    e4e08001        st1h    \{z1\.s\}, p0, \[x0, z0\.s, uxtw #1\]
+.*:    e4e08001        st1h    \{z1\.s\}, p0, \[x0, z0\.s, uxtw #1\]
+.*:    e4e08001        st1h    \{z1\.s\}, p0, \[x0, z0\.s, uxtw #1\]
+.*:    e4e0801f        st1h    \{z31\.s\}, p0, \[x0, z0\.s, uxtw #1\]
+.*:    e4e0801f        st1h    \{z31\.s\}, p0, \[x0, z0\.s, uxtw #1\]
+.*:    e4e0801f        st1h    \{z31\.s\}, p0, \[x0, z0\.s, uxtw #1\]
+.*:    e4e08800        st1h    \{z0\.s\}, p2, \[x0, z0\.s, uxtw #1\]
+.*:    e4e08800        st1h    \{z0\.s\}, p2, \[x0, z0\.s, uxtw #1\]
+.*:    e4e09c00        st1h    \{z0\.s\}, p7, \[x0, z0\.s, uxtw #1\]
+.*:    e4e09c00        st1h    \{z0\.s\}, p7, \[x0, z0\.s, uxtw #1\]
+.*:    e4e08060        st1h    \{z0\.s\}, p0, \[x3, z0\.s, uxtw #1\]
+.*:    e4e08060        st1h    \{z0\.s\}, p0, \[x3, z0\.s, uxtw #1\]
+.*:    e4e083e0        st1h    \{z0\.s\}, p0, \[sp, z0\.s, uxtw #1\]
+.*:    e4e083e0        st1h    \{z0\.s\}, p0, \[sp, z0\.s, uxtw #1\]
+.*:    e4e48000        st1h    \{z0\.s\}, p0, \[x0, z4\.s, uxtw #1\]
+.*:    e4e48000        st1h    \{z0\.s\}, p0, \[x0, z4\.s, uxtw #1\]
+.*:    e4ff8000        st1h    \{z0\.s\}, p0, \[x0, z31\.s, uxtw #1\]
+.*:    e4ff8000        st1h    \{z0\.s\}, p0, \[x0, z31\.s, uxtw #1\]
+.*:    e4e0c000        st1h    \{z0\.s\}, p0, \[x0, z0\.s, sxtw #1\]
+.*:    e4e0c000        st1h    \{z0\.s\}, p0, \[x0, z0\.s, sxtw #1\]
+.*:    e4e0c000        st1h    \{z0\.s\}, p0, \[x0, z0\.s, sxtw #1\]
+.*:    e4e0c001        st1h    \{z1\.s\}, p0, \[x0, z0\.s, sxtw #1\]
+.*:    e4e0c001        st1h    \{z1\.s\}, p0, \[x0, z0\.s, sxtw #1\]
+.*:    e4e0c001        st1h    \{z1\.s\}, p0, \[x0, z0\.s, sxtw #1\]
+.*:    e4e0c01f        st1h    \{z31\.s\}, p0, \[x0, z0\.s, sxtw #1\]
+.*:    e4e0c01f        st1h    \{z31\.s\}, p0, \[x0, z0\.s, sxtw #1\]
+.*:    e4e0c01f        st1h    \{z31\.s\}, p0, \[x0, z0\.s, sxtw #1\]
+.*:    e4e0c800        st1h    \{z0\.s\}, p2, \[x0, z0\.s, sxtw #1\]
+.*:    e4e0c800        st1h    \{z0\.s\}, p2, \[x0, z0\.s, sxtw #1\]
+.*:    e4e0dc00        st1h    \{z0\.s\}, p7, \[x0, z0\.s, sxtw #1\]
+.*:    e4e0dc00        st1h    \{z0\.s\}, p7, \[x0, z0\.s, sxtw #1\]
+.*:    e4e0c060        st1h    \{z0\.s\}, p0, \[x3, z0\.s, sxtw #1\]
+.*:    e4e0c060        st1h    \{z0\.s\}, p0, \[x3, z0\.s, sxtw #1\]
+.*:    e4e0c3e0        st1h    \{z0\.s\}, p0, \[sp, z0\.s, sxtw #1\]
+.*:    e4e0c3e0        st1h    \{z0\.s\}, p0, \[sp, z0\.s, sxtw #1\]
+.*:    e4e4c000        st1h    \{z0\.s\}, p0, \[x0, z4\.s, sxtw #1\]
+.*:    e4e4c000        st1h    \{z0\.s\}, p0, \[x0, z4\.s, sxtw #1\]
+.*:    e4ffc000        st1h    \{z0\.s\}, p0, \[x0, z31\.s, sxtw #1\]
+.*:    e4ffc000        st1h    \{z0\.s\}, p0, \[x0, z31\.s, sxtw #1\]
 .*:    e4a0e000        st1h    \{z0\.h\}, p0, \[x0\]
 .*:    e4a0e000        st1h    \{z0\.h\}, p0, \[x0\]
 .*:    e4a0e000        st1h    \{z0\.h\}, p0, \[x0\]
@@ -29924,14 +29924,14 @@ Disassembly of section .*:
 .*:    e4a0e3e0        st1h    \{z0\.h\}, p0, \[sp\]
 .*:    e4a0e3e0        st1h    \{z0\.h\}, p0, \[sp\]
 .*:    e4a0e3e0        st1h    \{z0\.h\}, p0, \[sp\]
-.*:    e4a7e000        st1h    \{z0\.h\}, p0, \[x0,#7,mul vl\]
-.*:    e4a7e000        st1h    \{z0\.h\}, p0, \[x0,#7,mul vl\]
-.*:    e4a8e000        st1h    \{z0\.h\}, p0, \[x0,#-8,mul vl\]
-.*:    e4a8e000        st1h    \{z0\.h\}, p0, \[x0,#-8,mul vl\]
-.*:    e4a9e000        st1h    \{z0\.h\}, p0, \[x0,#-7,mul vl\]
-.*:    e4a9e000        st1h    \{z0\.h\}, p0, \[x0,#-7,mul vl\]
-.*:    e4afe000        st1h    \{z0\.h\}, p0, \[x0,#-1,mul vl\]
-.*:    e4afe000        st1h    \{z0\.h\}, p0, \[x0,#-1,mul vl\]
+.*:    e4a7e000        st1h    \{z0\.h\}, p0, \[x0, #7, mul vl\]
+.*:    e4a7e000        st1h    \{z0\.h\}, p0, \[x0, #7, mul vl\]
+.*:    e4a8e000        st1h    \{z0\.h\}, p0, \[x0, #-8, mul vl\]
+.*:    e4a8e000        st1h    \{z0\.h\}, p0, \[x0, #-8, mul vl\]
+.*:    e4a9e000        st1h    \{z0\.h\}, p0, \[x0, #-7, mul vl\]
+.*:    e4a9e000        st1h    \{z0\.h\}, p0, \[x0, #-7, mul vl\]
+.*:    e4afe000        st1h    \{z0\.h\}, p0, \[x0, #-1, mul vl\]
+.*:    e4afe000        st1h    \{z0\.h\}, p0, \[x0, #-1, mul vl\]
 .*:    e4c0a000        st1h    \{z0\.d\}, p0, \[z0\.d\]
 .*:    e4c0a000        st1h    \{z0\.d\}, p0, \[z0\.d\]
 .*:    e4c0a000        st1h    \{z0\.d\}, p0, \[z0\.d\]
@@ -29956,14 +29956,14 @@ Disassembly of section .*:
 .*:    e4c0a3e0        st1h    \{z0\.d\}, p0, \[z31\.d\]
 .*:    e4c0a3e0        st1h    \{z0\.d\}, p0, \[z31\.d\]
 .*:    e4c0a3e0        st1h    \{z0\.d\}, p0, \[z31\.d\]
-.*:    e4cfa000        st1h    \{z0\.d\}, p0, \[z0\.d,#30\]
-.*:    e4cfa000        st1h    \{z0\.d\}, p0, \[z0\.d,#30\]
-.*:    e4d0a000        st1h    \{z0\.d\}, p0, \[z0\.d,#32\]
-.*:    e4d0a000        st1h    \{z0\.d\}, p0, \[z0\.d,#32\]
-.*:    e4d1a000        st1h    \{z0\.d\}, p0, \[z0\.d,#34\]
-.*:    e4d1a000        st1h    \{z0\.d\}, p0, \[z0\.d,#34\]
-.*:    e4dfa000        st1h    \{z0\.d\}, p0, \[z0\.d,#62\]
-.*:    e4dfa000        st1h    \{z0\.d\}, p0, \[z0\.d,#62\]
+.*:    e4cfa000        st1h    \{z0\.d\}, p0, \[z0\.d, #30\]
+.*:    e4cfa000        st1h    \{z0\.d\}, p0, \[z0\.d, #30\]
+.*:    e4d0a000        st1h    \{z0\.d\}, p0, \[z0\.d, #32\]
+.*:    e4d0a000        st1h    \{z0\.d\}, p0, \[z0\.d, #32\]
+.*:    e4d1a000        st1h    \{z0\.d\}, p0, \[z0\.d, #34\]
+.*:    e4d1a000        st1h    \{z0\.d\}, p0, \[z0\.d, #34\]
+.*:    e4dfa000        st1h    \{z0\.d\}, p0, \[z0\.d, #62\]
+.*:    e4dfa000        st1h    \{z0\.d\}, p0, \[z0\.d, #62\]
 .*:    e4c0e000        st1h    \{z0\.s\}, p0, \[x0\]
 .*:    e4c0e000        st1h    \{z0\.s\}, p0, \[x0\]
 .*:    e4c0e000        st1h    \{z0\.s\}, p0, \[x0\]
@@ -29995,14 +29995,14 @@ Disassembly of section .*:
 .*:    e4c0e3e0        st1h    \{z0\.s\}, p0, \[sp\]
 .*:    e4c0e3e0        st1h    \{z0\.s\}, p0, \[sp\]
 .*:    e4c0e3e0        st1h    \{z0\.s\}, p0, \[sp\]
-.*:    e4c7e000        st1h    \{z0\.s\}, p0, \[x0,#7,mul vl\]
-.*:    e4c7e000        st1h    \{z0\.s\}, p0, \[x0,#7,mul vl\]
-.*:    e4c8e000        st1h    \{z0\.s\}, p0, \[x0,#-8,mul vl\]
-.*:    e4c8e000        st1h    \{z0\.s\}, p0, \[x0,#-8,mul vl\]
-.*:    e4c9e000        st1h    \{z0\.s\}, p0, \[x0,#-7,mul vl\]
-.*:    e4c9e000        st1h    \{z0\.s\}, p0, \[x0,#-7,mul vl\]
-.*:    e4cfe000        st1h    \{z0\.s\}, p0, \[x0,#-1,mul vl\]
-.*:    e4cfe000        st1h    \{z0\.s\}, p0, \[x0,#-1,mul vl\]
+.*:    e4c7e000        st1h    \{z0\.s\}, p0, \[x0, #7, mul vl\]
+.*:    e4c7e000        st1h    \{z0\.s\}, p0, \[x0, #7, mul vl\]
+.*:    e4c8e000        st1h    \{z0\.s\}, p0, \[x0, #-8, mul vl\]
+.*:    e4c8e000        st1h    \{z0\.s\}, p0, \[x0, #-8, mul vl\]
+.*:    e4c9e000        st1h    \{z0\.s\}, p0, \[x0, #-7, mul vl\]
+.*:    e4c9e000        st1h    \{z0\.s\}, p0, \[x0, #-7, mul vl\]
+.*:    e4cfe000        st1h    \{z0\.s\}, p0, \[x0, #-1, mul vl\]
+.*:    e4cfe000        st1h    \{z0\.s\}, p0, \[x0, #-1, mul vl\]
 .*:    e4e0a000        st1h    \{z0\.s\}, p0, \[z0\.s\]
 .*:    e4e0a000        st1h    \{z0\.s\}, p0, \[z0\.s\]
 .*:    e4e0a000        st1h    \{z0\.s\}, p0, \[z0\.s\]
@@ -30027,14 +30027,14 @@ Disassembly of section .*:
 .*:    e4e0a3e0        st1h    \{z0\.s\}, p0, \[z31\.s\]
 .*:    e4e0a3e0        st1h    \{z0\.s\}, p0, \[z31\.s\]
 .*:    e4e0a3e0        st1h    \{z0\.s\}, p0, \[z31\.s\]
-.*:    e4efa000        st1h    \{z0\.s\}, p0, \[z0\.s,#30\]
-.*:    e4efa000        st1h    \{z0\.s\}, p0, \[z0\.s,#30\]
-.*:    e4f0a000        st1h    \{z0\.s\}, p0, \[z0\.s,#32\]
-.*:    e4f0a000        st1h    \{z0\.s\}, p0, \[z0\.s,#32\]
-.*:    e4f1a000        st1h    \{z0\.s\}, p0, \[z0\.s,#34\]
-.*:    e4f1a000        st1h    \{z0\.s\}, p0, \[z0\.s,#34\]
-.*:    e4ffa000        st1h    \{z0\.s\}, p0, \[z0\.s,#62\]
-.*:    e4ffa000        st1h    \{z0\.s\}, p0, \[z0\.s,#62\]
+.*:    e4efa000        st1h    \{z0\.s\}, p0, \[z0\.s, #30\]
+.*:    e4efa000        st1h    \{z0\.s\}, p0, \[z0\.s, #30\]
+.*:    e4f0a000        st1h    \{z0\.s\}, p0, \[z0\.s, #32\]
+.*:    e4f0a000        st1h    \{z0\.s\}, p0, \[z0\.s, #32\]
+.*:    e4f1a000        st1h    \{z0\.s\}, p0, \[z0\.s, #34\]
+.*:    e4f1a000        st1h    \{z0\.s\}, p0, \[z0\.s, #34\]
+.*:    e4ffa000        st1h    \{z0\.s\}, p0, \[z0\.s, #62\]
+.*:    e4ffa000        st1h    \{z0\.s\}, p0, \[z0\.s, #62\]
 .*:    e4e0e000        st1h    \{z0\.d\}, p0, \[x0\]
 .*:    e4e0e000        st1h    \{z0\.d\}, p0, \[x0\]
 .*:    e4e0e000        st1h    \{z0\.d\}, p0, \[x0\]
@@ -30066,311 +30066,311 @@ Disassembly of section .*:
 .*:    e4e0e3e0        st1h    \{z0\.d\}, p0, \[sp\]
 .*:    e4e0e3e0        st1h    \{z0\.d\}, p0, \[sp\]
 .*:    e4e0e3e0        st1h    \{z0\.d\}, p0, \[sp\]
-.*:    e4e7e000        st1h    \{z0\.d\}, p0, \[x0,#7,mul vl\]
-.*:    e4e7e000        st1h    \{z0\.d\}, p0, \[x0,#7,mul vl\]
-.*:    e4e8e000        st1h    \{z0\.d\}, p0, \[x0,#-8,mul vl\]
-.*:    e4e8e000        st1h    \{z0\.d\}, p0, \[x0,#-8,mul vl\]
-.*:    e4e9e000        st1h    \{z0\.d\}, p0, \[x0,#-7,mul vl\]
-.*:    e4e9e000        st1h    \{z0\.d\}, p0, \[x0,#-7,mul vl\]
-.*:    e4efe000        st1h    \{z0\.d\}, p0, \[x0,#-1,mul vl\]
-.*:    e4efe000        st1h    \{z0\.d\}, p0, \[x0,#-1,mul vl\]
-.*:    e5008000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5008000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5008000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5008000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5008001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5008001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5008001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5008001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e500801f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e500801f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e500801f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e500801f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,uxtw\]
-.*:    e5008800        st1w    \{z0\.d\}, p2, \[x0,z0\.d,uxtw\]
-.*:    e5008800        st1w    \{z0\.d\}, p2, \[x0,z0\.d,uxtw\]
-.*:    e5008800        st1w    \{z0\.d\}, p2, \[x0,z0\.d,uxtw\]
-.*:    e5009c00        st1w    \{z0\.d\}, p7, \[x0,z0\.d,uxtw\]
-.*:    e5009c00        st1w    \{z0\.d\}, p7, \[x0,z0\.d,uxtw\]
-.*:    e5009c00        st1w    \{z0\.d\}, p7, \[x0,z0\.d,uxtw\]
-.*:    e5008060        st1w    \{z0\.d\}, p0, \[x3,z0\.d,uxtw\]
-.*:    e5008060        st1w    \{z0\.d\}, p0, \[x3,z0\.d,uxtw\]
-.*:    e5008060        st1w    \{z0\.d\}, p0, \[x3,z0\.d,uxtw\]
-.*:    e50083e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d,uxtw\]
-.*:    e50083e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d,uxtw\]
-.*:    e50083e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d,uxtw\]
-.*:    e5048000        st1w    \{z0\.d\}, p0, \[x0,z4\.d,uxtw\]
-.*:    e5048000        st1w    \{z0\.d\}, p0, \[x0,z4\.d,uxtw\]
-.*:    e5048000        st1w    \{z0\.d\}, p0, \[x0,z4\.d,uxtw\]
-.*:    e51f8000        st1w    \{z0\.d\}, p0, \[x0,z31\.d,uxtw\]
-.*:    e51f8000        st1w    \{z0\.d\}, p0, \[x0,z31\.d,uxtw\]
-.*:    e51f8000        st1w    \{z0\.d\}, p0, \[x0,z31\.d,uxtw\]
-.*:    e500c000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e500c000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e500c000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e500c000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e500c001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e500c001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e500c001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e500c001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e500c01f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e500c01f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e500c01f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e500c01f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,sxtw\]
-.*:    e500c800        st1w    \{z0\.d\}, p2, \[x0,z0\.d,sxtw\]
-.*:    e500c800        st1w    \{z0\.d\}, p2, \[x0,z0\.d,sxtw\]
-.*:    e500c800        st1w    \{z0\.d\}, p2, \[x0,z0\.d,sxtw\]
-.*:    e500dc00        st1w    \{z0\.d\}, p7, \[x0,z0\.d,sxtw\]
-.*:    e500dc00        st1w    \{z0\.d\}, p7, \[x0,z0\.d,sxtw\]
-.*:    e500dc00        st1w    \{z0\.d\}, p7, \[x0,z0\.d,sxtw\]
-.*:    e500c060        st1w    \{z0\.d\}, p0, \[x3,z0\.d,sxtw\]
-.*:    e500c060        st1w    \{z0\.d\}, p0, \[x3,z0\.d,sxtw\]
-.*:    e500c060        st1w    \{z0\.d\}, p0, \[x3,z0\.d,sxtw\]
-.*:    e500c3e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d,sxtw\]
-.*:    e500c3e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d,sxtw\]
-.*:    e500c3e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d,sxtw\]
-.*:    e504c000        st1w    \{z0\.d\}, p0, \[x0,z4\.d,sxtw\]
-.*:    e504c000        st1w    \{z0\.d\}, p0, \[x0,z4\.d,sxtw\]
-.*:    e504c000        st1w    \{z0\.d\}, p0, \[x0,z4\.d,sxtw\]
-.*:    e51fc000        st1w    \{z0\.d\}, p0, \[x0,z31\.d,sxtw\]
-.*:    e51fc000        st1w    \{z0\.d\}, p0, \[x0,z31\.d,sxtw\]
-.*:    e51fc000        st1w    \{z0\.d\}, p0, \[x0,z31\.d,sxtw\]
-.*:    e500a000        st1w    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e500a000        st1w    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e500a000        st1w    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e500a000        st1w    \{z0\.d\}, p0, \[x0,z0\.d\]
-.*:    e500a001        st1w    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e500a001        st1w    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e500a001        st1w    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e500a001        st1w    \{z1\.d\}, p0, \[x0,z0\.d\]
-.*:    e500a01f        st1w    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e500a01f        st1w    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e500a01f        st1w    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e500a01f        st1w    \{z31\.d\}, p0, \[x0,z0\.d\]
-.*:    e500a800        st1w    \{z0\.d\}, p2, \[x0,z0\.d\]
-.*:    e500a800        st1w    \{z0\.d\}, p2, \[x0,z0\.d\]
-.*:    e500a800        st1w    \{z0\.d\}, p2, \[x0,z0\.d\]
-.*:    e500bc00        st1w    \{z0\.d\}, p7, \[x0,z0\.d\]
-.*:    e500bc00        st1w    \{z0\.d\}, p7, \[x0,z0\.d\]
-.*:    e500bc00        st1w    \{z0\.d\}, p7, \[x0,z0\.d\]
-.*:    e500a060        st1w    \{z0\.d\}, p0, \[x3,z0\.d\]
-.*:    e500a060        st1w    \{z0\.d\}, p0, \[x3,z0\.d\]
-.*:    e500a060        st1w    \{z0\.d\}, p0, \[x3,z0\.d\]
-.*:    e500a3e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d\]
-.*:    e500a3e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d\]
-.*:    e500a3e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d\]
-.*:    e504a000        st1w    \{z0\.d\}, p0, \[x0,z4\.d\]
-.*:    e504a000        st1w    \{z0\.d\}, p0, \[x0,z4\.d\]
-.*:    e504a000        st1w    \{z0\.d\}, p0, \[x0,z4\.d\]
-.*:    e51fa000        st1w    \{z0\.d\}, p0, \[x0,z31\.d\]
-.*:    e51fa000        st1w    \{z0\.d\}, p0, \[x0,z31\.d\]
-.*:    e51fa000        st1w    \{z0\.d\}, p0, \[x0,z31\.d\]
-.*:    e5208000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,uxtw #2\]
-.*:    e5208000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,uxtw #2\]
-.*:    e5208000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,uxtw #2\]
-.*:    e5208001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,uxtw #2\]
-.*:    e5208001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,uxtw #2\]
-.*:    e5208001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,uxtw #2\]
-.*:    e520801f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,uxtw #2\]
-.*:    e520801f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,uxtw #2\]
-.*:    e520801f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,uxtw #2\]
-.*:    e5208800        st1w    \{z0\.d\}, p2, \[x0,z0\.d,uxtw #2\]
-.*:    e5208800        st1w    \{z0\.d\}, p2, \[x0,z0\.d,uxtw #2\]
-.*:    e5209c00        st1w    \{z0\.d\}, p7, \[x0,z0\.d,uxtw #2\]
-.*:    e5209c00        st1w    \{z0\.d\}, p7, \[x0,z0\.d,uxtw #2\]
-.*:    e5208060        st1w    \{z0\.d\}, p0, \[x3,z0\.d,uxtw #2\]
-.*:    e5208060        st1w    \{z0\.d\}, p0, \[x3,z0\.d,uxtw #2\]
-.*:    e52083e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d,uxtw #2\]
-.*:    e52083e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d,uxtw #2\]
-.*:    e5248000        st1w    \{z0\.d\}, p0, \[x0,z4\.d,uxtw #2\]
-.*:    e5248000        st1w    \{z0\.d\}, p0, \[x0,z4\.d,uxtw #2\]
-.*:    e53f8000        st1w    \{z0\.d\}, p0, \[x0,z31\.d,uxtw #2\]
-.*:    e53f8000        st1w    \{z0\.d\}, p0, \[x0,z31\.d,uxtw #2\]
-.*:    e520c000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,sxtw #2\]
-.*:    e520c000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,sxtw #2\]
-.*:    e520c000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,sxtw #2\]
-.*:    e520c001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,sxtw #2\]
-.*:    e520c001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,sxtw #2\]
-.*:    e520c001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,sxtw #2\]
-.*:    e520c01f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,sxtw #2\]
-.*:    e520c01f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,sxtw #2\]
-.*:    e520c01f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,sxtw #2\]
-.*:    e520c800        st1w    \{z0\.d\}, p2, \[x0,z0\.d,sxtw #2\]
-.*:    e520c800        st1w    \{z0\.d\}, p2, \[x0,z0\.d,sxtw #2\]
-.*:    e520dc00        st1w    \{z0\.d\}, p7, \[x0,z0\.d,sxtw #2\]
-.*:    e520dc00        st1w    \{z0\.d\}, p7, \[x0,z0\.d,sxtw #2\]
-.*:    e520c060        st1w    \{z0\.d\}, p0, \[x3,z0\.d,sxtw #2\]
-.*:    e520c060        st1w    \{z0\.d\}, p0, \[x3,z0\.d,sxtw #2\]
-.*:    e520c3e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d,sxtw #2\]
-.*:    e520c3e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d,sxtw #2\]
-.*:    e524c000        st1w    \{z0\.d\}, p0, \[x0,z4\.d,sxtw #2\]
-.*:    e524c000        st1w    \{z0\.d\}, p0, \[x0,z4\.d,sxtw #2\]
-.*:    e53fc000        st1w    \{z0\.d\}, p0, \[x0,z31\.d,sxtw #2\]
-.*:    e53fc000        st1w    \{z0\.d\}, p0, \[x0,z31\.d,sxtw #2\]
-.*:    e520a000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,lsl #2\]
-.*:    e520a000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,lsl #2\]
-.*:    e520a000        st1w    \{z0\.d\}, p0, \[x0,z0\.d,lsl #2\]
-.*:    e520a001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,lsl #2\]
-.*:    e520a001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,lsl #2\]
-.*:    e520a001        st1w    \{z1\.d\}, p0, \[x0,z0\.d,lsl #2\]
-.*:    e520a01f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,lsl #2\]
-.*:    e520a01f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,lsl #2\]
-.*:    e520a01f        st1w    \{z31\.d\}, p0, \[x0,z0\.d,lsl #2\]
-.*:    e520a800        st1w    \{z0\.d\}, p2, \[x0,z0\.d,lsl #2\]
-.*:    e520a800        st1w    \{z0\.d\}, p2, \[x0,z0\.d,lsl #2\]
-.*:    e520bc00        st1w    \{z0\.d\}, p7, \[x0,z0\.d,lsl #2\]
-.*:    e520bc00        st1w    \{z0\.d\}, p7, \[x0,z0\.d,lsl #2\]
-.*:    e520a060        st1w    \{z0\.d\}, p0, \[x3,z0\.d,lsl #2\]
-.*:    e520a060        st1w    \{z0\.d\}, p0, \[x3,z0\.d,lsl #2\]
-.*:    e520a3e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d,lsl #2\]
-.*:    e520a3e0        st1w    \{z0\.d\}, p0, \[sp,z0\.d,lsl #2\]
-.*:    e524a000        st1w    \{z0\.d\}, p0, \[x0,z4\.d,lsl #2\]
-.*:    e524a000        st1w    \{z0\.d\}, p0, \[x0,z4\.d,lsl #2\]
-.*:    e53fa000        st1w    \{z0\.d\}, p0, \[x0,z31\.d,lsl #2\]
-.*:    e53fa000        st1w    \{z0\.d\}, p0, \[x0,z31\.d,lsl #2\]
-.*:    e5404000        st1w    \{z0\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5404000        st1w    \{z0\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5404000        st1w    \{z0\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5404001        st1w    \{z1\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5404001        st1w    \{z1\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5404001        st1w    \{z1\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e540401f        st1w    \{z31\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e540401f        st1w    \{z31\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e540401f        st1w    \{z31\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5404800        st1w    \{z0\.s\}, p2, \[x0,x0,lsl #2\]
-.*:    e5404800        st1w    \{z0\.s\}, p2, \[x0,x0,lsl #2\]
-.*:    e5405c00        st1w    \{z0\.s\}, p7, \[x0,x0,lsl #2\]
-.*:    e5405c00        st1w    \{z0\.s\}, p7, \[x0,x0,lsl #2\]
-.*:    e5404060        st1w    \{z0\.s\}, p0, \[x3,x0,lsl #2\]
-.*:    e5404060        st1w    \{z0\.s\}, p0, \[x3,x0,lsl #2\]
-.*:    e54043e0        st1w    \{z0\.s\}, p0, \[sp,x0,lsl #2\]
-.*:    e54043e0        st1w    \{z0\.s\}, p0, \[sp,x0,lsl #2\]
-.*:    e5444000        st1w    \{z0\.s\}, p0, \[x0,x4,lsl #2\]
-.*:    e5444000        st1w    \{z0\.s\}, p0, \[x0,x4,lsl #2\]
-.*:    e55e4000        st1w    \{z0\.s\}, p0, \[x0,x30,lsl #2\]
-.*:    e55e4000        st1w    \{z0\.s\}, p0, \[x0,x30,lsl #2\]
-.*:    e5408000        st1w    \{z0\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e5408000        st1w    \{z0\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e5408000        st1w    \{z0\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e5408000        st1w    \{z0\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e5408001        st1w    \{z1\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e5408001        st1w    \{z1\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e5408001        st1w    \{z1\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e5408001        st1w    \{z1\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e540801f        st1w    \{z31\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e540801f        st1w    \{z31\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e540801f        st1w    \{z31\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e540801f        st1w    \{z31\.s\}, p0, \[x0,z0\.s,uxtw\]
-.*:    e5408800        st1w    \{z0\.s\}, p2, \[x0,z0\.s,uxtw\]
-.*:    e5408800        st1w    \{z0\.s\}, p2, \[x0,z0\.s,uxtw\]
-.*:    e5408800        st1w    \{z0\.s\}, p2, \[x0,z0\.s,uxtw\]
-.*:    e5409c00        st1w    \{z0\.s\}, p7, \[x0,z0\.s,uxtw\]
-.*:    e5409c00        st1w    \{z0\.s\}, p7, \[x0,z0\.s,uxtw\]
-.*:    e5409c00        st1w    \{z0\.s\}, p7, \[x0,z0\.s,uxtw\]
-.*:    e5408060        st1w    \{z0\.s\}, p0, \[x3,z0\.s,uxtw\]
-.*:    e5408060        st1w    \{z0\.s\}, p0, \[x3,z0\.s,uxtw\]
-.*:    e5408060        st1w    \{z0\.s\}, p0, \[x3,z0\.s,uxtw\]
-.*:    e54083e0        st1w    \{z0\.s\}, p0, \[sp,z0\.s,uxtw\]
-.*:    e54083e0        st1w    \{z0\.s\}, p0, \[sp,z0\.s,uxtw\]
-.*:    e54083e0        st1w    \{z0\.s\}, p0, \[sp,z0\.s,uxtw\]
-.*:    e5448000        st1w    \{z0\.s\}, p0, \[x0,z4\.s,uxtw\]
-.*:    e5448000        st1w    \{z0\.s\}, p0, \[x0,z4\.s,uxtw\]
-.*:    e5448000        st1w    \{z0\.s\}, p0, \[x0,z4\.s,uxtw\]
-.*:    e55f8000        st1w    \{z0\.s\}, p0, \[x0,z31\.s,uxtw\]
-.*:    e55f8000        st1w    \{z0\.s\}, p0, \[x0,z31\.s,uxtw\]
-.*:    e55f8000        st1w    \{z0\.s\}, p0, \[x0,z31\.s,uxtw\]
-.*:    e540c000        st1w    \{z0\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e540c000        st1w    \{z0\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e540c000        st1w    \{z0\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e540c000        st1w    \{z0\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e540c001        st1w    \{z1\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e540c001        st1w    \{z1\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e540c001        st1w    \{z1\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e540c001        st1w    \{z1\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e540c01f        st1w    \{z31\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e540c01f        st1w    \{z31\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e540c01f        st1w    \{z31\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e540c01f        st1w    \{z31\.s\}, p0, \[x0,z0\.s,sxtw\]
-.*:    e540c800        st1w    \{z0\.s\}, p2, \[x0,z0\.s,sxtw\]
-.*:    e540c800        st1w    \{z0\.s\}, p2, \[x0,z0\.s,sxtw\]
-.*:    e540c800        st1w    \{z0\.s\}, p2, \[x0,z0\.s,sxtw\]
-.*:    e540dc00        st1w    \{z0\.s\}, p7, \[x0,z0\.s,sxtw\]
-.*:    e540dc00        st1w    \{z0\.s\}, p7, \[x0,z0\.s,sxtw\]
-.*:    e540dc00        st1w    \{z0\.s\}, p7, \[x0,z0\.s,sxtw\]
-.*:    e540c060        st1w    \{z0\.s\}, p0, \[x3,z0\.s,sxtw\]
-.*:    e540c060        st1w    \{z0\.s\}, p0, \[x3,z0\.s,sxtw\]
-.*:    e540c060        st1w    \{z0\.s\}, p0, \[x3,z0\.s,sxtw\]
-.*:    e540c3e0        st1w    \{z0\.s\}, p0, \[sp,z0\.s,sxtw\]
-.*:    e540c3e0        st1w    \{z0\.s\}, p0, \[sp,z0\.s,sxtw\]
-.*:    e540c3e0        st1w    \{z0\.s\}, p0, \[sp,z0\.s,sxtw\]
-.*:    e544c000        st1w    \{z0\.s\}, p0, \[x0,z4\.s,sxtw\]
-.*:    e544c000        st1w    \{z0\.s\}, p0, \[x0,z4\.s,sxtw\]
-.*:    e544c000        st1w    \{z0\.s\}, p0, \[x0,z4\.s,sxtw\]
-.*:    e55fc000        st1w    \{z0\.s\}, p0, \[x0,z31\.s,sxtw\]
-.*:    e55fc000        st1w    \{z0\.s\}, p0, \[x0,z31\.s,sxtw\]
-.*:    e55fc000        st1w    \{z0\.s\}, p0, \[x0,z31\.s,sxtw\]
-.*:    e5604000        st1w    \{z0\.d\}, p0, \[x0,x0,lsl #2\]
-.*:    e5604000        st1w    \{z0\.d\}, p0, \[x0,x0,lsl #2\]
-.*:    e5604000        st1w    \{z0\.d\}, p0, \[x0,x0,lsl #2\]
-.*:    e5604001        st1w    \{z1\.d\}, p0, \[x0,x0,lsl #2\]
-.*:    e5604001        st1w    \{z1\.d\}, p0, \[x0,x0,lsl #2\]
-.*:    e5604001        st1w    \{z1\.d\}, p0, \[x0,x0,lsl #2\]
-.*:    e560401f        st1w    \{z31\.d\}, p0, \[x0,x0,lsl #2\]
-.*:    e560401f        st1w    \{z31\.d\}, p0, \[x0,x0,lsl #2\]
-.*:    e560401f        st1w    \{z31\.d\}, p0, \[x0,x0,lsl #2\]
-.*:    e5604800        st1w    \{z0\.d\}, p2, \[x0,x0,lsl #2\]
-.*:    e5604800        st1w    \{z0\.d\}, p2, \[x0,x0,lsl #2\]
-.*:    e5605c00        st1w    \{z0\.d\}, p7, \[x0,x0,lsl #2\]
-.*:    e5605c00        st1w    \{z0\.d\}, p7, \[x0,x0,lsl #2\]
-.*:    e5604060        st1w    \{z0\.d\}, p0, \[x3,x0,lsl #2\]
-.*:    e5604060        st1w    \{z0\.d\}, p0, \[x3,x0,lsl #2\]
-.*:    e56043e0        st1w    \{z0\.d\}, p0, \[sp,x0,lsl #2\]
-.*:    e56043e0        st1w    \{z0\.d\}, p0, \[sp,x0,lsl #2\]
-.*:    e5644000        st1w    \{z0\.d\}, p0, \[x0,x4,lsl #2\]
-.*:    e5644000        st1w    \{z0\.d\}, p0, \[x0,x4,lsl #2\]
-.*:    e57e4000        st1w    \{z0\.d\}, p0, \[x0,x30,lsl #2\]
-.*:    e57e4000        st1w    \{z0\.d\}, p0, \[x0,x30,lsl #2\]
-.*:    e5608000        st1w    \{z0\.s\}, p0, \[x0,z0\.s,uxtw #2\]
-.*:    e5608000        st1w    \{z0\.s\}, p0, \[x0,z0\.s,uxtw #2\]
-.*:    e5608000        st1w    \{z0\.s\}, p0, \[x0,z0\.s,uxtw #2\]
-.*:    e5608001        st1w    \{z1\.s\}, p0, \[x0,z0\.s,uxtw #2\]
-.*:    e5608001        st1w    \{z1\.s\}, p0, \[x0,z0\.s,uxtw #2\]
-.*:    e5608001        st1w    \{z1\.s\}, p0, \[x0,z0\.s,uxtw #2\]
-.*:    e560801f        st1w    \{z31\.s\}, p0, \[x0,z0\.s,uxtw #2\]
-.*:    e560801f        st1w    \{z31\.s\}, p0, \[x0,z0\.s,uxtw #2\]
-.*:    e560801f        st1w    \{z31\.s\}, p0, \[x0,z0\.s,uxtw #2\]
-.*:    e5608800        st1w    \{z0\.s\}, p2, \[x0,z0\.s,uxtw #2\]
-.*:    e5608800        st1w    \{z0\.s\}, p2, \[x0,z0\.s,uxtw #2\]
-.*:    e5609c00        st1w    \{z0\.s\}, p7, \[x0,z0\.s,uxtw #2\]
-.*:    e5609c00        st1w    \{z0\.s\}, p7, \[x0,z0\.s,uxtw #2\]
-.*:    e5608060        st1w    \{z0\.s\}, p0, \[x3,z0\.s,uxtw #2\]
-.*:    e5608060        st1w    \{z0\.s\}, p0, \[x3,z0\.s,uxtw #2\]
-.*:    e56083e0        st1w    \{z0\.s\}, p0, \[sp,z0\.s,uxtw #2\]
-.*:    e56083e0        st1w    \{z0\.s\}, p0, \[sp,z0\.s,uxtw #2\]
-.*:    e5648000        st1w    \{z0\.s\}, p0, \[x0,z4\.s,uxtw #2\]
-.*:    e5648000        st1w    \{z0\.s\}, p0, \[x0,z4\.s,uxtw #2\]
-.*:    e57f8000        st1w    \{z0\.s\}, p0, \[x0,z31\.s,uxtw #2\]
-.*:    e57f8000        st1w    \{z0\.s\}, p0, \[x0,z31\.s,uxtw #2\]
-.*:    e560c000        st1w    \{z0\.s\}, p0, \[x0,z0\.s,sxtw #2\]
-.*:    e560c000        st1w    \{z0\.s\}, p0, \[x0,z0\.s,sxtw #2\]
-.*:    e560c000        st1w    \{z0\.s\}, p0, \[x0,z0\.s,sxtw #2\]
-.*:    e560c001        st1w    \{z1\.s\}, p0, \[x0,z0\.s,sxtw #2\]
-.*:    e560c001        st1w    \{z1\.s\}, p0, \[x0,z0\.s,sxtw #2\]
-.*:    e560c001        st1w    \{z1\.s\}, p0, \[x0,z0\.s,sxtw #2\]
-.*:    e560c01f        st1w    \{z31\.s\}, p0, \[x0,z0\.s,sxtw #2\]
-.*:    e560c01f        st1w    \{z31\.s\}, p0, \[x0,z0\.s,sxtw #2\]
-.*:    e560c01f        st1w    \{z31\.s\}, p0, \[x0,z0\.s,sxtw #2\]
-.*:    e560c800        st1w    \{z0\.s\}, p2, \[x0,z0\.s,sxtw #2\]
-.*:    e560c800        st1w    \{z0\.s\}, p2, \[x0,z0\.s,sxtw #2\]
-.*:    e560dc00        st1w    \{z0\.s\}, p7, \[x0,z0\.s,sxtw #2\]
-.*:    e560dc00        st1w    \{z0\.s\}, p7, \[x0,z0\.s,sxtw #2\]
-.*:    e560c060        st1w    \{z0\.s\}, p0, \[x3,z0\.s,sxtw #2\]
-.*:    e560c060        st1w    \{z0\.s\}, p0, \[x3,z0\.s,sxtw #2\]
-.*:    e560c3e0        st1w    \{z0\.s\}, p0, \[sp,z0\.s,sxtw #2\]
-.*:    e560c3e0        st1w    \{z0\.s\}, p0, \[sp,z0\.s,sxtw #2\]
-.*:    e564c000        st1w    \{z0\.s\}, p0, \[x0,z4\.s,sxtw #2\]
-.*:    e564c000        st1w    \{z0\.s\}, p0, \[x0,z4\.s,sxtw #2\]
-.*:    e57fc000        st1w    \{z0\.s\}, p0, \[x0,z31\.s,sxtw #2\]
-.*:    e57fc000        st1w    \{z0\.s\}, p0, \[x0,z31\.s,sxtw #2\]
+.*:    e4e7e000        st1h    \{z0\.d\}, p0, \[x0, #7, mul vl\]
+.*:    e4e7e000        st1h    \{z0\.d\}, p0, \[x0, #7, mul vl\]
+.*:    e4e8e000        st1h    \{z0\.d\}, p0, \[x0, #-8, mul vl\]
+.*:    e4e8e000        st1h    \{z0\.d\}, p0, \[x0, #-8, mul vl\]
+.*:    e4e9e000        st1h    \{z0\.d\}, p0, \[x0, #-7, mul vl\]
+.*:    e4e9e000        st1h    \{z0\.d\}, p0, \[x0, #-7, mul vl\]
+.*:    e4efe000        st1h    \{z0\.d\}, p0, \[x0, #-1, mul vl\]
+.*:    e4efe000        st1h    \{z0\.d\}, p0, \[x0, #-1, mul vl\]
+.*:    e5008000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5008000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5008000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5008000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5008001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5008001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5008001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5008001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e500801f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e500801f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e500801f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e500801f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
+.*:    e5008800        st1w    \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
+.*:    e5008800        st1w    \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
+.*:    e5008800        st1w    \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
+.*:    e5009c00        st1w    \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
+.*:    e5009c00        st1w    \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
+.*:    e5009c00        st1w    \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
+.*:    e5008060        st1w    \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
+.*:    e5008060        st1w    \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
+.*:    e5008060        st1w    \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
+.*:    e50083e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
+.*:    e50083e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
+.*:    e50083e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
+.*:    e5048000        st1w    \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
+.*:    e5048000        st1w    \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
+.*:    e5048000        st1w    \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
+.*:    e51f8000        st1w    \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
+.*:    e51f8000        st1w    \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
+.*:    e51f8000        st1w    \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
+.*:    e500c000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e500c000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e500c000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e500c000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e500c001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e500c001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e500c001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e500c001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e500c01f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e500c01f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e500c01f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e500c01f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
+.*:    e500c800        st1w    \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
+.*:    e500c800        st1w    \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
+.*:    e500c800        st1w    \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
+.*:    e500dc00        st1w    \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
+.*:    e500dc00        st1w    \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
+.*:    e500dc00        st1w    \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
+.*:    e500c060        st1w    \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
+.*:    e500c060        st1w    \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
+.*:    e500c060        st1w    \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
+.*:    e500c3e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
+.*:    e500c3e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
+.*:    e500c3e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
+.*:    e504c000        st1w    \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
+.*:    e504c000        st1w    \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
+.*:    e504c000        st1w    \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
+.*:    e51fc000        st1w    \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
+.*:    e51fc000        st1w    \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
+.*:    e51fc000        st1w    \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
+.*:    e500a000        st1w    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e500a000        st1w    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e500a000        st1w    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e500a000        st1w    \{z0\.d\}, p0, \[x0, z0\.d\]
+.*:    e500a001        st1w    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e500a001        st1w    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e500a001        st1w    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e500a001        st1w    \{z1\.d\}, p0, \[x0, z0\.d\]
+.*:    e500a01f        st1w    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e500a01f        st1w    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e500a01f        st1w    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e500a01f        st1w    \{z31\.d\}, p0, \[x0, z0\.d\]
+.*:    e500a800        st1w    \{z0\.d\}, p2, \[x0, z0\.d\]
+.*:    e500a800        st1w    \{z0\.d\}, p2, \[x0, z0\.d\]
+.*:    e500a800        st1w    \{z0\.d\}, p2, \[x0, z0\.d\]
+.*:    e500bc00        st1w    \{z0\.d\}, p7, \[x0, z0\.d\]
+.*:    e500bc00        st1w    \{z0\.d\}, p7, \[x0, z0\.d\]
+.*:    e500bc00        st1w    \{z0\.d\}, p7, \[x0, z0\.d\]
+.*:    e500a060        st1w    \{z0\.d\}, p0, \[x3, z0\.d\]
+.*:    e500a060        st1w    \{z0\.d\}, p0, \[x3, z0\.d\]
+.*:    e500a060        st1w    \{z0\.d\}, p0, \[x3, z0\.d\]
+.*:    e500a3e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d\]
+.*:    e500a3e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d\]
+.*:    e500a3e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d\]
+.*:    e504a000        st1w    \{z0\.d\}, p0, \[x0, z4\.d\]
+.*:    e504a000        st1w    \{z0\.d\}, p0, \[x0, z4\.d\]
+.*:    e504a000        st1w    \{z0\.d\}, p0, \[x0, z4\.d\]
+.*:    e51fa000        st1w    \{z0\.d\}, p0, \[x0, z31\.d\]
+.*:    e51fa000        st1w    \{z0\.d\}, p0, \[x0, z31\.d\]
+.*:    e51fa000        st1w    \{z0\.d\}, p0, \[x0, z31\.d\]
+.*:    e5208000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, uxtw #2\]
+.*:    e5208000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, uxtw #2\]
+.*:    e5208000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, uxtw #2\]
+.*:    e5208001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, uxtw #2\]
+.*:    e5208001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, uxtw #2\]
+.*:    e5208001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, uxtw #2\]
+.*:    e520801f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, uxtw #2\]
+.*:    e520801f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, uxtw #2\]
+.*:    e520801f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, uxtw #2\]
+.*:    e5208800        st1w    \{z0\.d\}, p2, \[x0, z0\.d, uxtw #2\]
+.*:    e5208800        st1w    \{z0\.d\}, p2, \[x0, z0\.d, uxtw #2\]
+.*:    e5209c00        st1w    \{z0\.d\}, p7, \[x0, z0\.d, uxtw #2\]
+.*:    e5209c00        st1w    \{z0\.d\}, p7, \[x0, z0\.d, uxtw #2\]
+.*:    e5208060        st1w    \{z0\.d\}, p0, \[x3, z0\.d, uxtw #2\]
+.*:    e5208060        st1w    \{z0\.d\}, p0, \[x3, z0\.d, uxtw #2\]
+.*:    e52083e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d, uxtw #2\]
+.*:    e52083e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d, uxtw #2\]
+.*:    e5248000        st1w    \{z0\.d\}, p0, \[x0, z4\.d, uxtw #2\]
+.*:    e5248000        st1w    \{z0\.d\}, p0, \[x0, z4\.d, uxtw #2\]
+.*:    e53f8000        st1w    \{z0\.d\}, p0, \[x0, z31\.d, uxtw #2\]
+.*:    e53f8000        st1w    \{z0\.d\}, p0, \[x0, z31\.d, uxtw #2\]
+.*:    e520c000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, sxtw #2\]
+.*:    e520c000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, sxtw #2\]
+.*:    e520c000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, sxtw #2\]
+.*:    e520c001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, sxtw #2\]
+.*:    e520c001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, sxtw #2\]
+.*:    e520c001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, sxtw #2\]
+.*:    e520c01f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, sxtw #2\]
+.*:    e520c01f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, sxtw #2\]
+.*:    e520c01f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, sxtw #2\]
+.*:    e520c800        st1w    \{z0\.d\}, p2, \[x0, z0\.d, sxtw #2\]
+.*:    e520c800        st1w    \{z0\.d\}, p2, \[x0, z0\.d, sxtw #2\]
+.*:    e520dc00        st1w    \{z0\.d\}, p7, \[x0, z0\.d, sxtw #2\]
+.*:    e520dc00        st1w    \{z0\.d\}, p7, \[x0, z0\.d, sxtw #2\]
+.*:    e520c060        st1w    \{z0\.d\}, p0, \[x3, z0\.d, sxtw #2\]
+.*:    e520c060        st1w    \{z0\.d\}, p0, \[x3, z0\.d, sxtw #2\]
+.*:    e520c3e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d, sxtw #2\]
+.*:    e520c3e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d, sxtw #2\]
+.*:    e524c000        st1w    \{z0\.d\}, p0, \[x0, z4\.d, sxtw #2\]
+.*:    e524c000        st1w    \{z0\.d\}, p0, \[x0, z4\.d, sxtw #2\]
+.*:    e53fc000        st1w    \{z0\.d\}, p0, \[x0, z31\.d, sxtw #2\]
+.*:    e53fc000        st1w    \{z0\.d\}, p0, \[x0, z31\.d, sxtw #2\]
+.*:    e520a000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, lsl #2\]
+.*:    e520a000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, lsl #2\]
+.*:    e520a000        st1w    \{z0\.d\}, p0, \[x0, z0\.d, lsl #2\]
+.*:    e520a001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, lsl #2\]
+.*:    e520a001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, lsl #2\]
+.*:    e520a001        st1w    \{z1\.d\}, p0, \[x0, z0\.d, lsl #2\]
+.*:    e520a01f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, lsl #2\]
+.*:    e520a01f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, lsl #2\]
+.*:    e520a01f        st1w    \{z31\.d\}, p0, \[x0, z0\.d, lsl #2\]
+.*:    e520a800        st1w    \{z0\.d\}, p2, \[x0, z0\.d, lsl #2\]
+.*:    e520a800        st1w    \{z0\.d\}, p2, \[x0, z0\.d, lsl #2\]
+.*:    e520bc00        st1w    \{z0\.d\}, p7, \[x0, z0\.d, lsl #2\]
+.*:    e520bc00        st1w    \{z0\.d\}, p7, \[x0, z0\.d, lsl #2\]
+.*:    e520a060        st1w    \{z0\.d\}, p0, \[x3, z0\.d, lsl #2\]
+.*:    e520a060        st1w    \{z0\.d\}, p0, \[x3, z0\.d, lsl #2\]
+.*:    e520a3e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d, lsl #2\]
+.*:    e520a3e0        st1w    \{z0\.d\}, p0, \[sp, z0\.d, lsl #2\]
+.*:    e524a000        st1w    \{z0\.d\}, p0, \[x0, z4\.d, lsl #2\]
+.*:    e524a000        st1w    \{z0\.d\}, p0, \[x0, z4\.d, lsl #2\]
+.*:    e53fa000        st1w    \{z0\.d\}, p0, \[x0, z31\.d, lsl #2\]
+.*:    e53fa000        st1w    \{z0\.d\}, p0, \[x0, z31\.d, lsl #2\]
+.*:    e5404000        st1w    \{z0\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5404000        st1w    \{z0\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5404000        st1w    \{z0\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5404001        st1w    \{z1\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5404001        st1w    \{z1\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5404001        st1w    \{z1\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e540401f        st1w    \{z31\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e540401f        st1w    \{z31\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e540401f        st1w    \{z31\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5404800        st1w    \{z0\.s\}, p2, \[x0, x0, lsl #2\]
+.*:    e5404800        st1w    \{z0\.s\}, p2, \[x0, x0, lsl #2\]
+.*:    e5405c00        st1w    \{z0\.s\}, p7, \[x0, x0, lsl #2\]
+.*:    e5405c00        st1w    \{z0\.s\}, p7, \[x0, x0, lsl #2\]
+.*:    e5404060        st1w    \{z0\.s\}, p0, \[x3, x0, lsl #2\]
+.*:    e5404060        st1w    \{z0\.s\}, p0, \[x3, x0, lsl #2\]
+.*:    e54043e0        st1w    \{z0\.s\}, p0, \[sp, x0, lsl #2\]
+.*:    e54043e0        st1w    \{z0\.s\}, p0, \[sp, x0, lsl #2\]
+.*:    e5444000        st1w    \{z0\.s\}, p0, \[x0, x4, lsl #2\]
+.*:    e5444000        st1w    \{z0\.s\}, p0, \[x0, x4, lsl #2\]
+.*:    e55e4000        st1w    \{z0\.s\}, p0, \[x0, x30, lsl #2\]
+.*:    e55e4000        st1w    \{z0\.s\}, p0, \[x0, x30, lsl #2\]
+.*:    e5408000        st1w    \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e5408000        st1w    \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e5408000        st1w    \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e5408000        st1w    \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e5408001        st1w    \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e5408001        st1w    \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e5408001        st1w    \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e5408001        st1w    \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e540801f        st1w    \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e540801f        st1w    \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e540801f        st1w    \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e540801f        st1w    \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
+.*:    e5408800        st1w    \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
+.*:    e5408800        st1w    \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
+.*:    e5408800        st1w    \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
+.*:    e5409c00        st1w    \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
+.*:    e5409c00        st1w    \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
+.*:    e5409c00        st1w    \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
+.*:    e5408060        st1w    \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
+.*:    e5408060        st1w    \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
+.*:    e5408060        st1w    \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
+.*:    e54083e0        st1w    \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
+.*:    e54083e0        st1w    \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
+.*:    e54083e0        st1w    \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
+.*:    e5448000        st1w    \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
+.*:    e5448000        st1w    \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
+.*:    e5448000        st1w    \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
+.*:    e55f8000        st1w    \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
+.*:    e55f8000        st1w    \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
+.*:    e55f8000        st1w    \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
+.*:    e540c000        st1w    \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e540c000        st1w    \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e540c000        st1w    \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e540c000        st1w    \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e540c001        st1w    \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e540c001        st1w    \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e540c001        st1w    \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e540c001        st1w    \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e540c01f        st1w    \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e540c01f        st1w    \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e540c01f        st1w    \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e540c01f        st1w    \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
+.*:    e540c800        st1w    \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
+.*:    e540c800        st1w    \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
+.*:    e540c800        st1w    \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
+.*:    e540dc00        st1w    \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
+.*:    e540dc00        st1w    \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
+.*:    e540dc00        st1w    \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
+.*:    e540c060        st1w    \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
+.*:    e540c060        st1w    \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
+.*:    e540c060        st1w    \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
+.*:    e540c3e0        st1w    \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
+.*:    e540c3e0        st1w    \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
+.*:    e540c3e0        st1w    \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
+.*:    e544c000        st1w    \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
+.*:    e544c000        st1w    \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
+.*:    e544c000        st1w    \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
+.*:    e55fc000        st1w    \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
+.*:    e55fc000        st1w    \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
+.*:    e55fc000        st1w    \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
+.*:    e5604000        st1w    \{z0\.d\}, p0, \[x0, x0, lsl #2\]
+.*:    e5604000        st1w    \{z0\.d\}, p0, \[x0, x0, lsl #2\]
+.*:    e5604000        st1w    \{z0\.d\}, p0, \[x0, x0, lsl #2\]
+.*:    e5604001        st1w    \{z1\.d\}, p0, \[x0, x0, lsl #2\]
+.*:    e5604001        st1w    \{z1\.d\}, p0, \[x0, x0, lsl #2\]
+.*:    e5604001        st1w    \{z1\.d\}, p0, \[x0, x0, lsl #2\]
+.*:    e560401f        st1w    \{z31\.d\}, p0, \[x0, x0, lsl #2\]
+.*:    e560401f        st1w    \{z31\.d\}, p0, \[x0, x0, lsl #2\]
+.*:    e560401f        st1w    \{z31\.d\}, p0, \[x0, x0, lsl #2\]
+.*:    e5604800        st1w    \{z0\.d\}, p2, \[x0, x0, lsl #2\]
+.*:    e5604800        st1w    \{z0\.d\}, p2, \[x0, x0, lsl #2\]
+.*:    e5605c00        st1w    \{z0\.d\}, p7, \[x0, x0, lsl #2\]
+.*:    e5605c00        st1w    \{z0\.d\}, p7, \[x0, x0, lsl #2\]
+.*:    e5604060        st1w    \{z0\.d\}, p0, \[x3, x0, lsl #2\]
+.*:    e5604060        st1w    \{z0\.d\}, p0, \[x3, x0, lsl #2\]
+.*:    e56043e0        st1w    \{z0\.d\}, p0, \[sp, x0, lsl #2\]
+.*:    e56043e0        st1w    \{z0\.d\}, p0, \[sp, x0, lsl #2\]
+.*:    e5644000        st1w    \{z0\.d\}, p0, \[x0, x4, lsl #2\]
+.*:    e5644000        st1w    \{z0\.d\}, p0, \[x0, x4, lsl #2\]
+.*:    e57e4000        st1w    \{z0\.d\}, p0, \[x0, x30, lsl #2\]
+.*:    e57e4000        st1w    \{z0\.d\}, p0, \[x0, x30, lsl #2\]
+.*:    e5608000        st1w    \{z0\.s\}, p0, \[x0, z0\.s, uxtw #2\]
+.*:    e5608000        st1w    \{z0\.s\}, p0, \[x0, z0\.s, uxtw #2\]
+.*:    e5608000        st1w    \{z0\.s\}, p0, \[x0, z0\.s, uxtw #2\]
+.*:    e5608001        st1w    \{z1\.s\}, p0, \[x0, z0\.s, uxtw #2\]
+.*:    e5608001        st1w    \{z1\.s\}, p0, \[x0, z0\.s, uxtw #2\]
+.*:    e5608001        st1w    \{z1\.s\}, p0, \[x0, z0\.s, uxtw #2\]
+.*:    e560801f        st1w    \{z31\.s\}, p0, \[x0, z0\.s, uxtw #2\]
+.*:    e560801f        st1w    \{z31\.s\}, p0, \[x0, z0\.s, uxtw #2\]
+.*:    e560801f        st1w    \{z31\.s\}, p0, \[x0, z0\.s, uxtw #2\]
+.*:    e5608800        st1w    \{z0\.s\}, p2, \[x0, z0\.s, uxtw #2\]
+.*:    e5608800        st1w    \{z0\.s\}, p2, \[x0, z0\.s, uxtw #2\]
+.*:    e5609c00        st1w    \{z0\.s\}, p7, \[x0, z0\.s, uxtw #2\]
+.*:    e5609c00        st1w    \{z0\.s\}, p7, \[x0, z0\.s, uxtw #2\]
+.*:    e5608060        st1w    \{z0\.s\}, p0, \[x3, z0\.s, uxtw #2\]
+.*:    e5608060        st1w    \{z0\.s\}, p0, \[x3, z0\.s, uxtw #2\]
+.*:    e56083e0        st1w    \{z0\.s\}, p0, \[sp, z0\.s, uxtw #2\]
+.*:    e56083e0        st1w    \{z0\.s\}, p0, \[sp, z0\.s, uxtw #2\]
+.*:    e5648000        st1w    \{z0\.s\}, p0, \[x0, z4\.s, uxtw #2\]
+.*:    e5648000        st1w    \{z0\.s\}, p0, \[x0, z4\.s, uxtw #2\]
+.*:    e57f8000        st1w    \{z0\.s\}, p0, \[x0, z31\.s, uxtw #2\]
+.*:    e57f8000        st1w    \{z0\.s\}, p0, \[x0, z31\.s, uxtw #2\]
+.*:    e560c000        st1w    \{z0\.s\}, p0, \[x0, z0\.s, sxtw #2\]
+.*:    e560c000        st1w    \{z0\.s\}, p0, \[x0, z0\.s, sxtw #2\]
+.*:    e560c000        st1w    \{z0\.s\}, p0, \[x0, z0\.s, sxtw #2\]
+.*:    e560c001        st1w    \{z1\.s\}, p0, \[x0, z0\.s, sxtw #2\]
+.*:    e560c001        st1w    \{z1\.s\}, p0, \[x0, z0\.s, sxtw #2\]
+.*:    e560c001        st1w    \{z1\.s\}, p0, \[x0, z0\.s, sxtw #2\]
+.*:    e560c01f        st1w    \{z31\.s\}, p0, \[x0, z0\.s, sxtw #2\]
+.*:    e560c01f        st1w    \{z31\.s\}, p0, \[x0, z0\.s, sxtw #2\]
+.*:    e560c01f        st1w    \{z31\.s\}, p0, \[x0, z0\.s, sxtw #2\]
+.*:    e560c800        st1w    \{z0\.s\}, p2, \[x0, z0\.s, sxtw #2\]
+.*:    e560c800        st1w    \{z0\.s\}, p2, \[x0, z0\.s, sxtw #2\]
+.*:    e560dc00        st1w    \{z0\.s\}, p7, \[x0, z0\.s, sxtw #2\]
+.*:    e560dc00        st1w    \{z0\.s\}, p7, \[x0, z0\.s, sxtw #2\]
+.*:    e560c060        st1w    \{z0\.s\}, p0, \[x3, z0\.s, sxtw #2\]
+.*:    e560c060        st1w    \{z0\.s\}, p0, \[x3, z0\.s, sxtw #2\]
+.*:    e560c3e0        st1w    \{z0\.s\}, p0, \[sp, z0\.s, sxtw #2\]
+.*:    e560c3e0        st1w    \{z0\.s\}, p0, \[sp, z0\.s, sxtw #2\]
+.*:    e564c000        st1w    \{z0\.s\}, p0, \[x0, z4\.s, sxtw #2\]
+.*:    e564c000        st1w    \{z0\.s\}, p0, \[x0, z4\.s, sxtw #2\]
+.*:    e57fc000        st1w    \{z0\.s\}, p0, \[x0, z31\.s, sxtw #2\]
+.*:    e57fc000        st1w    \{z0\.s\}, p0, \[x0, z31\.s, sxtw #2\]
 .*:    e540a000        st1w    \{z0\.d\}, p0, \[z0\.d\]
 .*:    e540a000        st1w    \{z0\.d\}, p0, \[z0\.d\]
 .*:    e540a000        st1w    \{z0\.d\}, p0, \[z0\.d\]
@@ -30395,14 +30395,14 @@ Disassembly of section .*:
 .*:    e540a3e0        st1w    \{z0\.d\}, p0, \[z31\.d\]
 .*:    e540a3e0        st1w    \{z0\.d\}, p0, \[z31\.d\]
 .*:    e540a3e0        st1w    \{z0\.d\}, p0, \[z31\.d\]
-.*:    e54fa000        st1w    \{z0\.d\}, p0, \[z0\.d,#60\]
-.*:    e54fa000        st1w    \{z0\.d\}, p0, \[z0\.d,#60\]
-.*:    e550a000        st1w    \{z0\.d\}, p0, \[z0\.d,#64\]
-.*:    e550a000        st1w    \{z0\.d\}, p0, \[z0\.d,#64\]
-.*:    e551a000        st1w    \{z0\.d\}, p0, \[z0\.d,#68\]
-.*:    e551a000        st1w    \{z0\.d\}, p0, \[z0\.d,#68\]
-.*:    e55fa000        st1w    \{z0\.d\}, p0, \[z0\.d,#124\]
-.*:    e55fa000        st1w    \{z0\.d\}, p0, \[z0\.d,#124\]
+.*:    e54fa000        st1w    \{z0\.d\}, p0, \[z0\.d, #60\]
+.*:    e54fa000        st1w    \{z0\.d\}, p0, \[z0\.d, #60\]
+.*:    e550a000        st1w    \{z0\.d\}, p0, \[z0\.d, #64\]
+.*:    e550a000        st1w    \{z0\.d\}, p0, \[z0\.d, #64\]
+.*:    e551a000        st1w    \{z0\.d\}, p0, \[z0\.d, #68\]
+.*:    e551a000        st1w    \{z0\.d\}, p0, \[z0\.d, #68\]
+.*:    e55fa000        st1w    \{z0\.d\}, p0, \[z0\.d, #124\]
+.*:    e55fa000        st1w    \{z0\.d\}, p0, \[z0\.d, #124\]
 .*:    e540e000        st1w    \{z0\.s\}, p0, \[x0\]
 .*:    e540e000        st1w    \{z0\.s\}, p0, \[x0\]
 .*:    e540e000        st1w    \{z0\.s\}, p0, \[x0\]
@@ -30434,14 +30434,14 @@ Disassembly of section .*:
 .*:    e540e3e0        st1w    \{z0\.s\}, p0, \[sp\]
 .*:    e540e3e0        st1w    \{z0\.s\}, p0, \[sp\]
 .*:    e540e3e0        st1w    \{z0\.s\}, p0, \[sp\]
-.*:    e547e000        st1w    \{z0\.s\}, p0, \[x0,#7,mul vl\]
-.*:    e547e000        st1w    \{z0\.s\}, p0, \[x0,#7,mul vl\]
-.*:    e548e000        st1w    \{z0\.s\}, p0, \[x0,#-8,mul vl\]
-.*:    e548e000        st1w    \{z0\.s\}, p0, \[x0,#-8,mul vl\]
-.*:    e549e000        st1w    \{z0\.s\}, p0, \[x0,#-7,mul vl\]
-.*:    e549e000        st1w    \{z0\.s\}, p0, \[x0,#-7,mul vl\]
-.*:    e54fe000        st1w    \{z0\.s\}, p0, \[x0,#-1,mul vl\]
-.*:    e54fe000        st1w    \{z0\.s\}, p0, \[x0,#-1,mul vl\]
+.*:    e547e000        st1w    \{z0\.s\}, p0, \[x0, #7, mul vl\]
+.*:    e547e000        st1w    \{z0\.s\}, p0, \[x0, #7, mul vl\]
+.*:    e548e000        st1w    \{z0\.s\}, p0, \[x0, #-8, mul vl\]
+.*:    e548e000        st1w    \{z0\.s\}, p0, \[x0, #-8, mul vl\]
+.*:    e549e000        st1w    \{z0\.s\}, p0, \[x0, #-7, mul vl\]
+.*:    e549e000        st1w    \{z0\.s\}, p0, \[x0, #-7, mul vl\]
+.*:    e54fe000        st1w    \{z0\.s\}, p0, \[x0, #-1, mul vl\]
+.*:    e54fe000        st1w    \{z0\.s\}, p0, \[x0, #-1, mul vl\]
 .*:    e560a000        st1w    \{z0\.s\}, p0, \[z0\.s\]
 .*:    e560a000        st1w    \{z0\.s\}, p0, \[z0\.s\]
 .*:    e560a000        st1w    \{z0\.s\}, p0, \[z0\.s\]
@@ -30466,14 +30466,14 @@ Disassembly of section .*:
 .*:    e560a3e0        st1w    \{z0\.s\}, p0, \[z31\.s\]
 .*:    e560a3e0        st1w    \{z0\.s\}, p0, \[z31\.s\]
 .*:    e560a3e0        st1w    \{z0\.s\}, p0, \[z31\.s\]
-.*:    e56fa000        st1w    \{z0\.s\}, p0, \[z0\.s,#60\]
-.*:    e56fa000        st1w    \{z0\.s\}, p0, \[z0\.s,#60\]
-.*:    e570a000        st1w    \{z0\.s\}, p0, \[z0\.s,#64\]
-.*:    e570a000        st1w    \{z0\.s\}, p0, \[z0\.s,#64\]
-.*:    e571a000        st1w    \{z0\.s\}, p0, \[z0\.s,#68\]
-.*:    e571a000        st1w    \{z0\.s\}, p0, \[z0\.s,#68\]
-.*:    e57fa000        st1w    \{z0\.s\}, p0, \[z0\.s,#124\]
-.*:    e57fa000        st1w    \{z0\.s\}, p0, \[z0\.s,#124\]
+.*:    e56fa000        st1w    \{z0\.s\}, p0, \[z0\.s, #60\]
+.*:    e56fa000        st1w    \{z0\.s\}, p0, \[z0\.s, #60\]
+.*:    e570a000        st1w    \{z0\.s\}, p0, \[z0\.s, #64\]
+.*:    e570a000        st1w    \{z0\.s\}, p0, \[z0\.s, #64\]
+.*:    e571a000        st1w    \{z0\.s\}, p0, \[z0\.s, #68\]
+.*:    e571a000        st1w    \{z0\.s\}, p0, \[z0\.s, #68\]
+.*:    e57fa000        st1w    \{z0\.s\}, p0, \[z0\.s, #124\]
+.*:    e57fa000        st1w    \{z0\.s\}, p0, \[z0\.s, #124\]
 .*:    e560e000        st1w    \{z0\.d\}, p0, \[x0\]
 .*:    e560e000        st1w    \{z0\.d\}, p0, \[x0\]
 .*:    e560e000        st1w    \{z0\.d\}, p0, \[x0\]
@@ -30505,57 +30505,57 @@ Disassembly of section .*:
 .*:    e560e3e0        st1w    \{z0\.d\}, p0, \[sp\]
 .*:    e560e3e0        st1w    \{z0\.d\}, p0, \[sp\]
 .*:    e560e3e0        st1w    \{z0\.d\}, p0, \[sp\]
-.*:    e567e000        st1w    \{z0\.d\}, p0, \[x0,#7,mul vl\]
-.*:    e567e000        st1w    \{z0\.d\}, p0, \[x0,#7,mul vl\]
-.*:    e568e000        st1w    \{z0\.d\}, p0, \[x0,#-8,mul vl\]
-.*:    e568e000        st1w    \{z0\.d\}, p0, \[x0,#-8,mul vl\]
-.*:    e569e000        st1w    \{z0\.d\}, p0, \[x0,#-7,mul vl\]
-.*:    e569e000        st1w    \{z0\.d\}, p0, \[x0,#-7,mul vl\]
-.*:    e56fe000        st1w    \{z0\.d\}, p0, \[x0,#-1,mul vl\]
-.*:    e56fe000        st1w    \{z0\.d\}, p0, \[x0,#-1,mul vl\]
-.*:    e4206000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x0\]
-.*:    e4206000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x0\]
-.*:    e4206000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x0\]
-.*:    e4206000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x0\]
-.*:    e4206000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x0\]
-.*:    e4206001        st2b    \{z1\.b, z2\.b\}, p0, \[x0,x0\]
-.*:    e4206001        st2b    \{z1\.b, z2\.b\}, p0, \[x0,x0\]
-.*:    e4206001        st2b    \{z1\.b, z2\.b\}, p0, \[x0,x0\]
-.*:    e4206001        st2b    \{z1\.b, z2\.b\}, p0, \[x0,x0\]
-.*:    e4206001        st2b    \{z1\.b, z2\.b\}, p0, \[x0,x0\]
-.*:    e420601f        st2b    \{z31\.b, z0\.b\}, p0, \[x0,x0\]
-.*:    e420601f        st2b    \{z31\.b, z0\.b\}, p0, \[x0,x0\]
-.*:    e420601f        st2b    \{z31\.b, z0\.b\}, p0, \[x0,x0\]
-.*:    e4206800        st2b    \{z0\.b, z1\.b\}, p2, \[x0,x0\]
-.*:    e4206800        st2b    \{z0\.b, z1\.b\}, p2, \[x0,x0\]
-.*:    e4206800        st2b    \{z0\.b, z1\.b\}, p2, \[x0,x0\]
-.*:    e4206800        st2b    \{z0\.b, z1\.b\}, p2, \[x0,x0\]
-.*:    e4206800        st2b    \{z0\.b, z1\.b\}, p2, \[x0,x0\]
-.*:    e4207c00        st2b    \{z0\.b, z1\.b\}, p7, \[x0,x0\]
-.*:    e4207c00        st2b    \{z0\.b, z1\.b\}, p7, \[x0,x0\]
-.*:    e4207c00        st2b    \{z0\.b, z1\.b\}, p7, \[x0,x0\]
-.*:    e4207c00        st2b    \{z0\.b, z1\.b\}, p7, \[x0,x0\]
-.*:    e4207c00        st2b    \{z0\.b, z1\.b\}, p7, \[x0,x0\]
-.*:    e4206060        st2b    \{z0\.b, z1\.b\}, p0, \[x3,x0\]
-.*:    e4206060        st2b    \{z0\.b, z1\.b\}, p0, \[x3,x0\]
-.*:    e4206060        st2b    \{z0\.b, z1\.b\}, p0, \[x3,x0\]
-.*:    e4206060        st2b    \{z0\.b, z1\.b\}, p0, \[x3,x0\]
-.*:    e4206060        st2b    \{z0\.b, z1\.b\}, p0, \[x3,x0\]
-.*:    e42063e0        st2b    \{z0\.b, z1\.b\}, p0, \[sp,x0\]
-.*:    e42063e0        st2b    \{z0\.b, z1\.b\}, p0, \[sp,x0\]
-.*:    e42063e0        st2b    \{z0\.b, z1\.b\}, p0, \[sp,x0\]
-.*:    e42063e0        st2b    \{z0\.b, z1\.b\}, p0, \[sp,x0\]
-.*:    e42063e0        st2b    \{z0\.b, z1\.b\}, p0, \[sp,x0\]
-.*:    e4246000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x4\]
-.*:    e4246000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x4\]
-.*:    e4246000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x4\]
-.*:    e4246000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x4\]
-.*:    e4246000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x4\]
-.*:    e43e6000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x30\]
-.*:    e43e6000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x30\]
-.*:    e43e6000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x30\]
-.*:    e43e6000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x30\]
-.*:    e43e6000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,x30\]
+.*:    e567e000        st1w    \{z0\.d\}, p0, \[x0, #7, mul vl\]
+.*:    e567e000        st1w    \{z0\.d\}, p0, \[x0, #7, mul vl\]
+.*:    e568e000        st1w    \{z0\.d\}, p0, \[x0, #-8, mul vl\]
+.*:    e568e000        st1w    \{z0\.d\}, p0, \[x0, #-8, mul vl\]
+.*:    e569e000        st1w    \{z0\.d\}, p0, \[x0, #-7, mul vl\]
+.*:    e569e000        st1w    \{z0\.d\}, p0, \[x0, #-7, mul vl\]
+.*:    e56fe000        st1w    \{z0\.d\}, p0, \[x0, #-1, mul vl\]
+.*:    e56fe000        st1w    \{z0\.d\}, p0, \[x0, #-1, mul vl\]
+.*:    e4206000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x0\]
+.*:    e4206000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x0\]
+.*:    e4206000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x0\]
+.*:    e4206000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x0\]
+.*:    e4206000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x0\]
+.*:    e4206001        st2b    \{z1\.b, z2\.b\}, p0, \[x0, x0\]
+.*:    e4206001        st2b    \{z1\.b, z2\.b\}, p0, \[x0, x0\]
+.*:    e4206001        st2b    \{z1\.b, z2\.b\}, p0, \[x0, x0\]
+.*:    e4206001        st2b    \{z1\.b, z2\.b\}, p0, \[x0, x0\]
+.*:    e4206001        st2b    \{z1\.b, z2\.b\}, p0, \[x0, x0\]
+.*:    e420601f        st2b    \{z31\.b, z0\.b\}, p0, \[x0, x0\]
+.*:    e420601f        st2b    \{z31\.b, z0\.b\}, p0, \[x0, x0\]
+.*:    e420601f        st2b    \{z31\.b, z0\.b\}, p0, \[x0, x0\]
+.*:    e4206800        st2b    \{z0\.b, z1\.b\}, p2, \[x0, x0\]
+.*:    e4206800        st2b    \{z0\.b, z1\.b\}, p2, \[x0, x0\]
+.*:    e4206800        st2b    \{z0\.b, z1\.b\}, p2, \[x0, x0\]
+.*:    e4206800        st2b    \{z0\.b, z1\.b\}, p2, \[x0, x0\]
+.*:    e4206800        st2b    \{z0\.b, z1\.b\}, p2, \[x0, x0\]
+.*:    e4207c00        st2b    \{z0\.b, z1\.b\}, p7, \[x0, x0\]
+.*:    e4207c00        st2b    \{z0\.b, z1\.b\}, p7, \[x0, x0\]
+.*:    e4207c00        st2b    \{z0\.b, z1\.b\}, p7, \[x0, x0\]
+.*:    e4207c00        st2b    \{z0\.b, z1\.b\}, p7, \[x0, x0\]
+.*:    e4207c00        st2b    \{z0\.b, z1\.b\}, p7, \[x0, x0\]
+.*:    e4206060        st2b    \{z0\.b, z1\.b\}, p0, \[x3, x0\]
+.*:    e4206060        st2b    \{z0\.b, z1\.b\}, p0, \[x3, x0\]
+.*:    e4206060        st2b    \{z0\.b, z1\.b\}, p0, \[x3, x0\]
+.*:    e4206060        st2b    \{z0\.b, z1\.b\}, p0, \[x3, x0\]
+.*:    e4206060        st2b    \{z0\.b, z1\.b\}, p0, \[x3, x0\]
+.*:    e42063e0        st2b    \{z0\.b, z1\.b\}, p0, \[sp, x0\]
+.*:    e42063e0        st2b    \{z0\.b, z1\.b\}, p0, \[sp, x0\]
+.*:    e42063e0        st2b    \{z0\.b, z1\.b\}, p0, \[sp, x0\]
+.*:    e42063e0        st2b    \{z0\.b, z1\.b\}, p0, \[sp, x0\]
+.*:    e42063e0        st2b    \{z0\.b, z1\.b\}, p0, \[sp, x0\]
+.*:    e4246000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x4\]
+.*:    e4246000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x4\]
+.*:    e4246000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x4\]
+.*:    e4246000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x4\]
+.*:    e4246000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x4\]
+.*:    e43e6000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x30\]
+.*:    e43e6000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x30\]
+.*:    e43e6000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x30\]
+.*:    e43e6000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x30\]
+.*:    e43e6000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, x30\]
 .*:    e430e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0\]
 .*:    e430e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0\]
 .*:    e430e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0\]
@@ -30602,44 +30602,44 @@ Disassembly of section .*:
 .*:    e430e3e0        st2b    \{z0\.b, z1\.b\}, p0, \[sp\]
 .*:    e430e3e0        st2b    \{z0\.b, z1\.b\}, p0, \[sp\]
 .*:    e430e3e0        st2b    \{z0\.b, z1\.b\}, p0, \[sp\]
-.*:    e437e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,#14,mul vl\]
-.*:    e437e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,#14,mul vl\]
-.*:    e437e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,#14,mul vl\]
-.*:    e438e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,#-16,mul vl\]
-.*:    e438e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,#-16,mul vl\]
-.*:    e438e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,#-16,mul vl\]
-.*:    e439e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,#-14,mul vl\]
-.*:    e439e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,#-14,mul vl\]
-.*:    e439e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,#-14,mul vl\]
-.*:    e43fe000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,#-2,mul vl\]
-.*:    e43fe000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,#-2,mul vl\]
-.*:    e43fe000        st2b    \{z0\.b, z1\.b\}, p0, \[x0,#-2,mul vl\]
-.*:    e5a06000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5a06000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5a06000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5a06001        st2d    \{z1\.d, z2\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5a06001        st2d    \{z1\.d, z2\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5a06001        st2d    \{z1\.d, z2\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5a0601f        st2d    \{z31\.d, z0\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5a0601f        st2d    \{z31\.d, z0\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5a06800        st2d    \{z0\.d, z1\.d\}, p2, \[x0,x0,lsl #3\]
-.*:    e5a06800        st2d    \{z0\.d, z1\.d\}, p2, \[x0,x0,lsl #3\]
-.*:    e5a06800        st2d    \{z0\.d, z1\.d\}, p2, \[x0,x0,lsl #3\]
-.*:    e5a07c00        st2d    \{z0\.d, z1\.d\}, p7, \[x0,x0,lsl #3\]
-.*:    e5a07c00        st2d    \{z0\.d, z1\.d\}, p7, \[x0,x0,lsl #3\]
-.*:    e5a07c00        st2d    \{z0\.d, z1\.d\}, p7, \[x0,x0,lsl #3\]
-.*:    e5a06060        st2d    \{z0\.d, z1\.d\}, p0, \[x3,x0,lsl #3\]
-.*:    e5a06060        st2d    \{z0\.d, z1\.d\}, p0, \[x3,x0,lsl #3\]
-.*:    e5a06060        st2d    \{z0\.d, z1\.d\}, p0, \[x3,x0,lsl #3\]
-.*:    e5a063e0        st2d    \{z0\.d, z1\.d\}, p0, \[sp,x0,lsl #3\]
-.*:    e5a063e0        st2d    \{z0\.d, z1\.d\}, p0, \[sp,x0,lsl #3\]
-.*:    e5a063e0        st2d    \{z0\.d, z1\.d\}, p0, \[sp,x0,lsl #3\]
-.*:    e5a46000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,x4,lsl #3\]
-.*:    e5a46000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,x4,lsl #3\]
-.*:    e5a46000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,x4,lsl #3\]
-.*:    e5be6000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,x30,lsl #3\]
-.*:    e5be6000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,x30,lsl #3\]
-.*:    e5be6000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,x30,lsl #3\]
+.*:    e437e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, #14, mul vl\]
+.*:    e437e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, #14, mul vl\]
+.*:    e437e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, #14, mul vl\]
+.*:    e438e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, #-16, mul vl\]
+.*:    e438e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, #-16, mul vl\]
+.*:    e438e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, #-16, mul vl\]
+.*:    e439e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, #-14, mul vl\]
+.*:    e439e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, #-14, mul vl\]
+.*:    e439e000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, #-14, mul vl\]
+.*:    e43fe000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, #-2, mul vl\]
+.*:    e43fe000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, #-2, mul vl\]
+.*:    e43fe000        st2b    \{z0\.b, z1\.b\}, p0, \[x0, #-2, mul vl\]
+.*:    e5a06000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5a06000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5a06000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5a06001        st2d    \{z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5a06001        st2d    \{z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5a06001        st2d    \{z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5a0601f        st2d    \{z31\.d, z0\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5a0601f        st2d    \{z31\.d, z0\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5a06800        st2d    \{z0\.d, z1\.d\}, p2, \[x0, x0, lsl #3\]
+.*:    e5a06800        st2d    \{z0\.d, z1\.d\}, p2, \[x0, x0, lsl #3\]
+.*:    e5a06800        st2d    \{z0\.d, z1\.d\}, p2, \[x0, x0, lsl #3\]
+.*:    e5a07c00        st2d    \{z0\.d, z1\.d\}, p7, \[x0, x0, lsl #3\]
+.*:    e5a07c00        st2d    \{z0\.d, z1\.d\}, p7, \[x0, x0, lsl #3\]
+.*:    e5a07c00        st2d    \{z0\.d, z1\.d\}, p7, \[x0, x0, lsl #3\]
+.*:    e5a06060        st2d    \{z0\.d, z1\.d\}, p0, \[x3, x0, lsl #3\]
+.*:    e5a06060        st2d    \{z0\.d, z1\.d\}, p0, \[x3, x0, lsl #3\]
+.*:    e5a06060        st2d    \{z0\.d, z1\.d\}, p0, \[x3, x0, lsl #3\]
+.*:    e5a063e0        st2d    \{z0\.d, z1\.d\}, p0, \[sp, x0, lsl #3\]
+.*:    e5a063e0        st2d    \{z0\.d, z1\.d\}, p0, \[sp, x0, lsl #3\]
+.*:    e5a063e0        st2d    \{z0\.d, z1\.d\}, p0, \[sp, x0, lsl #3\]
+.*:    e5a46000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, x4, lsl #3\]
+.*:    e5a46000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, x4, lsl #3\]
+.*:    e5a46000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, x4, lsl #3\]
+.*:    e5be6000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, x30, lsl #3\]
+.*:    e5be6000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, x30, lsl #3\]
+.*:    e5be6000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, x30, lsl #3\]
 .*:    e5b0e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0\]
 .*:    e5b0e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0\]
 .*:    e5b0e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0\]
@@ -30686,44 +30686,44 @@ Disassembly of section .*:
 .*:    e5b0e3e0        st2d    \{z0\.d, z1\.d\}, p0, \[sp\]
 .*:    e5b0e3e0        st2d    \{z0\.d, z1\.d\}, p0, \[sp\]
 .*:    e5b0e3e0        st2d    \{z0\.d, z1\.d\}, p0, \[sp\]
-.*:    e5b7e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,#14,mul vl\]
-.*:    e5b7e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,#14,mul vl\]
-.*:    e5b7e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,#14,mul vl\]
-.*:    e5b8e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,#-16,mul vl\]
-.*:    e5b8e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,#-16,mul vl\]
-.*:    e5b8e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,#-16,mul vl\]
-.*:    e5b9e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,#-14,mul vl\]
-.*:    e5b9e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,#-14,mul vl\]
-.*:    e5b9e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,#-14,mul vl\]
-.*:    e5bfe000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,#-2,mul vl\]
-.*:    e5bfe000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,#-2,mul vl\]
-.*:    e5bfe000        st2d    \{z0\.d, z1\.d\}, p0, \[x0,#-2,mul vl\]
-.*:    e4a06000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a06000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a06000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a06001        st2h    \{z1\.h, z2\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a06001        st2h    \{z1\.h, z2\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a06001        st2h    \{z1\.h, z2\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a0601f        st2h    \{z31\.h, z0\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a0601f        st2h    \{z31\.h, z0\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4a06800        st2h    \{z0\.h, z1\.h\}, p2, \[x0,x0,lsl #1\]
-.*:    e4a06800        st2h    \{z0\.h, z1\.h\}, p2, \[x0,x0,lsl #1\]
-.*:    e4a06800        st2h    \{z0\.h, z1\.h\}, p2, \[x0,x0,lsl #1\]
-.*:    e4a07c00        st2h    \{z0\.h, z1\.h\}, p7, \[x0,x0,lsl #1\]
-.*:    e4a07c00        st2h    \{z0\.h, z1\.h\}, p7, \[x0,x0,lsl #1\]
-.*:    e4a07c00        st2h    \{z0\.h, z1\.h\}, p7, \[x0,x0,lsl #1\]
-.*:    e4a06060        st2h    \{z0\.h, z1\.h\}, p0, \[x3,x0,lsl #1\]
-.*:    e4a06060        st2h    \{z0\.h, z1\.h\}, p0, \[x3,x0,lsl #1\]
-.*:    e4a06060        st2h    \{z0\.h, z1\.h\}, p0, \[x3,x0,lsl #1\]
-.*:    e4a063e0        st2h    \{z0\.h, z1\.h\}, p0, \[sp,x0,lsl #1\]
-.*:    e4a063e0        st2h    \{z0\.h, z1\.h\}, p0, \[sp,x0,lsl #1\]
-.*:    e4a063e0        st2h    \{z0\.h, z1\.h\}, p0, \[sp,x0,lsl #1\]
-.*:    e4a46000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,x4,lsl #1\]
-.*:    e4a46000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,x4,lsl #1\]
-.*:    e4a46000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,x4,lsl #1\]
-.*:    e4be6000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,x30,lsl #1\]
-.*:    e4be6000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,x30,lsl #1\]
-.*:    e4be6000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,x30,lsl #1\]
+.*:    e5b7e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, #14, mul vl\]
+.*:    e5b7e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, #14, mul vl\]
+.*:    e5b7e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, #14, mul vl\]
+.*:    e5b8e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, #-16, mul vl\]
+.*:    e5b8e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, #-16, mul vl\]
+.*:    e5b8e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, #-16, mul vl\]
+.*:    e5b9e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, #-14, mul vl\]
+.*:    e5b9e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, #-14, mul vl\]
+.*:    e5b9e000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, #-14, mul vl\]
+.*:    e5bfe000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, #-2, mul vl\]
+.*:    e5bfe000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, #-2, mul vl\]
+.*:    e5bfe000        st2d    \{z0\.d, z1\.d\}, p0, \[x0, #-2, mul vl\]
+.*:    e4a06000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a06000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a06000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a06001        st2h    \{z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a06001        st2h    \{z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a06001        st2h    \{z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a0601f        st2h    \{z31\.h, z0\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a0601f        st2h    \{z31\.h, z0\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4a06800        st2h    \{z0\.h, z1\.h\}, p2, \[x0, x0, lsl #1\]
+.*:    e4a06800        st2h    \{z0\.h, z1\.h\}, p2, \[x0, x0, lsl #1\]
+.*:    e4a06800        st2h    \{z0\.h, z1\.h\}, p2, \[x0, x0, lsl #1\]
+.*:    e4a07c00        st2h    \{z0\.h, z1\.h\}, p7, \[x0, x0, lsl #1\]
+.*:    e4a07c00        st2h    \{z0\.h, z1\.h\}, p7, \[x0, x0, lsl #1\]
+.*:    e4a07c00        st2h    \{z0\.h, z1\.h\}, p7, \[x0, x0, lsl #1\]
+.*:    e4a06060        st2h    \{z0\.h, z1\.h\}, p0, \[x3, x0, lsl #1\]
+.*:    e4a06060        st2h    \{z0\.h, z1\.h\}, p0, \[x3, x0, lsl #1\]
+.*:    e4a06060        st2h    \{z0\.h, z1\.h\}, p0, \[x3, x0, lsl #1\]
+.*:    e4a063e0        st2h    \{z0\.h, z1\.h\}, p0, \[sp, x0, lsl #1\]
+.*:    e4a063e0        st2h    \{z0\.h, z1\.h\}, p0, \[sp, x0, lsl #1\]
+.*:    e4a063e0        st2h    \{z0\.h, z1\.h\}, p0, \[sp, x0, lsl #1\]
+.*:    e4a46000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, x4, lsl #1\]
+.*:    e4a46000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, x4, lsl #1\]
+.*:    e4a46000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, x4, lsl #1\]
+.*:    e4be6000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, x30, lsl #1\]
+.*:    e4be6000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, x30, lsl #1\]
+.*:    e4be6000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, x30, lsl #1\]
 .*:    e4b0e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0\]
 .*:    e4b0e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0\]
 .*:    e4b0e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0\]
@@ -30770,44 +30770,44 @@ Disassembly of section .*:
 .*:    e4b0e3e0        st2h    \{z0\.h, z1\.h\}, p0, \[sp\]
 .*:    e4b0e3e0        st2h    \{z0\.h, z1\.h\}, p0, \[sp\]
 .*:    e4b0e3e0        st2h    \{z0\.h, z1\.h\}, p0, \[sp\]
-.*:    e4b7e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,#14,mul vl\]
-.*:    e4b7e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,#14,mul vl\]
-.*:    e4b7e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,#14,mul vl\]
-.*:    e4b8e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,#-16,mul vl\]
-.*:    e4b8e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,#-16,mul vl\]
-.*:    e4b8e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,#-16,mul vl\]
-.*:    e4b9e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,#-14,mul vl\]
-.*:    e4b9e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,#-14,mul vl\]
-.*:    e4b9e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,#-14,mul vl\]
-.*:    e4bfe000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,#-2,mul vl\]
-.*:    e4bfe000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,#-2,mul vl\]
-.*:    e4bfe000        st2h    \{z0\.h, z1\.h\}, p0, \[x0,#-2,mul vl\]
-.*:    e5206000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5206000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5206000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5206001        st2w    \{z1\.s, z2\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5206001        st2w    \{z1\.s, z2\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5206001        st2w    \{z1\.s, z2\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e520601f        st2w    \{z31\.s, z0\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e520601f        st2w    \{z31\.s, z0\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5206800        st2w    \{z0\.s, z1\.s\}, p2, \[x0,x0,lsl #2\]
-.*:    e5206800        st2w    \{z0\.s, z1\.s\}, p2, \[x0,x0,lsl #2\]
-.*:    e5206800        st2w    \{z0\.s, z1\.s\}, p2, \[x0,x0,lsl #2\]
-.*:    e5207c00        st2w    \{z0\.s, z1\.s\}, p7, \[x0,x0,lsl #2\]
-.*:    e5207c00        st2w    \{z0\.s, z1\.s\}, p7, \[x0,x0,lsl #2\]
-.*:    e5207c00        st2w    \{z0\.s, z1\.s\}, p7, \[x0,x0,lsl #2\]
-.*:    e5206060        st2w    \{z0\.s, z1\.s\}, p0, \[x3,x0,lsl #2\]
-.*:    e5206060        st2w    \{z0\.s, z1\.s\}, p0, \[x3,x0,lsl #2\]
-.*:    e5206060        st2w    \{z0\.s, z1\.s\}, p0, \[x3,x0,lsl #2\]
-.*:    e52063e0        st2w    \{z0\.s, z1\.s\}, p0, \[sp,x0,lsl #2\]
-.*:    e52063e0        st2w    \{z0\.s, z1\.s\}, p0, \[sp,x0,lsl #2\]
-.*:    e52063e0        st2w    \{z0\.s, z1\.s\}, p0, \[sp,x0,lsl #2\]
-.*:    e5246000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,x4,lsl #2\]
-.*:    e5246000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,x4,lsl #2\]
-.*:    e5246000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,x4,lsl #2\]
-.*:    e53e6000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,x30,lsl #2\]
-.*:    e53e6000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,x30,lsl #2\]
-.*:    e53e6000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,x30,lsl #2\]
+.*:    e4b7e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, #14, mul vl\]
+.*:    e4b7e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, #14, mul vl\]
+.*:    e4b7e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, #14, mul vl\]
+.*:    e4b8e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, #-16, mul vl\]
+.*:    e4b8e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, #-16, mul vl\]
+.*:    e4b8e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, #-16, mul vl\]
+.*:    e4b9e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, #-14, mul vl\]
+.*:    e4b9e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, #-14, mul vl\]
+.*:    e4b9e000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, #-14, mul vl\]
+.*:    e4bfe000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, #-2, mul vl\]
+.*:    e4bfe000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, #-2, mul vl\]
+.*:    e4bfe000        st2h    \{z0\.h, z1\.h\}, p0, \[x0, #-2, mul vl\]
+.*:    e5206000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5206000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5206000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5206001        st2w    \{z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5206001        st2w    \{z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5206001        st2w    \{z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e520601f        st2w    \{z31\.s, z0\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e520601f        st2w    \{z31\.s, z0\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5206800        st2w    \{z0\.s, z1\.s\}, p2, \[x0, x0, lsl #2\]
+.*:    e5206800        st2w    \{z0\.s, z1\.s\}, p2, \[x0, x0, lsl #2\]
+.*:    e5206800        st2w    \{z0\.s, z1\.s\}, p2, \[x0, x0, lsl #2\]
+.*:    e5207c00        st2w    \{z0\.s, z1\.s\}, p7, \[x0, x0, lsl #2\]
+.*:    e5207c00        st2w    \{z0\.s, z1\.s\}, p7, \[x0, x0, lsl #2\]
+.*:    e5207c00        st2w    \{z0\.s, z1\.s\}, p7, \[x0, x0, lsl #2\]
+.*:    e5206060        st2w    \{z0\.s, z1\.s\}, p0, \[x3, x0, lsl #2\]
+.*:    e5206060        st2w    \{z0\.s, z1\.s\}, p0, \[x3, x0, lsl #2\]
+.*:    e5206060        st2w    \{z0\.s, z1\.s\}, p0, \[x3, x0, lsl #2\]
+.*:    e52063e0        st2w    \{z0\.s, z1\.s\}, p0, \[sp, x0, lsl #2\]
+.*:    e52063e0        st2w    \{z0\.s, z1\.s\}, p0, \[sp, x0, lsl #2\]
+.*:    e52063e0        st2w    \{z0\.s, z1\.s\}, p0, \[sp, x0, lsl #2\]
+.*:    e5246000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, x4, lsl #2\]
+.*:    e5246000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, x4, lsl #2\]
+.*:    e5246000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, x4, lsl #2\]
+.*:    e53e6000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, x30, lsl #2\]
+.*:    e53e6000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, x30, lsl #2\]
+.*:    e53e6000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, x30, lsl #2\]
 .*:    e530e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0\]
 .*:    e530e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0\]
 .*:    e530e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0\]
@@ -30854,61 +30854,61 @@ Disassembly of section .*:
 .*:    e530e3e0        st2w    \{z0\.s, z1\.s\}, p0, \[sp\]
 .*:    e530e3e0        st2w    \{z0\.s, z1\.s\}, p0, \[sp\]
 .*:    e530e3e0        st2w    \{z0\.s, z1\.s\}, p0, \[sp\]
-.*:    e537e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,#14,mul vl\]
-.*:    e537e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,#14,mul vl\]
-.*:    e537e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,#14,mul vl\]
-.*:    e538e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,#-16,mul vl\]
-.*:    e538e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,#-16,mul vl\]
-.*:    e538e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,#-16,mul vl\]
-.*:    e539e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,#-14,mul vl\]
-.*:    e539e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,#-14,mul vl\]
-.*:    e539e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,#-14,mul vl\]
-.*:    e53fe000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,#-2,mul vl\]
-.*:    e53fe000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,#-2,mul vl\]
-.*:    e53fe000        st2w    \{z0\.s, z1\.s\}, p0, \[x0,#-2,mul vl\]
-.*:    e4406000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x0\]
-.*:    e4406000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x0\]
-.*:    e4406000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x0\]
-.*:    e4406000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x0\]
-.*:    e4406000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x0\]
-.*:    e4406001        st3b    \{z1\.b-z3\.b\}, p0, \[x0,x0\]
-.*:    e4406001        st3b    \{z1\.b-z3\.b\}, p0, \[x0,x0\]
-.*:    e4406001        st3b    \{z1\.b-z3\.b\}, p0, \[x0,x0\]
-.*:    e4406001        st3b    \{z1\.b-z3\.b\}, p0, \[x0,x0\]
-.*:    e4406001        st3b    \{z1\.b-z3\.b\}, p0, \[x0,x0\]
-.*:    e440601f        st3b    \{z31\.b, z0\.b, z1\.b\}, p0, \[x0,x0\]
-.*:    e440601f        st3b    \{z31\.b, z0\.b, z1\.b\}, p0, \[x0,x0\]
-.*:    e440601f        st3b    \{z31\.b, z0\.b, z1\.b\}, p0, \[x0,x0\]
-.*:    e4406800        st3b    \{z0\.b-z2\.b\}, p2, \[x0,x0\]
-.*:    e4406800        st3b    \{z0\.b-z2\.b\}, p2, \[x0,x0\]
-.*:    e4406800        st3b    \{z0\.b-z2\.b\}, p2, \[x0,x0\]
-.*:    e4406800        st3b    \{z0\.b-z2\.b\}, p2, \[x0,x0\]
-.*:    e4406800        st3b    \{z0\.b-z2\.b\}, p2, \[x0,x0\]
-.*:    e4407c00        st3b    \{z0\.b-z2\.b\}, p7, \[x0,x0\]
-.*:    e4407c00        st3b    \{z0\.b-z2\.b\}, p7, \[x0,x0\]
-.*:    e4407c00        st3b    \{z0\.b-z2\.b\}, p7, \[x0,x0\]
-.*:    e4407c00        st3b    \{z0\.b-z2\.b\}, p7, \[x0,x0\]
-.*:    e4407c00        st3b    \{z0\.b-z2\.b\}, p7, \[x0,x0\]
-.*:    e4406060        st3b    \{z0\.b-z2\.b\}, p0, \[x3,x0\]
-.*:    e4406060        st3b    \{z0\.b-z2\.b\}, p0, \[x3,x0\]
-.*:    e4406060        st3b    \{z0\.b-z2\.b\}, p0, \[x3,x0\]
-.*:    e4406060        st3b    \{z0\.b-z2\.b\}, p0, \[x3,x0\]
-.*:    e4406060        st3b    \{z0\.b-z2\.b\}, p0, \[x3,x0\]
-.*:    e44063e0        st3b    \{z0\.b-z2\.b\}, p0, \[sp,x0\]
-.*:    e44063e0        st3b    \{z0\.b-z2\.b\}, p0, \[sp,x0\]
-.*:    e44063e0        st3b    \{z0\.b-z2\.b\}, p0, \[sp,x0\]
-.*:    e44063e0        st3b    \{z0\.b-z2\.b\}, p0, \[sp,x0\]
-.*:    e44063e0        st3b    \{z0\.b-z2\.b\}, p0, \[sp,x0\]
-.*:    e4446000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x4\]
-.*:    e4446000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x4\]
-.*:    e4446000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x4\]
-.*:    e4446000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x4\]
-.*:    e4446000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x4\]
-.*:    e45e6000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x30\]
-.*:    e45e6000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x30\]
-.*:    e45e6000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x30\]
-.*:    e45e6000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x30\]
-.*:    e45e6000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,x30\]
+.*:    e537e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, #14, mul vl\]
+.*:    e537e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, #14, mul vl\]
+.*:    e537e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, #14, mul vl\]
+.*:    e538e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, #-16, mul vl\]
+.*:    e538e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, #-16, mul vl\]
+.*:    e538e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, #-16, mul vl\]
+.*:    e539e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, #-14, mul vl\]
+.*:    e539e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, #-14, mul vl\]
+.*:    e539e000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, #-14, mul vl\]
+.*:    e53fe000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, #-2, mul vl\]
+.*:    e53fe000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, #-2, mul vl\]
+.*:    e53fe000        st2w    \{z0\.s, z1\.s\}, p0, \[x0, #-2, mul vl\]
+.*:    e4406000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x0\]
+.*:    e4406000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x0\]
+.*:    e4406000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x0\]
+.*:    e4406000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x0\]
+.*:    e4406000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x0\]
+.*:    e4406001        st3b    \{z1\.b-z3\.b\}, p0, \[x0, x0\]
+.*:    e4406001        st3b    \{z1\.b-z3\.b\}, p0, \[x0, x0\]
+.*:    e4406001        st3b    \{z1\.b-z3\.b\}, p0, \[x0, x0\]
+.*:    e4406001        st3b    \{z1\.b-z3\.b\}, p0, \[x0, x0\]
+.*:    e4406001        st3b    \{z1\.b-z3\.b\}, p0, \[x0, x0\]
+.*:    e440601f        st3b    \{z31\.b, z0\.b, z1\.b\}, p0, \[x0, x0\]
+.*:    e440601f        st3b    \{z31\.b, z0\.b, z1\.b\}, p0, \[x0, x0\]
+.*:    e440601f        st3b    \{z31\.b, z0\.b, z1\.b\}, p0, \[x0, x0\]
+.*:    e4406800        st3b    \{z0\.b-z2\.b\}, p2, \[x0, x0\]
+.*:    e4406800        st3b    \{z0\.b-z2\.b\}, p2, \[x0, x0\]
+.*:    e4406800        st3b    \{z0\.b-z2\.b\}, p2, \[x0, x0\]
+.*:    e4406800        st3b    \{z0\.b-z2\.b\}, p2, \[x0, x0\]
+.*:    e4406800        st3b    \{z0\.b-z2\.b\}, p2, \[x0, x0\]
+.*:    e4407c00        st3b    \{z0\.b-z2\.b\}, p7, \[x0, x0\]
+.*:    e4407c00        st3b    \{z0\.b-z2\.b\}, p7, \[x0, x0\]
+.*:    e4407c00        st3b    \{z0\.b-z2\.b\}, p7, \[x0, x0\]
+.*:    e4407c00        st3b    \{z0\.b-z2\.b\}, p7, \[x0, x0\]
+.*:    e4407c00        st3b    \{z0\.b-z2\.b\}, p7, \[x0, x0\]
+.*:    e4406060        st3b    \{z0\.b-z2\.b\}, p0, \[x3, x0\]
+.*:    e4406060        st3b    \{z0\.b-z2\.b\}, p0, \[x3, x0\]
+.*:    e4406060        st3b    \{z0\.b-z2\.b\}, p0, \[x3, x0\]
+.*:    e4406060        st3b    \{z0\.b-z2\.b\}, p0, \[x3, x0\]
+.*:    e4406060        st3b    \{z0\.b-z2\.b\}, p0, \[x3, x0\]
+.*:    e44063e0        st3b    \{z0\.b-z2\.b\}, p0, \[sp, x0\]
+.*:    e44063e0        st3b    \{z0\.b-z2\.b\}, p0, \[sp, x0\]
+.*:    e44063e0        st3b    \{z0\.b-z2\.b\}, p0, \[sp, x0\]
+.*:    e44063e0        st3b    \{z0\.b-z2\.b\}, p0, \[sp, x0\]
+.*:    e44063e0        st3b    \{z0\.b-z2\.b\}, p0, \[sp, x0\]
+.*:    e4446000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x4\]
+.*:    e4446000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x4\]
+.*:    e4446000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x4\]
+.*:    e4446000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x4\]
+.*:    e4446000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x4\]
+.*:    e45e6000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x30\]
+.*:    e45e6000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x30\]
+.*:    e45e6000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x30\]
+.*:    e45e6000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x30\]
+.*:    e45e6000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, x30\]
 .*:    e450e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0\]
 .*:    e450e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0\]
 .*:    e450e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0\]
@@ -30955,44 +30955,44 @@ Disassembly of section .*:
 .*:    e450e3e0        st3b    \{z0\.b-z2\.b\}, p0, \[sp\]
 .*:    e450e3e0        st3b    \{z0\.b-z2\.b\}, p0, \[sp\]
 .*:    e450e3e0        st3b    \{z0\.b-z2\.b\}, p0, \[sp\]
-.*:    e457e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,#21,mul vl\]
-.*:    e457e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,#21,mul vl\]
-.*:    e457e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,#21,mul vl\]
-.*:    e458e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,#-24,mul vl\]
-.*:    e458e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,#-24,mul vl\]
-.*:    e458e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,#-24,mul vl\]
-.*:    e459e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,#-21,mul vl\]
-.*:    e459e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,#-21,mul vl\]
-.*:    e459e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,#-21,mul vl\]
-.*:    e45fe000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,#-3,mul vl\]
-.*:    e45fe000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,#-3,mul vl\]
-.*:    e45fe000        st3b    \{z0\.b-z2\.b\}, p0, \[x0,#-3,mul vl\]
-.*:    e5c06000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5c06000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5c06000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5c06001        st3d    \{z1\.d-z3\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5c06001        st3d    \{z1\.d-z3\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5c06001        st3d    \{z1\.d-z3\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5c0601f        st3d    \{z31\.d, z0\.d, z1\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5c0601f        st3d    \{z31\.d, z0\.d, z1\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5c06800        st3d    \{z0\.d-z2\.d\}, p2, \[x0,x0,lsl #3\]
-.*:    e5c06800        st3d    \{z0\.d-z2\.d\}, p2, \[x0,x0,lsl #3\]
-.*:    e5c06800        st3d    \{z0\.d-z2\.d\}, p2, \[x0,x0,lsl #3\]
-.*:    e5c07c00        st3d    \{z0\.d-z2\.d\}, p7, \[x0,x0,lsl #3\]
-.*:    e5c07c00        st3d    \{z0\.d-z2\.d\}, p7, \[x0,x0,lsl #3\]
-.*:    e5c07c00        st3d    \{z0\.d-z2\.d\}, p7, \[x0,x0,lsl #3\]
-.*:    e5c06060        st3d    \{z0\.d-z2\.d\}, p0, \[x3,x0,lsl #3\]
-.*:    e5c06060        st3d    \{z0\.d-z2\.d\}, p0, \[x3,x0,lsl #3\]
-.*:    e5c06060        st3d    \{z0\.d-z2\.d\}, p0, \[x3,x0,lsl #3\]
-.*:    e5c063e0        st3d    \{z0\.d-z2\.d\}, p0, \[sp,x0,lsl #3\]
-.*:    e5c063e0        st3d    \{z0\.d-z2\.d\}, p0, \[sp,x0,lsl #3\]
-.*:    e5c063e0        st3d    \{z0\.d-z2\.d\}, p0, \[sp,x0,lsl #3\]
-.*:    e5c46000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,x4,lsl #3\]
-.*:    e5c46000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,x4,lsl #3\]
-.*:    e5c46000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,x4,lsl #3\]
-.*:    e5de6000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,x30,lsl #3\]
-.*:    e5de6000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,x30,lsl #3\]
-.*:    e5de6000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,x30,lsl #3\]
+.*:    e457e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, #21, mul vl\]
+.*:    e457e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, #21, mul vl\]
+.*:    e457e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, #21, mul vl\]
+.*:    e458e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, #-24, mul vl\]
+.*:    e458e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, #-24, mul vl\]
+.*:    e458e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, #-24, mul vl\]
+.*:    e459e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, #-21, mul vl\]
+.*:    e459e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, #-21, mul vl\]
+.*:    e459e000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, #-21, mul vl\]
+.*:    e45fe000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, #-3, mul vl\]
+.*:    e45fe000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, #-3, mul vl\]
+.*:    e45fe000        st3b    \{z0\.b-z2\.b\}, p0, \[x0, #-3, mul vl\]
+.*:    e5c06000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5c06000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5c06000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5c06001        st3d    \{z1\.d-z3\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5c06001        st3d    \{z1\.d-z3\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5c06001        st3d    \{z1\.d-z3\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5c0601f        st3d    \{z31\.d, z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5c0601f        st3d    \{z31\.d, z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5c06800        st3d    \{z0\.d-z2\.d\}, p2, \[x0, x0, lsl #3\]
+.*:    e5c06800        st3d    \{z0\.d-z2\.d\}, p2, \[x0, x0, lsl #3\]
+.*:    e5c06800        st3d    \{z0\.d-z2\.d\}, p2, \[x0, x0, lsl #3\]
+.*:    e5c07c00        st3d    \{z0\.d-z2\.d\}, p7, \[x0, x0, lsl #3\]
+.*:    e5c07c00        st3d    \{z0\.d-z2\.d\}, p7, \[x0, x0, lsl #3\]
+.*:    e5c07c00        st3d    \{z0\.d-z2\.d\}, p7, \[x0, x0, lsl #3\]
+.*:    e5c06060        st3d    \{z0\.d-z2\.d\}, p0, \[x3, x0, lsl #3\]
+.*:    e5c06060        st3d    \{z0\.d-z2\.d\}, p0, \[x3, x0, lsl #3\]
+.*:    e5c06060        st3d    \{z0\.d-z2\.d\}, p0, \[x3, x0, lsl #3\]
+.*:    e5c063e0        st3d    \{z0\.d-z2\.d\}, p0, \[sp, x0, lsl #3\]
+.*:    e5c063e0        st3d    \{z0\.d-z2\.d\}, p0, \[sp, x0, lsl #3\]
+.*:    e5c063e0        st3d    \{z0\.d-z2\.d\}, p0, \[sp, x0, lsl #3\]
+.*:    e5c46000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, x4, lsl #3\]
+.*:    e5c46000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, x4, lsl #3\]
+.*:    e5c46000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, x4, lsl #3\]
+.*:    e5de6000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, x30, lsl #3\]
+.*:    e5de6000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, x30, lsl #3\]
+.*:    e5de6000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, x30, lsl #3\]
 .*:    e5d0e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0\]
 .*:    e5d0e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0\]
 .*:    e5d0e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0\]
@@ -31039,44 +31039,44 @@ Disassembly of section .*:
 .*:    e5d0e3e0        st3d    \{z0\.d-z2\.d\}, p0, \[sp\]
 .*:    e5d0e3e0        st3d    \{z0\.d-z2\.d\}, p0, \[sp\]
 .*:    e5d0e3e0        st3d    \{z0\.d-z2\.d\}, p0, \[sp\]
-.*:    e5d7e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,#21,mul vl\]
-.*:    e5d7e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,#21,mul vl\]
-.*:    e5d7e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,#21,mul vl\]
-.*:    e5d8e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,#-24,mul vl\]
-.*:    e5d8e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,#-24,mul vl\]
-.*:    e5d8e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,#-24,mul vl\]
-.*:    e5d9e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,#-21,mul vl\]
-.*:    e5d9e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,#-21,mul vl\]
-.*:    e5d9e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,#-21,mul vl\]
-.*:    e5dfe000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,#-3,mul vl\]
-.*:    e5dfe000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,#-3,mul vl\]
-.*:    e5dfe000        st3d    \{z0\.d-z2\.d\}, p0, \[x0,#-3,mul vl\]
-.*:    e4c06000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c06000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c06000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c06001        st3h    \{z1\.h-z3\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c06001        st3h    \{z1\.h-z3\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c06001        st3h    \{z1\.h-z3\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c0601f        st3h    \{z31\.h, z0\.h, z1\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c0601f        st3h    \{z31\.h, z0\.h, z1\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4c06800        st3h    \{z0\.h-z2\.h\}, p2, \[x0,x0,lsl #1\]
-.*:    e4c06800        st3h    \{z0\.h-z2\.h\}, p2, \[x0,x0,lsl #1\]
-.*:    e4c06800        st3h    \{z0\.h-z2\.h\}, p2, \[x0,x0,lsl #1\]
-.*:    e4c07c00        st3h    \{z0\.h-z2\.h\}, p7, \[x0,x0,lsl #1\]
-.*:    e4c07c00        st3h    \{z0\.h-z2\.h\}, p7, \[x0,x0,lsl #1\]
-.*:    e4c07c00        st3h    \{z0\.h-z2\.h\}, p7, \[x0,x0,lsl #1\]
-.*:    e4c06060        st3h    \{z0\.h-z2\.h\}, p0, \[x3,x0,lsl #1\]
-.*:    e4c06060        st3h    \{z0\.h-z2\.h\}, p0, \[x3,x0,lsl #1\]
-.*:    e4c06060        st3h    \{z0\.h-z2\.h\}, p0, \[x3,x0,lsl #1\]
-.*:    e4c063e0        st3h    \{z0\.h-z2\.h\}, p0, \[sp,x0,lsl #1\]
-.*:    e4c063e0        st3h    \{z0\.h-z2\.h\}, p0, \[sp,x0,lsl #1\]
-.*:    e4c063e0        st3h    \{z0\.h-z2\.h\}, p0, \[sp,x0,lsl #1\]
-.*:    e4c46000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,x4,lsl #1\]
-.*:    e4c46000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,x4,lsl #1\]
-.*:    e4c46000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,x4,lsl #1\]
-.*:    e4de6000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,x30,lsl #1\]
-.*:    e4de6000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,x30,lsl #1\]
-.*:    e4de6000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,x30,lsl #1\]
+.*:    e5d7e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, #21, mul vl\]
+.*:    e5d7e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, #21, mul vl\]
+.*:    e5d7e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, #21, mul vl\]
+.*:    e5d8e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, #-24, mul vl\]
+.*:    e5d8e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, #-24, mul vl\]
+.*:    e5d8e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, #-24, mul vl\]
+.*:    e5d9e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, #-21, mul vl\]
+.*:    e5d9e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, #-21, mul vl\]
+.*:    e5d9e000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, #-21, mul vl\]
+.*:    e5dfe000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, #-3, mul vl\]
+.*:    e5dfe000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, #-3, mul vl\]
+.*:    e5dfe000        st3d    \{z0\.d-z2\.d\}, p0, \[x0, #-3, mul vl\]
+.*:    e4c06000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c06000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c06000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c06001        st3h    \{z1\.h-z3\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c06001        st3h    \{z1\.h-z3\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c06001        st3h    \{z1\.h-z3\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c0601f        st3h    \{z31\.h, z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c0601f        st3h    \{z31\.h, z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4c06800        st3h    \{z0\.h-z2\.h\}, p2, \[x0, x0, lsl #1\]
+.*:    e4c06800        st3h    \{z0\.h-z2\.h\}, p2, \[x0, x0, lsl #1\]
+.*:    e4c06800        st3h    \{z0\.h-z2\.h\}, p2, \[x0, x0, lsl #1\]
+.*:    e4c07c00        st3h    \{z0\.h-z2\.h\}, p7, \[x0, x0, lsl #1\]
+.*:    e4c07c00        st3h    \{z0\.h-z2\.h\}, p7, \[x0, x0, lsl #1\]
+.*:    e4c07c00        st3h    \{z0\.h-z2\.h\}, p7, \[x0, x0, lsl #1\]
+.*:    e4c06060        st3h    \{z0\.h-z2\.h\}, p0, \[x3, x0, lsl #1\]
+.*:    e4c06060        st3h    \{z0\.h-z2\.h\}, p0, \[x3, x0, lsl #1\]
+.*:    e4c06060        st3h    \{z0\.h-z2\.h\}, p0, \[x3, x0, lsl #1\]
+.*:    e4c063e0        st3h    \{z0\.h-z2\.h\}, p0, \[sp, x0, lsl #1\]
+.*:    e4c063e0        st3h    \{z0\.h-z2\.h\}, p0, \[sp, x0, lsl #1\]
+.*:    e4c063e0        st3h    \{z0\.h-z2\.h\}, p0, \[sp, x0, lsl #1\]
+.*:    e4c46000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, x4, lsl #1\]
+.*:    e4c46000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, x4, lsl #1\]
+.*:    e4c46000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, x4, lsl #1\]
+.*:    e4de6000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, x30, lsl #1\]
+.*:    e4de6000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, x30, lsl #1\]
+.*:    e4de6000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, x30, lsl #1\]
 .*:    e4d0e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0\]
 .*:    e4d0e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0\]
 .*:    e4d0e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0\]
@@ -31123,44 +31123,44 @@ Disassembly of section .*:
 .*:    e4d0e3e0        st3h    \{z0\.h-z2\.h\}, p0, \[sp\]
 .*:    e4d0e3e0        st3h    \{z0\.h-z2\.h\}, p0, \[sp\]
 .*:    e4d0e3e0        st3h    \{z0\.h-z2\.h\}, p0, \[sp\]
-.*:    e4d7e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,#21,mul vl\]
-.*:    e4d7e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,#21,mul vl\]
-.*:    e4d7e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,#21,mul vl\]
-.*:    e4d8e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,#-24,mul vl\]
-.*:    e4d8e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,#-24,mul vl\]
-.*:    e4d8e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,#-24,mul vl\]
-.*:    e4d9e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,#-21,mul vl\]
-.*:    e4d9e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,#-21,mul vl\]
-.*:    e4d9e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,#-21,mul vl\]
-.*:    e4dfe000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,#-3,mul vl\]
-.*:    e4dfe000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,#-3,mul vl\]
-.*:    e4dfe000        st3h    \{z0\.h-z2\.h\}, p0, \[x0,#-3,mul vl\]
-.*:    e5406000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5406000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5406000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5406001        st3w    \{z1\.s-z3\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5406001        st3w    \{z1\.s-z3\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5406001        st3w    \{z1\.s-z3\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e540601f        st3w    \{z31\.s, z0\.s, z1\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e540601f        st3w    \{z31\.s, z0\.s, z1\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5406800        st3w    \{z0\.s-z2\.s\}, p2, \[x0,x0,lsl #2\]
-.*:    e5406800        st3w    \{z0\.s-z2\.s\}, p2, \[x0,x0,lsl #2\]
-.*:    e5406800        st3w    \{z0\.s-z2\.s\}, p2, \[x0,x0,lsl #2\]
-.*:    e5407c00        st3w    \{z0\.s-z2\.s\}, p7, \[x0,x0,lsl #2\]
-.*:    e5407c00        st3w    \{z0\.s-z2\.s\}, p7, \[x0,x0,lsl #2\]
-.*:    e5407c00        st3w    \{z0\.s-z2\.s\}, p7, \[x0,x0,lsl #2\]
-.*:    e5406060        st3w    \{z0\.s-z2\.s\}, p0, \[x3,x0,lsl #2\]
-.*:    e5406060        st3w    \{z0\.s-z2\.s\}, p0, \[x3,x0,lsl #2\]
-.*:    e5406060        st3w    \{z0\.s-z2\.s\}, p0, \[x3,x0,lsl #2\]
-.*:    e54063e0        st3w    \{z0\.s-z2\.s\}, p0, \[sp,x0,lsl #2\]
-.*:    e54063e0        st3w    \{z0\.s-z2\.s\}, p0, \[sp,x0,lsl #2\]
-.*:    e54063e0        st3w    \{z0\.s-z2\.s\}, p0, \[sp,x0,lsl #2\]
-.*:    e5446000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,x4,lsl #2\]
-.*:    e5446000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,x4,lsl #2\]
-.*:    e5446000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,x4,lsl #2\]
-.*:    e55e6000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,x30,lsl #2\]
-.*:    e55e6000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,x30,lsl #2\]
-.*:    e55e6000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,x30,lsl #2\]
+.*:    e4d7e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, #21, mul vl\]
+.*:    e4d7e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, #21, mul vl\]
+.*:    e4d7e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, #21, mul vl\]
+.*:    e4d8e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, #-24, mul vl\]
+.*:    e4d8e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, #-24, mul vl\]
+.*:    e4d8e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, #-24, mul vl\]
+.*:    e4d9e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, #-21, mul vl\]
+.*:    e4d9e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, #-21, mul vl\]
+.*:    e4d9e000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, #-21, mul vl\]
+.*:    e4dfe000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, #-3, mul vl\]
+.*:    e4dfe000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, #-3, mul vl\]
+.*:    e4dfe000        st3h    \{z0\.h-z2\.h\}, p0, \[x0, #-3, mul vl\]
+.*:    e5406000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5406000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5406000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5406001        st3w    \{z1\.s-z3\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5406001        st3w    \{z1\.s-z3\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5406001        st3w    \{z1\.s-z3\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e540601f        st3w    \{z31\.s, z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e540601f        st3w    \{z31\.s, z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5406800        st3w    \{z0\.s-z2\.s\}, p2, \[x0, x0, lsl #2\]
+.*:    e5406800        st3w    \{z0\.s-z2\.s\}, p2, \[x0, x0, lsl #2\]
+.*:    e5406800        st3w    \{z0\.s-z2\.s\}, p2, \[x0, x0, lsl #2\]
+.*:    e5407c00        st3w    \{z0\.s-z2\.s\}, p7, \[x0, x0, lsl #2\]
+.*:    e5407c00        st3w    \{z0\.s-z2\.s\}, p7, \[x0, x0, lsl #2\]
+.*:    e5407c00        st3w    \{z0\.s-z2\.s\}, p7, \[x0, x0, lsl #2\]
+.*:    e5406060        st3w    \{z0\.s-z2\.s\}, p0, \[x3, x0, lsl #2\]
+.*:    e5406060        st3w    \{z0\.s-z2\.s\}, p0, \[x3, x0, lsl #2\]
+.*:    e5406060        st3w    \{z0\.s-z2\.s\}, p0, \[x3, x0, lsl #2\]
+.*:    e54063e0        st3w    \{z0\.s-z2\.s\}, p0, \[sp, x0, lsl #2\]
+.*:    e54063e0        st3w    \{z0\.s-z2\.s\}, p0, \[sp, x0, lsl #2\]
+.*:    e54063e0        st3w    \{z0\.s-z2\.s\}, p0, \[sp, x0, lsl #2\]
+.*:    e5446000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, x4, lsl #2\]
+.*:    e5446000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, x4, lsl #2\]
+.*:    e5446000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, x4, lsl #2\]
+.*:    e55e6000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, x30, lsl #2\]
+.*:    e55e6000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, x30, lsl #2\]
+.*:    e55e6000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, x30, lsl #2\]
 .*:    e550e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0\]
 .*:    e550e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0\]
 .*:    e550e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0\]
@@ -31207,61 +31207,61 @@ Disassembly of section .*:
 .*:    e550e3e0        st3w    \{z0\.s-z2\.s\}, p0, \[sp\]
 .*:    e550e3e0        st3w    \{z0\.s-z2\.s\}, p0, \[sp\]
 .*:    e550e3e0        st3w    \{z0\.s-z2\.s\}, p0, \[sp\]
-.*:    e557e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,#21,mul vl\]
-.*:    e557e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,#21,mul vl\]
-.*:    e557e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,#21,mul vl\]
-.*:    e558e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,#-24,mul vl\]
-.*:    e558e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,#-24,mul vl\]
-.*:    e558e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,#-24,mul vl\]
-.*:    e559e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,#-21,mul vl\]
-.*:    e559e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,#-21,mul vl\]
-.*:    e559e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,#-21,mul vl\]
-.*:    e55fe000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,#-3,mul vl\]
-.*:    e55fe000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,#-3,mul vl\]
-.*:    e55fe000        st3w    \{z0\.s-z2\.s\}, p0, \[x0,#-3,mul vl\]
-.*:    e4606000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x0\]
-.*:    e4606000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x0\]
-.*:    e4606000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x0\]
-.*:    e4606000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x0\]
-.*:    e4606000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x0\]
-.*:    e4606001        st4b    \{z1\.b-z4\.b\}, p0, \[x0,x0\]
-.*:    e4606001        st4b    \{z1\.b-z4\.b\}, p0, \[x0,x0\]
-.*:    e4606001        st4b    \{z1\.b-z4\.b\}, p0, \[x0,x0\]
-.*:    e4606001        st4b    \{z1\.b-z4\.b\}, p0, \[x0,x0\]
-.*:    e4606001        st4b    \{z1\.b-z4\.b\}, p0, \[x0,x0\]
-.*:    e460601f        st4b    \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0,x0\]
-.*:    e460601f        st4b    \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0,x0\]
-.*:    e460601f        st4b    \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0,x0\]
-.*:    e4606800        st4b    \{z0\.b-z3\.b\}, p2, \[x0,x0\]
-.*:    e4606800        st4b    \{z0\.b-z3\.b\}, p2, \[x0,x0\]
-.*:    e4606800        st4b    \{z0\.b-z3\.b\}, p2, \[x0,x0\]
-.*:    e4606800        st4b    \{z0\.b-z3\.b\}, p2, \[x0,x0\]
-.*:    e4606800        st4b    \{z0\.b-z3\.b\}, p2, \[x0,x0\]
-.*:    e4607c00        st4b    \{z0\.b-z3\.b\}, p7, \[x0,x0\]
-.*:    e4607c00        st4b    \{z0\.b-z3\.b\}, p7, \[x0,x0\]
-.*:    e4607c00        st4b    \{z0\.b-z3\.b\}, p7, \[x0,x0\]
-.*:    e4607c00        st4b    \{z0\.b-z3\.b\}, p7, \[x0,x0\]
-.*:    e4607c00        st4b    \{z0\.b-z3\.b\}, p7, \[x0,x0\]
-.*:    e4606060        st4b    \{z0\.b-z3\.b\}, p0, \[x3,x0\]
-.*:    e4606060        st4b    \{z0\.b-z3\.b\}, p0, \[x3,x0\]
-.*:    e4606060        st4b    \{z0\.b-z3\.b\}, p0, \[x3,x0\]
-.*:    e4606060        st4b    \{z0\.b-z3\.b\}, p0, \[x3,x0\]
-.*:    e4606060        st4b    \{z0\.b-z3\.b\}, p0, \[x3,x0\]
-.*:    e46063e0        st4b    \{z0\.b-z3\.b\}, p0, \[sp,x0\]
-.*:    e46063e0        st4b    \{z0\.b-z3\.b\}, p0, \[sp,x0\]
-.*:    e46063e0        st4b    \{z0\.b-z3\.b\}, p0, \[sp,x0\]
-.*:    e46063e0        st4b    \{z0\.b-z3\.b\}, p0, \[sp,x0\]
-.*:    e46063e0        st4b    \{z0\.b-z3\.b\}, p0, \[sp,x0\]
-.*:    e4646000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x4\]
-.*:    e4646000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x4\]
-.*:    e4646000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x4\]
-.*:    e4646000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x4\]
-.*:    e4646000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x4\]
-.*:    e47e6000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x30\]
-.*:    e47e6000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x30\]
-.*:    e47e6000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x30\]
-.*:    e47e6000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x30\]
-.*:    e47e6000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,x30\]
+.*:    e557e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, #21, mul vl\]
+.*:    e557e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, #21, mul vl\]
+.*:    e557e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, #21, mul vl\]
+.*:    e558e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, #-24, mul vl\]
+.*:    e558e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, #-24, mul vl\]
+.*:    e558e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, #-24, mul vl\]
+.*:    e559e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, #-21, mul vl\]
+.*:    e559e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, #-21, mul vl\]
+.*:    e559e000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, #-21, mul vl\]
+.*:    e55fe000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, #-3, mul vl\]
+.*:    e55fe000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, #-3, mul vl\]
+.*:    e55fe000        st3w    \{z0\.s-z2\.s\}, p0, \[x0, #-3, mul vl\]
+.*:    e4606000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x0\]
+.*:    e4606000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x0\]
+.*:    e4606000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x0\]
+.*:    e4606000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x0\]
+.*:    e4606000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x0\]
+.*:    e4606001        st4b    \{z1\.b-z4\.b\}, p0, \[x0, x0\]
+.*:    e4606001        st4b    \{z1\.b-z4\.b\}, p0, \[x0, x0\]
+.*:    e4606001        st4b    \{z1\.b-z4\.b\}, p0, \[x0, x0\]
+.*:    e4606001        st4b    \{z1\.b-z4\.b\}, p0, \[x0, x0\]
+.*:    e4606001        st4b    \{z1\.b-z4\.b\}, p0, \[x0, x0\]
+.*:    e460601f        st4b    \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0, x0\]
+.*:    e460601f        st4b    \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0, x0\]
+.*:    e460601f        st4b    \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0, x0\]
+.*:    e4606800        st4b    \{z0\.b-z3\.b\}, p2, \[x0, x0\]
+.*:    e4606800        st4b    \{z0\.b-z3\.b\}, p2, \[x0, x0\]
+.*:    e4606800        st4b    \{z0\.b-z3\.b\}, p2, \[x0, x0\]
+.*:    e4606800        st4b    \{z0\.b-z3\.b\}, p2, \[x0, x0\]
+.*:    e4606800        st4b    \{z0\.b-z3\.b\}, p2, \[x0, x0\]
+.*:    e4607c00        st4b    \{z0\.b-z3\.b\}, p7, \[x0, x0\]
+.*:    e4607c00        st4b    \{z0\.b-z3\.b\}, p7, \[x0, x0\]
+.*:    e4607c00        st4b    \{z0\.b-z3\.b\}, p7, \[x0, x0\]
+.*:    e4607c00        st4b    \{z0\.b-z3\.b\}, p7, \[x0, x0\]
+.*:    e4607c00        st4b    \{z0\.b-z3\.b\}, p7, \[x0, x0\]
+.*:    e4606060        st4b    \{z0\.b-z3\.b\}, p0, \[x3, x0\]
+.*:    e4606060        st4b    \{z0\.b-z3\.b\}, p0, \[x3, x0\]
+.*:    e4606060        st4b    \{z0\.b-z3\.b\}, p0, \[x3, x0\]
+.*:    e4606060        st4b    \{z0\.b-z3\.b\}, p0, \[x3, x0\]
+.*:    e4606060        st4b    \{z0\.b-z3\.b\}, p0, \[x3, x0\]
+.*:    e46063e0        st4b    \{z0\.b-z3\.b\}, p0, \[sp, x0\]
+.*:    e46063e0        st4b    \{z0\.b-z3\.b\}, p0, \[sp, x0\]
+.*:    e46063e0        st4b    \{z0\.b-z3\.b\}, p0, \[sp, x0\]
+.*:    e46063e0        st4b    \{z0\.b-z3\.b\}, p0, \[sp, x0\]
+.*:    e46063e0        st4b    \{z0\.b-z3\.b\}, p0, \[sp, x0\]
+.*:    e4646000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x4\]
+.*:    e4646000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x4\]
+.*:    e4646000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x4\]
+.*:    e4646000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x4\]
+.*:    e4646000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x4\]
+.*:    e47e6000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x30\]
+.*:    e47e6000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x30\]
+.*:    e47e6000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x30\]
+.*:    e47e6000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x30\]
+.*:    e47e6000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, x30\]
 .*:    e470e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0\]
 .*:    e470e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0\]
 .*:    e470e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0\]
@@ -31308,44 +31308,44 @@ Disassembly of section .*:
 .*:    e470e3e0        st4b    \{z0\.b-z3\.b\}, p0, \[sp\]
 .*:    e470e3e0        st4b    \{z0\.b-z3\.b\}, p0, \[sp\]
 .*:    e470e3e0        st4b    \{z0\.b-z3\.b\}, p0, \[sp\]
-.*:    e477e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,#28,mul vl\]
-.*:    e477e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,#28,mul vl\]
-.*:    e477e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,#28,mul vl\]
-.*:    e478e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,#-32,mul vl\]
-.*:    e478e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,#-32,mul vl\]
-.*:    e478e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,#-32,mul vl\]
-.*:    e479e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,#-28,mul vl\]
-.*:    e479e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,#-28,mul vl\]
-.*:    e479e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,#-28,mul vl\]
-.*:    e47fe000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,#-4,mul vl\]
-.*:    e47fe000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,#-4,mul vl\]
-.*:    e47fe000        st4b    \{z0\.b-z3\.b\}, p0, \[x0,#-4,mul vl\]
-.*:    e5e06000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e06000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e06000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e06001        st4d    \{z1\.d-z4\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e06001        st4d    \{z1\.d-z4\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e06001        st4d    \{z1\.d-z4\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e0601f        st4d    \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e0601f        st4d    \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5e06800        st4d    \{z0\.d-z3\.d\}, p2, \[x0,x0,lsl #3\]
-.*:    e5e06800        st4d    \{z0\.d-z3\.d\}, p2, \[x0,x0,lsl #3\]
-.*:    e5e06800        st4d    \{z0\.d-z3\.d\}, p2, \[x0,x0,lsl #3\]
-.*:    e5e07c00        st4d    \{z0\.d-z3\.d\}, p7, \[x0,x0,lsl #3\]
-.*:    e5e07c00        st4d    \{z0\.d-z3\.d\}, p7, \[x0,x0,lsl #3\]
-.*:    e5e07c00        st4d    \{z0\.d-z3\.d\}, p7, \[x0,x0,lsl #3\]
-.*:    e5e06060        st4d    \{z0\.d-z3\.d\}, p0, \[x3,x0,lsl #3\]
-.*:    e5e06060        st4d    \{z0\.d-z3\.d\}, p0, \[x3,x0,lsl #3\]
-.*:    e5e06060        st4d    \{z0\.d-z3\.d\}, p0, \[x3,x0,lsl #3\]
-.*:    e5e063e0        st4d    \{z0\.d-z3\.d\}, p0, \[sp,x0,lsl #3\]
-.*:    e5e063e0        st4d    \{z0\.d-z3\.d\}, p0, \[sp,x0,lsl #3\]
-.*:    e5e063e0        st4d    \{z0\.d-z3\.d\}, p0, \[sp,x0,lsl #3\]
-.*:    e5e46000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,x4,lsl #3\]
-.*:    e5e46000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,x4,lsl #3\]
-.*:    e5e46000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,x4,lsl #3\]
-.*:    e5fe6000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,x30,lsl #3\]
-.*:    e5fe6000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,x30,lsl #3\]
-.*:    e5fe6000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,x30,lsl #3\]
+.*:    e477e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, #28, mul vl\]
+.*:    e477e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, #28, mul vl\]
+.*:    e477e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, #28, mul vl\]
+.*:    e478e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, #-32, mul vl\]
+.*:    e478e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, #-32, mul vl\]
+.*:    e478e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, #-32, mul vl\]
+.*:    e479e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, #-28, mul vl\]
+.*:    e479e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, #-28, mul vl\]
+.*:    e479e000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, #-28, mul vl\]
+.*:    e47fe000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, #-4, mul vl\]
+.*:    e47fe000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, #-4, mul vl\]
+.*:    e47fe000        st4b    \{z0\.b-z3\.b\}, p0, \[x0, #-4, mul vl\]
+.*:    e5e06000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e06000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e06000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e06001        st4d    \{z1\.d-z4\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e06001        st4d    \{z1\.d-z4\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e06001        st4d    \{z1\.d-z4\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e0601f        st4d    \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e0601f        st4d    \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5e06800        st4d    \{z0\.d-z3\.d\}, p2, \[x0, x0, lsl #3\]
+.*:    e5e06800        st4d    \{z0\.d-z3\.d\}, p2, \[x0, x0, lsl #3\]
+.*:    e5e06800        st4d    \{z0\.d-z3\.d\}, p2, \[x0, x0, lsl #3\]
+.*:    e5e07c00        st4d    \{z0\.d-z3\.d\}, p7, \[x0, x0, lsl #3\]
+.*:    e5e07c00        st4d    \{z0\.d-z3\.d\}, p7, \[x0, x0, lsl #3\]
+.*:    e5e07c00        st4d    \{z0\.d-z3\.d\}, p7, \[x0, x0, lsl #3\]
+.*:    e5e06060        st4d    \{z0\.d-z3\.d\}, p0, \[x3, x0, lsl #3\]
+.*:    e5e06060        st4d    \{z0\.d-z3\.d\}, p0, \[x3, x0, lsl #3\]
+.*:    e5e06060        st4d    \{z0\.d-z3\.d\}, p0, \[x3, x0, lsl #3\]
+.*:    e5e063e0        st4d    \{z0\.d-z3\.d\}, p0, \[sp, x0, lsl #3\]
+.*:    e5e063e0        st4d    \{z0\.d-z3\.d\}, p0, \[sp, x0, lsl #3\]
+.*:    e5e063e0        st4d    \{z0\.d-z3\.d\}, p0, \[sp, x0, lsl #3\]
+.*:    e5e46000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, x4, lsl #3\]
+.*:    e5e46000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, x4, lsl #3\]
+.*:    e5e46000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, x4, lsl #3\]
+.*:    e5fe6000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, x30, lsl #3\]
+.*:    e5fe6000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, x30, lsl #3\]
+.*:    e5fe6000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, x30, lsl #3\]
 .*:    e5f0e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0\]
 .*:    e5f0e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0\]
 .*:    e5f0e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0\]
@@ -31392,44 +31392,44 @@ Disassembly of section .*:
 .*:    e5f0e3e0        st4d    \{z0\.d-z3\.d\}, p0, \[sp\]
 .*:    e5f0e3e0        st4d    \{z0\.d-z3\.d\}, p0, \[sp\]
 .*:    e5f0e3e0        st4d    \{z0\.d-z3\.d\}, p0, \[sp\]
-.*:    e5f7e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,#28,mul vl\]
-.*:    e5f7e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,#28,mul vl\]
-.*:    e5f7e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,#28,mul vl\]
-.*:    e5f8e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,#-32,mul vl\]
-.*:    e5f8e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,#-32,mul vl\]
-.*:    e5f8e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,#-32,mul vl\]
-.*:    e5f9e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,#-28,mul vl\]
-.*:    e5f9e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,#-28,mul vl\]
-.*:    e5f9e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,#-28,mul vl\]
-.*:    e5ffe000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,#-4,mul vl\]
-.*:    e5ffe000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,#-4,mul vl\]
-.*:    e5ffe000        st4d    \{z0\.d-z3\.d\}, p0, \[x0,#-4,mul vl\]
-.*:    e4e06000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e06000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e06000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e06001        st4h    \{z1\.h-z4\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e06001        st4h    \{z1\.h-z4\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e06001        st4h    \{z1\.h-z4\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e0601f        st4h    \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e0601f        st4h    \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4e06800        st4h    \{z0\.h-z3\.h\}, p2, \[x0,x0,lsl #1\]
-.*:    e4e06800        st4h    \{z0\.h-z3\.h\}, p2, \[x0,x0,lsl #1\]
-.*:    e4e06800        st4h    \{z0\.h-z3\.h\}, p2, \[x0,x0,lsl #1\]
-.*:    e4e07c00        st4h    \{z0\.h-z3\.h\}, p7, \[x0,x0,lsl #1\]
-.*:    e4e07c00        st4h    \{z0\.h-z3\.h\}, p7, \[x0,x0,lsl #1\]
-.*:    e4e07c00        st4h    \{z0\.h-z3\.h\}, p7, \[x0,x0,lsl #1\]
-.*:    e4e06060        st4h    \{z0\.h-z3\.h\}, p0, \[x3,x0,lsl #1\]
-.*:    e4e06060        st4h    \{z0\.h-z3\.h\}, p0, \[x3,x0,lsl #1\]
-.*:    e4e06060        st4h    \{z0\.h-z3\.h\}, p0, \[x3,x0,lsl #1\]
-.*:    e4e063e0        st4h    \{z0\.h-z3\.h\}, p0, \[sp,x0,lsl #1\]
-.*:    e4e063e0        st4h    \{z0\.h-z3\.h\}, p0, \[sp,x0,lsl #1\]
-.*:    e4e063e0        st4h    \{z0\.h-z3\.h\}, p0, \[sp,x0,lsl #1\]
-.*:    e4e46000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,x4,lsl #1\]
-.*:    e4e46000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,x4,lsl #1\]
-.*:    e4e46000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,x4,lsl #1\]
-.*:    e4fe6000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,x30,lsl #1\]
-.*:    e4fe6000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,x30,lsl #1\]
-.*:    e4fe6000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,x30,lsl #1\]
+.*:    e5f7e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, #28, mul vl\]
+.*:    e5f7e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, #28, mul vl\]
+.*:    e5f7e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, #28, mul vl\]
+.*:    e5f8e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, #-32, mul vl\]
+.*:    e5f8e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, #-32, mul vl\]
+.*:    e5f8e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, #-32, mul vl\]
+.*:    e5f9e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, #-28, mul vl\]
+.*:    e5f9e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, #-28, mul vl\]
+.*:    e5f9e000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, #-28, mul vl\]
+.*:    e5ffe000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, #-4, mul vl\]
+.*:    e5ffe000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, #-4, mul vl\]
+.*:    e5ffe000        st4d    \{z0\.d-z3\.d\}, p0, \[x0, #-4, mul vl\]
+.*:    e4e06000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e06000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e06000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e06001        st4h    \{z1\.h-z4\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e06001        st4h    \{z1\.h-z4\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e06001        st4h    \{z1\.h-z4\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e0601f        st4h    \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e0601f        st4h    \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4e06800        st4h    \{z0\.h-z3\.h\}, p2, \[x0, x0, lsl #1\]
+.*:    e4e06800        st4h    \{z0\.h-z3\.h\}, p2, \[x0, x0, lsl #1\]
+.*:    e4e06800        st4h    \{z0\.h-z3\.h\}, p2, \[x0, x0, lsl #1\]
+.*:    e4e07c00        st4h    \{z0\.h-z3\.h\}, p7, \[x0, x0, lsl #1\]
+.*:    e4e07c00        st4h    \{z0\.h-z3\.h\}, p7, \[x0, x0, lsl #1\]
+.*:    e4e07c00        st4h    \{z0\.h-z3\.h\}, p7, \[x0, x0, lsl #1\]
+.*:    e4e06060        st4h    \{z0\.h-z3\.h\}, p0, \[x3, x0, lsl #1\]
+.*:    e4e06060        st4h    \{z0\.h-z3\.h\}, p0, \[x3, x0, lsl #1\]
+.*:    e4e06060        st4h    \{z0\.h-z3\.h\}, p0, \[x3, x0, lsl #1\]
+.*:    e4e063e0        st4h    \{z0\.h-z3\.h\}, p0, \[sp, x0, lsl #1\]
+.*:    e4e063e0        st4h    \{z0\.h-z3\.h\}, p0, \[sp, x0, lsl #1\]
+.*:    e4e063e0        st4h    \{z0\.h-z3\.h\}, p0, \[sp, x0, lsl #1\]
+.*:    e4e46000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, x4, lsl #1\]
+.*:    e4e46000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, x4, lsl #1\]
+.*:    e4e46000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, x4, lsl #1\]
+.*:    e4fe6000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, x30, lsl #1\]
+.*:    e4fe6000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, x30, lsl #1\]
+.*:    e4fe6000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, x30, lsl #1\]
 .*:    e4f0e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0\]
 .*:    e4f0e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0\]
 .*:    e4f0e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0\]
@@ -31476,44 +31476,44 @@ Disassembly of section .*:
 .*:    e4f0e3e0        st4h    \{z0\.h-z3\.h\}, p0, \[sp\]
 .*:    e4f0e3e0        st4h    \{z0\.h-z3\.h\}, p0, \[sp\]
 .*:    e4f0e3e0        st4h    \{z0\.h-z3\.h\}, p0, \[sp\]
-.*:    e4f7e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,#28,mul vl\]
-.*:    e4f7e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,#28,mul vl\]
-.*:    e4f7e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,#28,mul vl\]
-.*:    e4f8e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,#-32,mul vl\]
-.*:    e4f8e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,#-32,mul vl\]
-.*:    e4f8e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,#-32,mul vl\]
-.*:    e4f9e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,#-28,mul vl\]
-.*:    e4f9e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,#-28,mul vl\]
-.*:    e4f9e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,#-28,mul vl\]
-.*:    e4ffe000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,#-4,mul vl\]
-.*:    e4ffe000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,#-4,mul vl\]
-.*:    e4ffe000        st4h    \{z0\.h-z3\.h\}, p0, \[x0,#-4,mul vl\]
-.*:    e5606000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5606000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5606000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5606001        st4w    \{z1\.s-z4\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5606001        st4w    \{z1\.s-z4\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5606001        st4w    \{z1\.s-z4\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e560601f        st4w    \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e560601f        st4w    \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5606800        st4w    \{z0\.s-z3\.s\}, p2, \[x0,x0,lsl #2\]
-.*:    e5606800        st4w    \{z0\.s-z3\.s\}, p2, \[x0,x0,lsl #2\]
-.*:    e5606800        st4w    \{z0\.s-z3\.s\}, p2, \[x0,x0,lsl #2\]
-.*:    e5607c00        st4w    \{z0\.s-z3\.s\}, p7, \[x0,x0,lsl #2\]
-.*:    e5607c00        st4w    \{z0\.s-z3\.s\}, p7, \[x0,x0,lsl #2\]
-.*:    e5607c00        st4w    \{z0\.s-z3\.s\}, p7, \[x0,x0,lsl #2\]
-.*:    e5606060        st4w    \{z0\.s-z3\.s\}, p0, \[x3,x0,lsl #2\]
-.*:    e5606060        st4w    \{z0\.s-z3\.s\}, p0, \[x3,x0,lsl #2\]
-.*:    e5606060        st4w    \{z0\.s-z3\.s\}, p0, \[x3,x0,lsl #2\]
-.*:    e56063e0        st4w    \{z0\.s-z3\.s\}, p0, \[sp,x0,lsl #2\]
-.*:    e56063e0        st4w    \{z0\.s-z3\.s\}, p0, \[sp,x0,lsl #2\]
-.*:    e56063e0        st4w    \{z0\.s-z3\.s\}, p0, \[sp,x0,lsl #2\]
-.*:    e5646000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,x4,lsl #2\]
-.*:    e5646000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,x4,lsl #2\]
-.*:    e5646000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,x4,lsl #2\]
-.*:    e57e6000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,x30,lsl #2\]
-.*:    e57e6000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,x30,lsl #2\]
-.*:    e57e6000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,x30,lsl #2\]
+.*:    e4f7e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, #28, mul vl\]
+.*:    e4f7e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, #28, mul vl\]
+.*:    e4f7e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, #28, mul vl\]
+.*:    e4f8e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, #-32, mul vl\]
+.*:    e4f8e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, #-32, mul vl\]
+.*:    e4f8e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, #-32, mul vl\]
+.*:    e4f9e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, #-28, mul vl\]
+.*:    e4f9e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, #-28, mul vl\]
+.*:    e4f9e000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, #-28, mul vl\]
+.*:    e4ffe000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, #-4, mul vl\]
+.*:    e4ffe000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, #-4, mul vl\]
+.*:    e4ffe000        st4h    \{z0\.h-z3\.h\}, p0, \[x0, #-4, mul vl\]
+.*:    e5606000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5606000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5606000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5606001        st4w    \{z1\.s-z4\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5606001        st4w    \{z1\.s-z4\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5606001        st4w    \{z1\.s-z4\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e560601f        st4w    \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e560601f        st4w    \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5606800        st4w    \{z0\.s-z3\.s\}, p2, \[x0, x0, lsl #2\]
+.*:    e5606800        st4w    \{z0\.s-z3\.s\}, p2, \[x0, x0, lsl #2\]
+.*:    e5606800        st4w    \{z0\.s-z3\.s\}, p2, \[x0, x0, lsl #2\]
+.*:    e5607c00        st4w    \{z0\.s-z3\.s\}, p7, \[x0, x0, lsl #2\]
+.*:    e5607c00        st4w    \{z0\.s-z3\.s\}, p7, \[x0, x0, lsl #2\]
+.*:    e5607c00        st4w    \{z0\.s-z3\.s\}, p7, \[x0, x0, lsl #2\]
+.*:    e5606060        st4w    \{z0\.s-z3\.s\}, p0, \[x3, x0, lsl #2\]
+.*:    e5606060        st4w    \{z0\.s-z3\.s\}, p0, \[x3, x0, lsl #2\]
+.*:    e5606060        st4w    \{z0\.s-z3\.s\}, p0, \[x3, x0, lsl #2\]
+.*:    e56063e0        st4w    \{z0\.s-z3\.s\}, p0, \[sp, x0, lsl #2\]
+.*:    e56063e0        st4w    \{z0\.s-z3\.s\}, p0, \[sp, x0, lsl #2\]
+.*:    e56063e0        st4w    \{z0\.s-z3\.s\}, p0, \[sp, x0, lsl #2\]
+.*:    e5646000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, x4, lsl #2\]
+.*:    e5646000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, x4, lsl #2\]
+.*:    e5646000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, x4, lsl #2\]
+.*:    e57e6000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, x30, lsl #2\]
+.*:    e57e6000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, x30, lsl #2\]
+.*:    e57e6000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, x30, lsl #2\]
 .*:    e570e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0\]
 .*:    e570e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0\]
 .*:    e570e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0\]
@@ -31560,48 +31560,48 @@ Disassembly of section .*:
 .*:    e570e3e0        st4w    \{z0\.s-z3\.s\}, p0, \[sp\]
 .*:    e570e3e0        st4w    \{z0\.s-z3\.s\}, p0, \[sp\]
 .*:    e570e3e0        st4w    \{z0\.s-z3\.s\}, p0, \[sp\]
-.*:    e577e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,#28,mul vl\]
-.*:    e577e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,#28,mul vl\]
-.*:    e577e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,#28,mul vl\]
-.*:    e578e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,#-32,mul vl\]
-.*:    e578e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,#-32,mul vl\]
-.*:    e578e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,#-32,mul vl\]
-.*:    e579e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,#-28,mul vl\]
-.*:    e579e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,#-28,mul vl\]
-.*:    e579e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,#-28,mul vl\]
-.*:    e57fe000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,#-4,mul vl\]
-.*:    e57fe000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,#-4,mul vl\]
-.*:    e57fe000        st4w    \{z0\.s-z3\.s\}, p0, \[x0,#-4,mul vl\]
-.*:    e4006000        stnt1b  \{z0\.b\}, p0, \[x0,x0\]
-.*:    e4006000        stnt1b  \{z0\.b\}, p0, \[x0,x0\]
-.*:    e4006000        stnt1b  \{z0\.b\}, p0, \[x0,x0\]
-.*:    e4006000        stnt1b  \{z0\.b\}, p0, \[x0,x0\]
-.*:    e4006001        stnt1b  \{z1\.b\}, p0, \[x0,x0\]
-.*:    e4006001        stnt1b  \{z1\.b\}, p0, \[x0,x0\]
-.*:    e4006001        stnt1b  \{z1\.b\}, p0, \[x0,x0\]
-.*:    e4006001        stnt1b  \{z1\.b\}, p0, \[x0,x0\]
-.*:    e400601f        stnt1b  \{z31\.b\}, p0, \[x0,x0\]
-.*:    e400601f        stnt1b  \{z31\.b\}, p0, \[x0,x0\]
-.*:    e400601f        stnt1b  \{z31\.b\}, p0, \[x0,x0\]
-.*:    e400601f        stnt1b  \{z31\.b\}, p0, \[x0,x0\]
-.*:    e4006800        stnt1b  \{z0\.b\}, p2, \[x0,x0\]
-.*:    e4006800        stnt1b  \{z0\.b\}, p2, \[x0,x0\]
-.*:    e4006800        stnt1b  \{z0\.b\}, p2, \[x0,x0\]
-.*:    e4007c00        stnt1b  \{z0\.b\}, p7, \[x0,x0\]
-.*:    e4007c00        stnt1b  \{z0\.b\}, p7, \[x0,x0\]
-.*:    e4007c00        stnt1b  \{z0\.b\}, p7, \[x0,x0\]
-.*:    e4006060        stnt1b  \{z0\.b\}, p0, \[x3,x0\]
-.*:    e4006060        stnt1b  \{z0\.b\}, p0, \[x3,x0\]
-.*:    e4006060        stnt1b  \{z0\.b\}, p0, \[x3,x0\]
-.*:    e40063e0        stnt1b  \{z0\.b\}, p0, \[sp,x0\]
-.*:    e40063e0        stnt1b  \{z0\.b\}, p0, \[sp,x0\]
-.*:    e40063e0        stnt1b  \{z0\.b\}, p0, \[sp,x0\]
-.*:    e4046000        stnt1b  \{z0\.b\}, p0, \[x0,x4\]
-.*:    e4046000        stnt1b  \{z0\.b\}, p0, \[x0,x4\]
-.*:    e4046000        stnt1b  \{z0\.b\}, p0, \[x0,x4\]
-.*:    e41e6000        stnt1b  \{z0\.b\}, p0, \[x0,x30\]
-.*:    e41e6000        stnt1b  \{z0\.b\}, p0, \[x0,x30\]
-.*:    e41e6000        stnt1b  \{z0\.b\}, p0, \[x0,x30\]
+.*:    e577e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, #28, mul vl\]
+.*:    e577e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, #28, mul vl\]
+.*:    e577e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, #28, mul vl\]
+.*:    e578e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, #-32, mul vl\]
+.*:    e578e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, #-32, mul vl\]
+.*:    e578e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, #-32, mul vl\]
+.*:    e579e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, #-28, mul vl\]
+.*:    e579e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, #-28, mul vl\]
+.*:    e579e000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, #-28, mul vl\]
+.*:    e57fe000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, #-4, mul vl\]
+.*:    e57fe000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, #-4, mul vl\]
+.*:    e57fe000        st4w    \{z0\.s-z3\.s\}, p0, \[x0, #-4, mul vl\]
+.*:    e4006000        stnt1b  \{z0\.b\}, p0, \[x0, x0\]
+.*:    e4006000        stnt1b  \{z0\.b\}, p0, \[x0, x0\]
+.*:    e4006000        stnt1b  \{z0\.b\}, p0, \[x0, x0\]
+.*:    e4006000        stnt1b  \{z0\.b\}, p0, \[x0, x0\]
+.*:    e4006001        stnt1b  \{z1\.b\}, p0, \[x0, x0\]
+.*:    e4006001        stnt1b  \{z1\.b\}, p0, \[x0, x0\]
+.*:    e4006001        stnt1b  \{z1\.b\}, p0, \[x0, x0\]
+.*:    e4006001        stnt1b  \{z1\.b\}, p0, \[x0, x0\]
+.*:    e400601f        stnt1b  \{z31\.b\}, p0, \[x0, x0\]
+.*:    e400601f        stnt1b  \{z31\.b\}, p0, \[x0, x0\]
+.*:    e400601f        stnt1b  \{z31\.b\}, p0, \[x0, x0\]
+.*:    e400601f        stnt1b  \{z31\.b\}, p0, \[x0, x0\]
+.*:    e4006800        stnt1b  \{z0\.b\}, p2, \[x0, x0\]
+.*:    e4006800        stnt1b  \{z0\.b\}, p2, \[x0, x0\]
+.*:    e4006800        stnt1b  \{z0\.b\}, p2, \[x0, x0\]
+.*:    e4007c00        stnt1b  \{z0\.b\}, p7, \[x0, x0\]
+.*:    e4007c00        stnt1b  \{z0\.b\}, p7, \[x0, x0\]
+.*:    e4007c00        stnt1b  \{z0\.b\}, p7, \[x0, x0\]
+.*:    e4006060        stnt1b  \{z0\.b\}, p0, \[x3, x0\]
+.*:    e4006060        stnt1b  \{z0\.b\}, p0, \[x3, x0\]
+.*:    e4006060        stnt1b  \{z0\.b\}, p0, \[x3, x0\]
+.*:    e40063e0        stnt1b  \{z0\.b\}, p0, \[sp, x0\]
+.*:    e40063e0        stnt1b  \{z0\.b\}, p0, \[sp, x0\]
+.*:    e40063e0        stnt1b  \{z0\.b\}, p0, \[sp, x0\]
+.*:    e4046000        stnt1b  \{z0\.b\}, p0, \[x0, x4\]
+.*:    e4046000        stnt1b  \{z0\.b\}, p0, \[x0, x4\]
+.*:    e4046000        stnt1b  \{z0\.b\}, p0, \[x0, x4\]
+.*:    e41e6000        stnt1b  \{z0\.b\}, p0, \[x0, x30\]
+.*:    e41e6000        stnt1b  \{z0\.b\}, p0, \[x0, x30\]
+.*:    e41e6000        stnt1b  \{z0\.b\}, p0, \[x0, x30\]
 .*:    e410e000        stnt1b  \{z0\.b\}, p0, \[x0\]
 .*:    e410e000        stnt1b  \{z0\.b\}, p0, \[x0\]
 .*:    e410e000        stnt1b  \{z0\.b\}, p0, \[x0\]
@@ -31633,35 +31633,35 @@ Disassembly of section .*:
 .*:    e410e3e0        stnt1b  \{z0\.b\}, p0, \[sp\]
 .*:    e410e3e0        stnt1b  \{z0\.b\}, p0, \[sp\]
 .*:    e410e3e0        stnt1b  \{z0\.b\}, p0, \[sp\]
-.*:    e417e000        stnt1b  \{z0\.b\}, p0, \[x0,#7,mul vl\]
-.*:    e417e000        stnt1b  \{z0\.b\}, p0, \[x0,#7,mul vl\]
-.*:    e418e000        stnt1b  \{z0\.b\}, p0, \[x0,#-8,mul vl\]
-.*:    e418e000        stnt1b  \{z0\.b\}, p0, \[x0,#-8,mul vl\]
-.*:    e419e000        stnt1b  \{z0\.b\}, p0, \[x0,#-7,mul vl\]
-.*:    e419e000        stnt1b  \{z0\.b\}, p0, \[x0,#-7,mul vl\]
-.*:    e41fe000        stnt1b  \{z0\.b\}, p0, \[x0,#-1,mul vl\]
-.*:    e41fe000        stnt1b  \{z0\.b\}, p0, \[x0,#-1,mul vl\]
-.*:    e5806000        stnt1d  \{z0\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5806000        stnt1d  \{z0\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5806000        stnt1d  \{z0\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5806001        stnt1d  \{z1\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5806001        stnt1d  \{z1\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5806001        stnt1d  \{z1\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e580601f        stnt1d  \{z31\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e580601f        stnt1d  \{z31\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e580601f        stnt1d  \{z31\.d\}, p0, \[x0,x0,lsl #3\]
-.*:    e5806800        stnt1d  \{z0\.d\}, p2, \[x0,x0,lsl #3\]
-.*:    e5806800        stnt1d  \{z0\.d\}, p2, \[x0,x0,lsl #3\]
-.*:    e5807c00        stnt1d  \{z0\.d\}, p7, \[x0,x0,lsl #3\]
-.*:    e5807c00        stnt1d  \{z0\.d\}, p7, \[x0,x0,lsl #3\]
-.*:    e5806060        stnt1d  \{z0\.d\}, p0, \[x3,x0,lsl #3\]
-.*:    e5806060        stnt1d  \{z0\.d\}, p0, \[x3,x0,lsl #3\]
-.*:    e58063e0        stnt1d  \{z0\.d\}, p0, \[sp,x0,lsl #3\]
-.*:    e58063e0        stnt1d  \{z0\.d\}, p0, \[sp,x0,lsl #3\]
-.*:    e5846000        stnt1d  \{z0\.d\}, p0, \[x0,x4,lsl #3\]
-.*:    e5846000        stnt1d  \{z0\.d\}, p0, \[x0,x4,lsl #3\]
-.*:    e59e6000        stnt1d  \{z0\.d\}, p0, \[x0,x30,lsl #3\]
-.*:    e59e6000        stnt1d  \{z0\.d\}, p0, \[x0,x30,lsl #3\]
+.*:    e417e000        stnt1b  \{z0\.b\}, p0, \[x0, #7, mul vl\]
+.*:    e417e000        stnt1b  \{z0\.b\}, p0, \[x0, #7, mul vl\]
+.*:    e418e000        stnt1b  \{z0\.b\}, p0, \[x0, #-8, mul vl\]
+.*:    e418e000        stnt1b  \{z0\.b\}, p0, \[x0, #-8, mul vl\]
+.*:    e419e000        stnt1b  \{z0\.b\}, p0, \[x0, #-7, mul vl\]
+.*:    e419e000        stnt1b  \{z0\.b\}, p0, \[x0, #-7, mul vl\]
+.*:    e41fe000        stnt1b  \{z0\.b\}, p0, \[x0, #-1, mul vl\]
+.*:    e41fe000        stnt1b  \{z0\.b\}, p0, \[x0, #-1, mul vl\]
+.*:    e5806000        stnt1d  \{z0\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5806000        stnt1d  \{z0\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5806000        stnt1d  \{z0\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5806001        stnt1d  \{z1\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5806001        stnt1d  \{z1\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5806001        stnt1d  \{z1\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e580601f        stnt1d  \{z31\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e580601f        stnt1d  \{z31\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e580601f        stnt1d  \{z31\.d\}, p0, \[x0, x0, lsl #3\]
+.*:    e5806800        stnt1d  \{z0\.d\}, p2, \[x0, x0, lsl #3\]
+.*:    e5806800        stnt1d  \{z0\.d\}, p2, \[x0, x0, lsl #3\]
+.*:    e5807c00        stnt1d  \{z0\.d\}, p7, \[x0, x0, lsl #3\]
+.*:    e5807c00        stnt1d  \{z0\.d\}, p7, \[x0, x0, lsl #3\]
+.*:    e5806060        stnt1d  \{z0\.d\}, p0, \[x3, x0, lsl #3\]
+.*:    e5806060        stnt1d  \{z0\.d\}, p0, \[x3, x0, lsl #3\]
+.*:    e58063e0        stnt1d  \{z0\.d\}, p0, \[sp, x0, lsl #3\]
+.*:    e58063e0        stnt1d  \{z0\.d\}, p0, \[sp, x0, lsl #3\]
+.*:    e5846000        stnt1d  \{z0\.d\}, p0, \[x0, x4, lsl #3\]
+.*:    e5846000        stnt1d  \{z0\.d\}, p0, \[x0, x4, lsl #3\]
+.*:    e59e6000        stnt1d  \{z0\.d\}, p0, \[x0, x30, lsl #3\]
+.*:    e59e6000        stnt1d  \{z0\.d\}, p0, \[x0, x30, lsl #3\]
 .*:    e590e000        stnt1d  \{z0\.d\}, p0, \[x0\]
 .*:    e590e000        stnt1d  \{z0\.d\}, p0, \[x0\]
 .*:    e590e000        stnt1d  \{z0\.d\}, p0, \[x0\]
@@ -31693,35 +31693,35 @@ Disassembly of section .*:
 .*:    e590e3e0        stnt1d  \{z0\.d\}, p0, \[sp\]
 .*:    e590e3e0        stnt1d  \{z0\.d\}, p0, \[sp\]
 .*:    e590e3e0        stnt1d  \{z0\.d\}, p0, \[sp\]
-.*:    e597e000        stnt1d  \{z0\.d\}, p0, \[x0,#7,mul vl\]
-.*:    e597e000        stnt1d  \{z0\.d\}, p0, \[x0,#7,mul vl\]
-.*:    e598e000        stnt1d  \{z0\.d\}, p0, \[x0,#-8,mul vl\]
-.*:    e598e000        stnt1d  \{z0\.d\}, p0, \[x0,#-8,mul vl\]
-.*:    e599e000        stnt1d  \{z0\.d\}, p0, \[x0,#-7,mul vl\]
-.*:    e599e000        stnt1d  \{z0\.d\}, p0, \[x0,#-7,mul vl\]
-.*:    e59fe000        stnt1d  \{z0\.d\}, p0, \[x0,#-1,mul vl\]
-.*:    e59fe000        stnt1d  \{z0\.d\}, p0, \[x0,#-1,mul vl\]
-.*:    e4806000        stnt1h  \{z0\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4806000        stnt1h  \{z0\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4806000        stnt1h  \{z0\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4806001        stnt1h  \{z1\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4806001        stnt1h  \{z1\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4806001        stnt1h  \{z1\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e480601f        stnt1h  \{z31\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e480601f        stnt1h  \{z31\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e480601f        stnt1h  \{z31\.h\}, p0, \[x0,x0,lsl #1\]
-.*:    e4806800        stnt1h  \{z0\.h\}, p2, \[x0,x0,lsl #1\]
-.*:    e4806800        stnt1h  \{z0\.h\}, p2, \[x0,x0,lsl #1\]
-.*:    e4807c00        stnt1h  \{z0\.h\}, p7, \[x0,x0,lsl #1\]
-.*:    e4807c00        stnt1h  \{z0\.h\}, p7, \[x0,x0,lsl #1\]
-.*:    e4806060        stnt1h  \{z0\.h\}, p0, \[x3,x0,lsl #1\]
-.*:    e4806060        stnt1h  \{z0\.h\}, p0, \[x3,x0,lsl #1\]
-.*:    e48063e0        stnt1h  \{z0\.h\}, p0, \[sp,x0,lsl #1\]
-.*:    e48063e0        stnt1h  \{z0\.h\}, p0, \[sp,x0,lsl #1\]
-.*:    e4846000        stnt1h  \{z0\.h\}, p0, \[x0,x4,lsl #1\]
-.*:    e4846000        stnt1h  \{z0\.h\}, p0, \[x0,x4,lsl #1\]
-.*:    e49e6000        stnt1h  \{z0\.h\}, p0, \[x0,x30,lsl #1\]
-.*:    e49e6000        stnt1h  \{z0\.h\}, p0, \[x0,x30,lsl #1\]
+.*:    e597e000        stnt1d  \{z0\.d\}, p0, \[x0, #7, mul vl\]
+.*:    e597e000        stnt1d  \{z0\.d\}, p0, \[x0, #7, mul vl\]
+.*:    e598e000        stnt1d  \{z0\.d\}, p0, \[x0, #-8, mul vl\]
+.*:    e598e000        stnt1d  \{z0\.d\}, p0, \[x0, #-8, mul vl\]
+.*:    e599e000        stnt1d  \{z0\.d\}, p0, \[x0, #-7, mul vl\]
+.*:    e599e000        stnt1d  \{z0\.d\}, p0, \[x0, #-7, mul vl\]
+.*:    e59fe000        stnt1d  \{z0\.d\}, p0, \[x0, #-1, mul vl\]
+.*:    e59fe000        stnt1d  \{z0\.d\}, p0, \[x0, #-1, mul vl\]
+.*:    e4806000        stnt1h  \{z0\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4806000        stnt1h  \{z0\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4806000        stnt1h  \{z0\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4806001        stnt1h  \{z1\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4806001        stnt1h  \{z1\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4806001        stnt1h  \{z1\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e480601f        stnt1h  \{z31\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e480601f        stnt1h  \{z31\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e480601f        stnt1h  \{z31\.h\}, p0, \[x0, x0, lsl #1\]
+.*:    e4806800        stnt1h  \{z0\.h\}, p2, \[x0, x0, lsl #1\]
+.*:    e4806800        stnt1h  \{z0\.h\}, p2, \[x0, x0, lsl #1\]
+.*:    e4807c00        stnt1h  \{z0\.h\}, p7, \[x0, x0, lsl #1\]
+.*:    e4807c00        stnt1h  \{z0\.h\}, p7, \[x0, x0, lsl #1\]
+.*:    e4806060        stnt1h  \{z0\.h\}, p0, \[x3, x0, lsl #1\]
+.*:    e4806060        stnt1h  \{z0\.h\}, p0, \[x3, x0, lsl #1\]
+.*:    e48063e0        stnt1h  \{z0\.h\}, p0, \[sp, x0, lsl #1\]
+.*:    e48063e0        stnt1h  \{z0\.h\}, p0, \[sp, x0, lsl #1\]
+.*:    e4846000        stnt1h  \{z0\.h\}, p0, \[x0, x4, lsl #1\]
+.*:    e4846000        stnt1h  \{z0\.h\}, p0, \[x0, x4, lsl #1\]
+.*:    e49e6000        stnt1h  \{z0\.h\}, p0, \[x0, x30, lsl #1\]
+.*:    e49e6000        stnt1h  \{z0\.h\}, p0, \[x0, x30, lsl #1\]
 .*:    e490e000        stnt1h  \{z0\.h\}, p0, \[x0\]
 .*:    e490e000        stnt1h  \{z0\.h\}, p0, \[x0\]
 .*:    e490e000        stnt1h  \{z0\.h\}, p0, \[x0\]
@@ -31753,35 +31753,35 @@ Disassembly of section .*:
 .*:    e490e3e0        stnt1h  \{z0\.h\}, p0, \[sp\]
 .*:    e490e3e0        stnt1h  \{z0\.h\}, p0, \[sp\]
 .*:    e490e3e0        stnt1h  \{z0\.h\}, p0, \[sp\]
-.*:    e497e000        stnt1h  \{z0\.h\}, p0, \[x0,#7,mul vl\]
-.*:    e497e000        stnt1h  \{z0\.h\}, p0, \[x0,#7,mul vl\]
-.*:    e498e000        stnt1h  \{z0\.h\}, p0, \[x0,#-8,mul vl\]
-.*:    e498e000        stnt1h  \{z0\.h\}, p0, \[x0,#-8,mul vl\]
-.*:    e499e000        stnt1h  \{z0\.h\}, p0, \[x0,#-7,mul vl\]
-.*:    e499e000        stnt1h  \{z0\.h\}, p0, \[x0,#-7,mul vl\]
-.*:    e49fe000        stnt1h  \{z0\.h\}, p0, \[x0,#-1,mul vl\]
-.*:    e49fe000        stnt1h  \{z0\.h\}, p0, \[x0,#-1,mul vl\]
-.*:    e5006000        stnt1w  \{z0\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5006000        stnt1w  \{z0\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5006000        stnt1w  \{z0\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5006001        stnt1w  \{z1\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5006001        stnt1w  \{z1\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5006001        stnt1w  \{z1\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e500601f        stnt1w  \{z31\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e500601f        stnt1w  \{z31\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e500601f        stnt1w  \{z31\.s\}, p0, \[x0,x0,lsl #2\]
-.*:    e5006800        stnt1w  \{z0\.s\}, p2, \[x0,x0,lsl #2\]
-.*:    e5006800        stnt1w  \{z0\.s\}, p2, \[x0,x0,lsl #2\]
-.*:    e5007c00        stnt1w  \{z0\.s\}, p7, \[x0,x0,lsl #2\]
-.*:    e5007c00        stnt1w  \{z0\.s\}, p7, \[x0,x0,lsl #2\]
-.*:    e5006060        stnt1w  \{z0\.s\}, p0, \[x3,x0,lsl #2\]
-.*:    e5006060        stnt1w  \{z0\.s\}, p0, \[x3,x0,lsl #2\]
-.*:    e50063e0        stnt1w  \{z0\.s\}, p0, \[sp,x0,lsl #2\]
-.*:    e50063e0        stnt1w  \{z0\.s\}, p0, \[sp,x0,lsl #2\]
-.*:    e5046000        stnt1w  \{z0\.s\}, p0, \[x0,x4,lsl #2\]
-.*:    e5046000        stnt1w  \{z0\.s\}, p0, \[x0,x4,lsl #2\]
-.*:    e51e6000        stnt1w  \{z0\.s\}, p0, \[x0,x30,lsl #2\]
-.*:    e51e6000        stnt1w  \{z0\.s\}, p0, \[x0,x30,lsl #2\]
+.*:    e497e000        stnt1h  \{z0\.h\}, p0, \[x0, #7, mul vl\]
+.*:    e497e000        stnt1h  \{z0\.h\}, p0, \[x0, #7, mul vl\]
+.*:    e498e000        stnt1h  \{z0\.h\}, p0, \[x0, #-8, mul vl\]
+.*:    e498e000        stnt1h  \{z0\.h\}, p0, \[x0, #-8, mul vl\]
+.*:    e499e000        stnt1h  \{z0\.h\}, p0, \[x0, #-7, mul vl\]
+.*:    e499e000        stnt1h  \{z0\.h\}, p0, \[x0, #-7, mul vl\]
+.*:    e49fe000        stnt1h  \{z0\.h\}, p0, \[x0, #-1, mul vl\]
+.*:    e49fe000        stnt1h  \{z0\.h\}, p0, \[x0, #-1, mul vl\]
+.*:    e5006000        stnt1w  \{z0\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5006000        stnt1w  \{z0\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5006000        stnt1w  \{z0\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5006001        stnt1w  \{z1\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5006001        stnt1w  \{z1\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5006001        stnt1w  \{z1\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e500601f        stnt1w  \{z31\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e500601f        stnt1w  \{z31\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e500601f        stnt1w  \{z31\.s\}, p0, \[x0, x0, lsl #2\]
+.*:    e5006800        stnt1w  \{z0\.s\}, p2, \[x0, x0, lsl #2\]
+.*:    e5006800        stnt1w  \{z0\.s\}, p2, \[x0, x0, lsl #2\]
+.*:    e5007c00        stnt1w  \{z0\.s\}, p7, \[x0, x0, lsl #2\]
+.*:    e5007c00        stnt1w  \{z0\.s\}, p7, \[x0, x0, lsl #2\]
+.*:    e5006060        stnt1w  \{z0\.s\}, p0, \[x3, x0, lsl #2\]
+.*:    e5006060        stnt1w  \{z0\.s\}, p0, \[x3, x0, lsl #2\]
+.*:    e50063e0        stnt1w  \{z0\.s\}, p0, \[sp, x0, lsl #2\]
+.*:    e50063e0        stnt1w  \{z0\.s\}, p0, \[sp, x0, lsl #2\]
+.*:    e5046000        stnt1w  \{z0\.s\}, p0, \[x0, x4, lsl #2\]
+.*:    e5046000        stnt1w  \{z0\.s\}, p0, \[x0, x4, lsl #2\]
+.*:    e51e6000        stnt1w  \{z0\.s\}, p0, \[x0, x30, lsl #2\]
+.*:    e51e6000        stnt1w  \{z0\.s\}, p0, \[x0, x30, lsl #2\]
 .*:    e510e000        stnt1w  \{z0\.s\}, p0, \[x0\]
 .*:    e510e000        stnt1w  \{z0\.s\}, p0, \[x0\]
 .*:    e510e000        stnt1w  \{z0\.s\}, p0, \[x0\]
@@ -31813,14 +31813,14 @@ Disassembly of section .*:
 .*:    e510e3e0        stnt1w  \{z0\.s\}, p0, \[sp\]
 .*:    e510e3e0        stnt1w  \{z0\.s\}, p0, \[sp\]
 .*:    e510e3e0        stnt1w  \{z0\.s\}, p0, \[sp\]
-.*:    e517e000        stnt1w  \{z0\.s\}, p0, \[x0,#7,mul vl\]
-.*:    e517e000        stnt1w  \{z0\.s\}, p0, \[x0,#7,mul vl\]
-.*:    e518e000        stnt1w  \{z0\.s\}, p0, \[x0,#-8,mul vl\]
-.*:    e518e000        stnt1w  \{z0\.s\}, p0, \[x0,#-8,mul vl\]
-.*:    e519e000        stnt1w  \{z0\.s\}, p0, \[x0,#-7,mul vl\]
-.*:    e519e000        stnt1w  \{z0\.s\}, p0, \[x0,#-7,mul vl\]
-.*:    e51fe000        stnt1w  \{z0\.s\}, p0, \[x0,#-1,mul vl\]
-.*:    e51fe000        stnt1w  \{z0\.s\}, p0, \[x0,#-1,mul vl\]
+.*:    e517e000        stnt1w  \{z0\.s\}, p0, \[x0, #7, mul vl\]
+.*:    e517e000        stnt1w  \{z0\.s\}, p0, \[x0, #7, mul vl\]
+.*:    e518e000        stnt1w  \{z0\.s\}, p0, \[x0, #-8, mul vl\]
+.*:    e518e000        stnt1w  \{z0\.s\}, p0, \[x0, #-8, mul vl\]
+.*:    e519e000        stnt1w  \{z0\.s\}, p0, \[x0, #-7, mul vl\]
+.*:    e519e000        stnt1w  \{z0\.s\}, p0, \[x0, #-7, mul vl\]
+.*:    e51fe000        stnt1w  \{z0\.s\}, p0, \[x0, #-1, mul vl\]
+.*:    e51fe000        stnt1w  \{z0\.s\}, p0, \[x0, #-1, mul vl\]
 .*:    e5800000        str     p0, \[x0\]
 .*:    e5800000        str     p0, \[x0\]
 .*:    e5800000        str     p0, \[x0\]
@@ -31841,14 +31841,14 @@ Disassembly of section .*:
 .*:    e58003e0        str     p0, \[sp\]
 .*:    e58003e0        str     p0, \[sp\]
 .*:    e58003e0        str     p0, \[sp\]
-.*:    e59f1c00        str     p0, \[x0,#255,mul vl\]
-.*:    e59f1c00        str     p0, \[x0,#255,mul vl\]
-.*:    e5a00000        str     p0, \[x0,#-256,mul vl\]
-.*:    e5a00000        str     p0, \[x0,#-256,mul vl\]
-.*:    e5a00400        str     p0, \[x0,#-255,mul vl\]
-.*:    e5a00400        str     p0, \[x0,#-255,mul vl\]
-.*:    e5bf1c00        str     p0, \[x0,#-1,mul vl\]
-.*:    e5bf1c00        str     p0, \[x0,#-1,mul vl\]
+.*:    e59f1c00        str     p0, \[x0, #255, mul vl\]
+.*:    e59f1c00        str     p0, \[x0, #255, mul vl\]
+.*:    e5a00000        str     p0, \[x0, #-256, mul vl\]
+.*:    e5a00000        str     p0, \[x0, #-256, mul vl\]
+.*:    e5a00400        str     p0, \[x0, #-255, mul vl\]
+.*:    e5a00400        str     p0, \[x0, #-255, mul vl\]
+.*:    e5bf1c00        str     p0, \[x0, #-1, mul vl\]
+.*:    e5bf1c00        str     p0, \[x0, #-1, mul vl\]
 .*:    e5804000        str     z0, \[x0\]
 .*:    e5804000        str     z0, \[x0\]
 .*:    e5804000        str     z0, \[x0\]
@@ -31869,14 +31869,14 @@ Disassembly of section .*:
 .*:    e58043e0        str     z0, \[sp\]
 .*:    e58043e0        str     z0, \[sp\]
 .*:    e58043e0        str     z0, \[sp\]
-.*:    e59f5c00        str     z0, \[x0,#255,mul vl\]
-.*:    e59f5c00        str     z0, \[x0,#255,mul vl\]
-.*:    e5a04000        str     z0, \[x0,#-256,mul vl\]
-.*:    e5a04000        str     z0, \[x0,#-256,mul vl\]
-.*:    e5a04400        str     z0, \[x0,#-255,mul vl\]
-.*:    e5a04400        str     z0, \[x0,#-255,mul vl\]
-.*:    e5bf5c00        str     z0, \[x0,#-1,mul vl\]
-.*:    e5bf5c00        str     z0, \[x0,#-1,mul vl\]
+.*:    e59f5c00        str     z0, \[x0, #255, mul vl\]
+.*:    e59f5c00        str     z0, \[x0, #255, mul vl\]
+.*:    e5a04000        str     z0, \[x0, #-256, mul vl\]
+.*:    e5a04000        str     z0, \[x0, #-256, mul vl\]
+.*:    e5a04400        str     z0, \[x0, #-255, mul vl\]
+.*:    e5a04400        str     z0, \[x0, #-255, mul vl\]
+.*:    e5bf5c00        str     z0, \[x0, #-1, mul vl\]
+.*:    e5bf5c00        str     z0, \[x0, #-1, mul vl\]
 .*:    04200400        sub     z0\.b, z0\.b, z0\.b
 .*:    04200400        sub     z0\.b, z0\.b, z0\.b
 .*:    04200401        sub     z1\.b, z0\.b, z0\.b