#name: Valid v8-a+fp
+#source: armv8-ar+fp.s
+#as: -march=armv8-a
#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-pe *-*-wince
.*: +file format .*arm.*
0[0-9a-f]+ <[^>]+> fefd0ae0 vcvtn.s32.f32 s1, s1
0[0-9a-f]+ <[^>]+> febefa4f vcvtp.u32.f32 s30, s30
0[0-9a-f]+ <[^>]+> fefffa6f vcvtm.u32.f32 s31, s31
-0[0-9a-f]+ <[^>]+> febc0b40 vcvta.u32.f64 s0, d0
-0[0-9a-f]+ <[^>]+> fefd0b60 vcvtn.u32.f64 s1, d16
+0[0-9a-f]+ <[^>]+> febc0bc0 vcvta.s32.f64 s0, d0
+0[0-9a-f]+ <[^>]+> fefd0be0 vcvtn.s32.f64 s1, d16
0[0-9a-f]+ <[^>]+> febefb4f vcvtp.u32.f64 s30, d15
0[0-9a-f]+ <[^>]+> fefffb6f vcvtm.u32.f64 s31, d31
0[0-9a-f]+ <[^>]+> eeb60ac0 vrintz.f32 s0, s0
0[0-9a-f]+ <[^>]+> fefd 0ae0 vcvtn.s32.f32 s1, s1
0[0-9a-f]+ <[^>]+> febe fa4f vcvtp.u32.f32 s30, s30
0[0-9a-f]+ <[^>]+> feff fa6f vcvtm.u32.f32 s31, s31
-0[0-9a-f]+ <[^>]+> febc 0b40 vcvta.u32.f64 s0, d0
-0[0-9a-f]+ <[^>]+> fefd 0b60 vcvtn.u32.f64 s1, d16
+0[0-9a-f]+ <[^>]+> febc 0bc0 vcvta.s32.f64 s0, d0
+0[0-9a-f]+ <[^>]+> fefd 0be0 vcvtn.s32.f64 s1, d16
0[0-9a-f]+ <[^>]+> febe fb4f vcvtp.u32.f64 s30, d15
0[0-9a-f]+ <[^>]+> feff fb6f vcvtm.u32.f64 s31, d31
0[0-9a-f]+ <[^>]+> eeb6 0ac0 vrintz.f32 s0, s0
0[0-9a-f]+ <[^>]+> eef2 0b60 vcvtb.f64.f16 d16, s1
0[0-9a-f]+ <[^>]+> eeb2 fbcf vcvtt.f64.f16 d15, s30
0[0-9a-f]+ <[^>]+> eef2 fb6f vcvtb.f64.f16 d31, s31
+0[0-9a-f]+ <[^>]+> eef5 9a10 vmrs r9, mvfr2
+0[0-9a-f]+ <[^>]+> eee5 7a10 vmsr mvfr2, r7
+0[0-9a-f]+ <[^>]+> eef5 4a10 vmrs r4, mvfr2
+0[0-9a-f]+ <[^>]+> eee5 5a10 vmsr mvfr2, r5
\ No newline at end of file