cmpeq fp, fp
.text
- .global machl1
-machl1:
- machl1 fp, fp
+ .global maclh1
+maclh1:
+ maclh1 fp, fp
.text
.global macsl0
mullo fp, fp, a0
.text
- .global mulwhi
-mulwhi:
- mulwhi fp, fp, a1
-
- .text
- .global mulwlo
-mulwlo:
- mulwlo fp, fp, a0
+ .global divh
+divh:
+ divh fp, fp
.text
.global machi
maclo:
maclo fp, fp, a0
- .text
- .global macwhi
-macwhi:
- macwhi fp, fp, a1
-
- .text
- .global macwlo
-macwlo:
- macwlo fp, fp, a0
-
.text
.global mvfachi
mvfachi:
.text
.global mvfaclo
mvfaclo:
- mvfaclo fp, a0
+ mvfaclo fp, a1
.text
.global mvtachi
rac:
rac a1
+ .text
+ .global rac_ds
+rac_ds:
+ rac a1, a0
+
+ .text
+ .global rac_dsi
+rac_dsi:
+ rac a0, a1, #1
+
.text
.global rach
rach:
rach a1
+ .text
+ .global rach_ds
+rach_ds:
+ rach a0, a1
+
+ .text
+ .global rach_dsi
+rach_dsi:
+ rach a1, a0, #2
+
# Test explicitly parallel and implicitly parallel instructions
# Including apparent instruction sequence reordering.
.text
.global bc__add
bc__add:
- bc branchpoint || add fp, fp
- bc branchpoint
+ bc bcl || add fp, fp
+# Use bc.s here as bc is relaxable and thus a nop will be emitted.
+ bc.s bcl
add fp, fp
.text
.global bcl__addi
bcl__addi:
- bcl branchpoint || addi fp, #77
+ bcl bcl || addi fp, #77
addi fp, #77
- bcl branchpoint
+# Use bcl.s here as bcl is relaxable and thus the parallelization won't happen.
+ bcl.s bcl
.text
.global bl__addv
bl__addv:
- bl branchpoint || addv fp, fp
+ bl bcl || addv fp, fp
addv fp, fp
- bl branchpoint
+# Use bl.s here as bl is relaxable and thus the parallelization won't happen.
+ bl.s bcl
.text
.global bnc__addx
bnc__addx:
- bnc branchpoint || addx fp, fp
- bnc branchpoint
+ bnc bcl || addx fp, fp
+# Use bnc.s here as bnc is relaxable and thus the parallelization attempt won't
+# happen. Things still won't be parallelized, but we want this test to try.
+ bnc.s bcl
addx fp, fp
.text
.global bncl__and
bncl__and:
- bncl branchpoint || and fp, fp
- bncl branchpoint
+ bncl bcl || and fp, fp
and fp, fp
+ bncl.s bcl
.text
.global bra__cmp
bra__cmp:
- bra branchpoint || cmp fp, fp
+ bra bcl || cmp fp, fp
cmp fp, fp
- bra branchpoint
+# Use bra.s here as bra is relaxable and thus the parallelization won't happen.
+ bra.s bcl
.text
.global jl__cmpeq
.text
.global mvtc__subv
mvtc__subv:
- mvtc fp, cr0 || subv r2, fp
- mvtc fp, cr0
+ mvtc fp, cr2 || subv r2, fp
+ mvtc fp, cr2
subv r2, fp
.text
.global rte__subx
rte__subx:
- rte || subx r2, fp
+ rte || sub r2, fp
rte
subx r2, fp
machi r2, fp
.text
- .global sra__machl1
-sra__machl1:
- sra fp, fp || machl1 r2, fp
+ .global sra__maclh1
+sra__maclh1:
+ sra fp, fp || maclh1 r2, fp
sra fp, fp
- machl1 r2, fp
+ maclh1 r2, fp
.text
.global srai__maclo
.text
.global trap__mulwhi
trap__mulwhi:
- trap 2 || mulwhi r2, fp
- trap 2
+ trap #2 || mulwhi r2, fp
+ trap #2
mulwhi r2, fp
.text
.text
.global cmpu__rach
cmpu__rach:
- cmpu fp, fp || rach a0
+ cmpu fp, fp || rach a0, a1
cmpu fp, fp
- rach a0
+ rach a1, a1, #1
.text
.global cmpz__sadd
snc
neg fp, r2
+# Test automatic and explicit parallelisation of instructions
+ .text
+ .global nop__sadd
+nop__sadd:
+ nop
+ sadd
+
+ .text
+ .global sadd__nop
+sadd__nop:
+ sadd
+ nop
+
+ .text
+ .global sadd__nop_reverse
+sadd__nop_reverse:
+ sadd || nop
+
+ .text
+ .global add__not
+add__not:
+ add r0, r1
+ not r3, r5
+
+ .text
+ .global add__not__dest_clash
+add__not_dest_clash:
+ add r3, r4
+ not r3, r5
+
+ .text
+ .global add__not__src_clash
+add__not__src_clash:
+ add r3, r4
+ not r5, r3
+
+ .text
+ .global add__not__no_clash
+add__not__no_clash:
+ add r3, r4
+ not r4, r5
+
+ .text
+ .global mul__sra
+mul__sra:
+ mul r1, r2
+ sra r3, r4
+
+ .text
+ .global mul__sra__reverse_src_clash
+mul__sra__reverse_src_clash:
+ mul r1, r3
+ sra r3, r4
+ .text
+ .global bc__add_
+bc__add_:
+ bc.s label
+ add r1, r2
+
+ .text
+ .global add__bc
+add__bc:
+ add r3, r4
+ bc.s label
+
+ .text
+ .global bc__add__forced_parallel
+bc__add__forced_parallel:
+ bc label || add r5, r6
+
+ .text
+ .global add__bc__forced_parallel
+add__bc__forced_parallel:
+ add r7, r8 || bc label
+label:
+ nop
+
+; Additional testcases.
+; These insns were added to the chip later.
+
+ .text
+mulwhi:
+ mulwhi fp, fp, a0
+ mulwhi fp, fp, a1
+mulwlo:
+ mulwlo fp, fp, a0
+ mulwlo fp, fp, a1
+
+macwhi:
+ macwhi fp, fp, a0
+ macwhi fp, fp, a1
-
\ No newline at end of file
+macwlo:
+ macwlo fp, fp, a0
+ macwlo fp, fp, a1
projects / deliverable / binutils-gdb.git / blobdiff