2010-01-06 Quentin Neill <quentin.neill@amd.com>

[deliverable/binutils-gdb.git] / gas / testsuite / gas / m32r / m32rx.s

diff --git a/gas/testsuite/gas/m32r/m32rx.s b/gas/testsuite/gas/m32r/m32rx.s
index df632a229c42d8a15db390782fc63a166fe4aa54..e25ec77bc0a4211fb18f243a0292ca86ac24b4bf 100644 (file)
--- a/gas/testsuite/gas/m32r/m32rx.s
+++ b/gas/testsuite/gas/m32r/m32rx.s
@@ -22,9 +22,9 @@ cmpeq:
        cmpeq fp, fp
 
        .text
-       .global machl1
-machl1:
-       machl1 fp, fp
+       .global maclh1
+maclh1:
+       maclh1 fp, fp
        
        .text
        .global macsl0
@@ -63,14 +63,9 @@ mullo:
        mullo fp, fp, a0
        
        .text
-       .global mulwhi
-mulwhi:
-       mulwhi fp, fp, a1
-       
-       .text
-       .global mulwlo
-mulwlo:
-       mulwlo fp, fp, a0
+       .global divh
+divh:
+       divh fp, fp
        
        .text
        .global machi
@@ -82,16 +77,6 @@ machi:
 maclo:
        maclo fp, fp, a0
        
-       .text
-       .global macwhi
-macwhi:
-       macwhi fp, fp, a1
-       
-       .text
-       .global macwlo
-macwlo:
-       macwlo fp, fp, a0
-       
        .text
        .global mvfachi
 mvfachi:
@@ -105,7 +90,7 @@ mvfacmi:
        .text
        .global mvfaclo
 mvfaclo:
-       mvfaclo fp, a0
+       mvfaclo fp, a1
        
        .text
        .global mvtachi
@@ -122,18 +107,39 @@ mvtaclo:
 rac:
        rac a1
        
+       .text
+       .global rac_ds
+rac_ds:
+       rac a1, a0
+       
+       .text
+       .global rac_dsi
+rac_dsi:
+       rac a0, a1, #1
+       
        .text
        .global rach
 rach:
        rach a1
        
+       .text
+       .global rach_ds
+rach_ds:
+       rach a0, a1
+       
+       .text
+       .global rach_dsi
+rach_dsi:
+       rach a1, a0, #2
+       
 # Test explicitly parallel and implicitly parallel instructions
 # Including apparent instruction sequence reordering.
        .text
        .global bc__add
 bc__add:
        bc bcl || add fp, fp
-       bc bcl
+# Use bc.s here as bc is relaxable and thus a nop will be emitted.
+       bc.s bcl
        add fp, fp
 
        .text
@@ -141,35 +147,40 @@ bc__add:
 bcl__addi:     
        bcl bcl || addi fp, #77
        addi fp, #77
-       bcl bcl
+# Use bcl.s here as bcl is relaxable and thus the parallelization won't happen.
+       bcl.s bcl
 
        .text
        .global bl__addv
 bl__addv:
        bl bcl || addv fp, fp
        addv fp, fp
-       bl bcl
+# Use bl.s here as bl is relaxable and thus the parallelization won't happen.
+       bl.s bcl
        
        .text
        .global bnc__addx
 bnc__addx:
        bnc bcl || addx fp, fp
-       bnc bcl
+# Use bnc.s here as bnc is relaxable and thus the parallelization attempt won't
+# happen.  Things still won't be parallelized, but we want this test to try.
+       bnc.s bcl
        addx fp, fp
 
        .text
        .global bncl__and
 bncl__and:
        bncl bcl || and fp, fp
-       bncl bcl
        and fp, fp
+       bncl.s bcl
 
        .text
        .global bra__cmp
 bra__cmp:
        bra bcl || cmp fp, fp
        cmp fp, fp
-       bra bcl
+# Use bra.s here as bra is relaxable and thus the parallelization won't happen.
+       bra.s bcl
        
        .text
        .global jl__cmpeq
@@ -244,14 +255,14 @@ mvfc__sub:
        .text
        .global mvtc__subv
 mvtc__subv:
-       mvtc fp, cr0 || subv r2, fp
-       mvtc fp, cr0
+       mvtc fp, cr2 || subv r2, fp
+       mvtc fp, cr2
        subv r2, fp
 
        .text
        .global rte__subx
 rte__subx:
-       rte || subx r2, fp
+       rte || sub r2, fp
        rte
        subx r2, fp
 
@@ -270,11 +281,11 @@ slli__machi:
        machi r2, fp
 
        .text
-       .global sra__machl1
-sra__machl1:
-       sra fp, fp || machl1 r2, fp
+       .global sra__maclh1
+sra__maclh1:
+       sra fp, fp || maclh1 r2, fp
        sra fp, fp
-       machl1 r2, fp
+       maclh1 r2, fp
 
        .text
        .global srai__maclo
@@ -398,9 +409,9 @@ cmpeq__rac:
        .text
        .global cmpu__rach
 cmpu__rach:
-       cmpu fp, fp || rach a0
+       cmpu fp, fp || rach a0, a1
        cmpu fp, fp
-       rach a0
+       rach a1, a1, #1
 
        .text
        .global cmpz__sadd
@@ -484,7 +495,6 @@ snc__neg:
        .text
        .global nop__sadd
 nop__sadd:
-label:         
        nop
        sadd
 
@@ -538,14 +548,14 @@ mul__sra__reverse_src_clash:
        .text
        .global bc__add_
 bc__add_:
-       bc label
+       bc.s label
        add r1, r2
 
        .text
        .global add__bc
 add__bc:
        add r3, r4
-       bc  label
+       bc.s  label
 
        .text
        .global bc__add__forced_parallel
@@ -556,3 +566,25 @@ bc__add__forced_parallel:
        .global add__bc__forced_parallel
 add__bc__forced_parallel:
        add r7, r8 || bc label
+label:
+       nop
+
+; Additional testcases.
+; These insns were added to the chip later.
+
+       .text
+mulwhi:
+       mulwhi fp, fp, a0
+       mulwhi fp, fp, a1
+       
+mulwlo:
+       mulwlo fp, fp, a0
+       mulwlo fp, fp, a1
+
+macwhi:
+       macwhi fp, fp, a0
+       macwhi fp, fp, a1
+
+macwlo:
+       macwlo fp, fp, a0
+       macwlo fp, fp, a1