MIPS/GAS: Use non-zero frag offset directly in PIC branch relaxation

[deliverable/binutils-gdb.git] / gas / testsuite / gas / mips / mips16-pcrel-reloc-7.d

diff --git a/gas/testsuite/gas/mips/mips16-pcrel-reloc-7.d b/gas/testsuite/gas/mips/mips16-pcrel-reloc-7.d
index 5f86e335092bd1078aff1878d699dc6080a7bc6e..ef266d23fa8c847920110c942b2d0b021c23ee51 100644 (file)
--- a/gas/testsuite/gas/mips/mips16-pcrel-reloc-7.d
+++ b/gas/testsuite/gas/mips/mips16-pcrel-reloc-7.d
@@ -1,3 +1,20 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
 #name: MIPS16 PC-relative relocation 7
-#as: -32 -mips3
-#error-output: mips16-pcrel-reloc-7.l
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+       \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00    li      v0,0
+[      ]*[0-9a-f]+: R_MIPS16_HI16      bar
+[0-9a-f]+ <[^>]*> f400 3240    sll     v0,16
+[0-9a-f]+ <[^>]*> f000 fd40    daddiu  v0,0
+[      ]*[0-9a-f]+: R_MIPS16_LO16      bar
+[0-9a-f]+ <[^>]*> f000 6a00    li      v0,0
+[      ]*[0-9a-f]+: R_MIPS16_HI16      bar
+[0-9a-f]+ <[^>]*> f400 3240    sll     v0,16
+[0-9a-f]+ <[^>]*> f000 3a40    ld      v0,0\(v0\)
+[      ]*[0-9a-f]+: R_MIPS16_LO16      bar
+[0-9a-f]+ <[^>]*> 6500         nop
+       \.\.\.