MIPS/GAS: Use non-zero frag offset directly in PIC branch relaxation

[deliverable/binutils-gdb.git] / gas / testsuite / gas / mips / mips32-sf32.l

diff --git a/gas/testsuite/gas/mips/mips32-sf32.l b/gas/testsuite/gas/mips/mips32-sf32.l
index b2980aed4ad1bce63df85af17e19b0b6bbafe5f1..d55f890c7f43f4e9eac16a67b4f1abe5780283d3 100644 (file)
--- a/gas/testsuite/gas/mips/mips32-sf32.l
+++ b/gas/testsuite/gas/mips/mips32-sf32.l
@@ -1,8 +1,8 @@
 .*: Assembler messages:
-.*:5: Error: Opcode not supported on this processor: .* \(.*\) `li.s \$f1,1.0'
-.*:6: Error: Opcode not supported on this processor: .* \(.*\) `li.s \$f3,1.9'
-.*:7: Error: Opcode not supported on this processor: .* \(.*\) `add.s \$f5,\$f1,\$f3'
-.*:8: Error: Opcode not supported on this processor: .* \(.*\) `cvt.d.s \$f8,\$f7'
-.*:9: Error: Opcode not supported on this processor: .* \(.*\) `cvt.d.w \$f8,\$f7'
-.*:10: Error: Opcode not supported on this processor: .* \(.*\) `cvt.s.d \$f7,\$f8'
-.*:11: Error: Opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f7,\$f8'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `li.s \$f1,1.0'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `li.s \$f3,1.9'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f5,\$f1,\$f3'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `cvt.d.s \$f8,\$f7'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `cvt.d.w \$f8,\$f7'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `cvt.s.d \$f7,\$f8'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f7,\$f8'