bfd/

[deliverable/binutils-gdb.git] / gas / testsuite / gas / mips / mips32.s

diff --git a/gas/testsuite/gas/mips/mips32.s b/gas/testsuite/gas/mips/mips32.s
index a4d2d0d1876b9883e5159eec82a2fa87f184ecc4..f5426580543931f8e61a89f0750907e5cdb1103a 100644 (file)
--- a/gas/testsuite/gas/mips/mips32.s
+++ b/gas/testsuite/gas/mips/mips32.s
@@ -3,7 +3,7 @@
         .set noreorder
       .set noat
 
-      .globl text_label .text
+      .text
 text_label:
 
       # unprivileged CPU instructions
@@ -49,6 +49,12 @@ text_label:
       cache   5, ($1)
       cache   5, 32767($2)
       cache   5, -32768($3)
+      .set at
+      cache   5, 32768($4)
+      cache   5, -32769($5)
+      cache   5, 32768
+      cache   5, -32769
+      .set noat
       eret
       tlbp
       tlbr
@@ -58,14 +64,30 @@ text_label:
       wait    0                       # disassembles without code
       wait    0x56789
 
-      # Instructions in previous ISAs or CPUs which are now slightly
-      # different.
+      # For a while break for the mips32 ISA interpreted a single argument
+      # as a 20-bit code, placing it in the opcode differently to
+      # traditional ISAs.  This turned out to cause problems, so it has
+      # been removed.  This test is to assure consistent interpretation.
       break
       break   0                       # disassembles without code
-      break   0x12345
+      break   0x345
+      break   0x48,0x345              # this still specifies a 20-bit code
+
+      # Instructions in previous ISAs or CPUs which are now slightly
+      # different.
       sdbbp
       sdbbp   0                       # disassembles without code
       sdbbp   0x56789
 
+      # Cop2 branches with cond code number, like bc1t/f
+      bc2f    $cc0,text_label
+      nop
+      bc2fl   $cc1,text_label
+      nop
+      bc2t    $cc6,text_label
+      nop
+      bc2tl   $cc7,text_label
+      nop
+
 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
       .space  8