0: 60 00 00 00 nop
4: 60 00 00 00 nop
8: 60 00 00 00 nop
- c: 48 00 00 04 b 10 <foo\+0x10>
- 10: 48 00 00 08 b 18 <foo\+0x18>
- 14: 48 00 00 00 b 14 <foo\+0x14>
+ c: 48 00 00 04 b 10 <foo\+0x10>
+ 10: 48 00 00 08 b 18 <foo\+0x18>
+ 14: 48 00 00 00 b 14 <foo\+0x14>
14: R_PPC_REL24 x
- 18: 48 00 00 04 b 1c <foo\+0x1c>
+ 18: 48 00 00 04 b 1c <foo\+0x1c>
18: R_PPC_REL24 \.data\+0x4
- 1c: 48 00 00 00 b 1c <foo\+0x1c>
+ 1c: 48 00 00 00 b 1c <foo\+0x1c>
1c: R_PPC_REL24 z
- 20: 48 00 00 14 b 34 <foo\+0x34>
+ 20: 48 00 00 14 b 34 <foo\+0x34>
20: R_PPC_REL24 z\+0x14
- 24: 48 00 00 04 b 28 <foo\+0x28>
- 28: 48 00 00 00 b 28 <foo\+0x28>
+ 24: 48 00 00 04 b 28 <foo\+0x28>
+ 28: 48 00 00 00 b 28 <foo\+0x28>
28: R_PPC_REL24 a
- 2c: 48 00 00 50 b 7c <apfour>
- 30: 48 00 00 04 b 34 <foo\+0x34>
+ 2c: 48 00 00 50 b 7c <apfour>
+ 30: 48 00 00 04 b 34 <foo\+0x34>
30: R_PPC_REL24 a\+0x4
- 34: 48 00 00 4c b 80 <apfour\+0x4>
- 38: 48 00 00 00 b 38 <foo\+0x38>
+ 34: 48 00 00 4c b 80 <apfour\+0x4>
+ 38: 48 00 00 00 b 38 <foo\+0x38>
38: R_PPC_LOCAL24PC a
- 3c: 48 00 00 40 b 7c <apfour>
+ 3c: 48 00 00 40 b 7c <apfour>
40: 00 00 00 40 \.long 0x40
40: R_PPC_ADDR32 \.text\+0x40
58: R_PPC_ADDR32 x
5c: R_PPC_ADDR32 y
60: R_PPC_ADDR32 z
- 64: ff ff ff fc fnmsub f31,f31,f31,f31
+ 64: ff ff ff fc fnmsub f31,f31,f31,f31
64: R_PPC_ADDR32 x\+0xf+ffffffc
- 68: ff ff ff fc fnmsub f31,f31,f31,f31
+ 68: ff ff ff fc fnmsub f31,f31,f31,f31
68: R_PPC_ADDR32 y\+0xf+ffffffc
- 6c: ff ff ff fc fnmsub f31,f31,f31,f31
+ 6c: ff ff ff fc fnmsub f31,f31,f31,f31
6c: R_PPC_ADDR32 z\+0xf+ffffffc
70: 00 00 00 08 \.long 0x8
74: 00 00 00 08 \.long 0x8
\.\.\.
7c: R_PPC_ADDR32 b
80: R_PPC_ADDR32 apfour
- 84: ff ff ff fc fnmsub f31,f31,f31,f31
+ 84: ff ff ff fc fnmsub f31,f31,f31,f31
88: 00 00 00 02 \.long 0x2
88: R_PPC_ADDR32 apfour\+0x2
8c: 00 00 00 00 \.long 0x0
90: 60 00 00 00 nop
- 94: 40 a5 ff fc ble- cr1,90 <apfour\+0x14>
- 98: 41 a9 ff f8 bgt- cr2,90 <apfour\+0x14>
- 9c: 40 8d ff f4 ble\+ cr3,90 <apfour\+0x14>
- a0: 41 91 ff f0 bgt\+ cr4,90 <apfour\+0x14>
- a4: 40 95 00 10 ble- cr5,b4 <nop>
- a8: 41 99 00 0c bgt- cr6,b4 <nop>
- ac: 40 bd 00 08 ble\+ cr7,b4 <nop>
- b0: 41 a1 00 04 bgt\+ b4 <nop>
+ 94: 40 a5 ff fc ble- cr1,90 <apfour\+0x14>
+ 98: 41 a9 ff f8 bgt- cr2,90 <apfour\+0x14>
+ 9c: 40 8d ff f4 ble\+ cr3,90 <apfour\+0x14>
+ a0: 41 91 ff f0 bgt\+ cr4,90 <apfour\+0x14>
+ a4: 40 95 00 10 ble- cr5,b4 <nop>
+ a8: 41 99 00 0c bgt- cr6,b4 <nop>
+ ac: 40 bd 00 08 ble\+ cr7,b4 <nop>
+ b0: 41 a1 00 04 bgt\+ b4 <nop>
Disassembly of section \.data:
0+0000000 <x>: