and arm. */
gdb_static_assert (sizeof (regs) >= 18 * 4);
- tid = ptid_get_lwp (regcache_get_ptid (regcache));
+ tid = ptid_get_lwp (regcache->ptid ());
iovec.iov_base = ®s;
if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
/* Make sure REGS can hold all registers contents on both aarch64
and arm. */
gdb_static_assert (sizeof (regs) >= 18 * 4);
- tid = ptid_get_lwp (regcache_get_ptid (regcache));
+ tid = ptid_get_lwp (regcache->ptid ());
iovec.iov_base = ®s;
if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
int regno;
for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
- if (REG_VALID == regcache_register_status (regcache, regno))
+ if (REG_VALID == regcache->get_register_status (regno))
regcache_raw_collect (regcache, regno,
®s[regno - AARCH64_X0_REGNUM]);
}
and arm. */
gdb_static_assert (sizeof regs >= VFP_REGS_SIZE);
- tid = ptid_get_lwp (regcache_get_ptid (regcache));
+ tid = ptid_get_lwp (regcache->ptid ());
iovec.iov_base = ®s;
/* Make sure REGS can hold all VFP registers contents on both aarch64
and arm. */
gdb_static_assert (sizeof regs >= VFP_REGS_SIZE);
- tid = ptid_get_lwp (regcache_get_ptid (regcache));
+ tid = ptid_get_lwp (regcache->ptid ());
iovec.iov_base = ®s;
perror_with_name (_("Unable to fetch FP/SIMD registers."));
for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
- if (REG_VALID == regcache_register_status (regcache, regno))
+ if (REG_VALID == regcache->get_register_status (regno))
regcache_raw_collect (regcache, regno,
(char *) ®s.vregs[regno - AARCH64_V0_REGNUM]);
- if (REG_VALID == regcache_register_status (regcache, AARCH64_FPSR_REGNUM))
+ if (REG_VALID == regcache->get_register_status (AARCH64_FPSR_REGNUM))
regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM,
(char *) ®s.fpsr);
- if (REG_VALID == regcache_register_status (regcache, AARCH64_FPCR_REGNUM))
+ if (REG_VALID == regcache->get_register_status (AARCH64_FPCR_REGNUM))
regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM,
(char *) ®s.fpcr);
}