Add set/show debug dwarf-line.

[deliverable/binutils-gdb.git] / gdb / aarch64-tdep.c

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 85974972608176e942110ae0751c0febc9de160a..9650a7a0cd7cf64b95e0778b79f1ca883802b0e2 100644 (file)
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -3006,9 +3006,9 @@ aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
       /* Exception generation instructions. */
       if (insn_bits24_27 == 0x04)
        {
-         if (!bits (aarch64_insn_r->aarch64_insn, 2, 4) &&
-             !bits (aarch64_insn_r->aarch64_insn, 21, 23) &&
-             bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
+         if (!bits (aarch64_insn_r->aarch64_insn, 2, 4)
+             && !bits (aarch64_insn_r->aarch64_insn, 21, 23)
+             && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01)
            {
              ULONGEST svc_number;
 
@@ -3410,8 +3410,8 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
         }
     }
   /* Load/store register (register offset) instructions.  */
-  else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 &&
-          insn_bits10_11 == 0x02 && insn_bit21)
+  else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
+          && insn_bits10_11 == 0x02 && insn_bit21)
     {
       if (record_debug)
        {
@@ -3457,8 +3457,8 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
         }
     }
   /* Load/store register (immediate and unprivileged) instructions.  */
-  else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 &&
-          !insn_bit21)
+  else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03
+          && !insn_bit21)
     {
       if (record_debug)
        {
@@ -3592,7 +3592,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
              record_buf[0] = AARCH64_CPSR_REGNUM;
            }
          /* Floating point - integer conversions instructions.  */
-         if (insn_bits12_15 == 0x00)
+         else if (insn_bits12_15 == 0x00)
            {
              /* Convert float to integer instruction.  */
              if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode))
@@ -3621,8 +3621,14 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
                  else
                    record_buf[0] = reg_rd + AARCH64_V0_REGNUM;
                }
+             else
+               return AARCH64_RECORD_UNKNOWN;
             }
+         else
+           return AARCH64_RECORD_UNKNOWN;
         }
+      else
+       return AARCH64_RECORD_UNKNOWN;
     }
   else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e)
     {