#include "features/aarch64.c"
+#include "arch/aarch64-insn.h"
+
+#include "opcode/aarch64.h"
+
+#define submask(x) ((1L << ((x) + 1)) - 1)
+#define bit(obj,st) (((obj) >> (st)) & 1)
+#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
+
/* Pseudo register base numbers. */
#define AARCH64_Q0_REGNUM 0
#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + 32)
struct trad_frame_saved_reg *saved_regs;
};
-/* Toggle this file's internal debugging dump. */
-static int aarch64_debug;
-
static void
show_aarch64_debug (struct ui_file *file, int from_tty,
struct cmd_list_element *c, const char *value)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd, unsigned *rn,
- int32_t *imm)
+aarch64_decode_add_sub_imm (CORE_ADDR addr, uint32_t insn, unsigned *rd,
+ unsigned *rn, int32_t *imm)
{
if ((insn & 0x9f000000) == 0x91000000)
{
return 0;
}
-/* Decode an opcode if it represents an ADRP instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- RD receives the 'rd' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_adrp (CORE_ADDR addr, uint32_t insn, unsigned *rd)
-{
- if (decode_masked_match (insn, 0x9f000000, 0x90000000))
- {
- *rd = (insn >> 0) & 0x1f;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x adrp x%u, #?\n",
- core_addr_to_string_nz (addr), insn, *rd);
- }
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents an branch immediate or branch
- and link immediate instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- IS_BL receives the 'op' bit from the decoded instruction.
- OFFSET receives the immediate offset from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_b (CORE_ADDR addr, uint32_t insn, int *is_bl, int32_t *offset)
-{
- /* b 0001 01ii iiii iiii iiii iiii iiii iiii */
- /* bl 1001 01ii iiii iiii iiii iiii iiii iiii */
- if (decode_masked_match (insn, 0x7c000000, 0x14000000))
- {
- *is_bl = (insn >> 31) & 0x1;
- *offset = extract_signed_bitfield (insn, 26, 0) << 2;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_bl ? "bl" : "b",
- core_addr_to_string_nz (addr + *offset));
- }
-
- return 1;
- }
- return 0;
-}
-
-/* Decode an opcode if it represents a conditional branch instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- COND receives the branch condition field from the decoded
- instruction.
- OFFSET receives the immediate offset from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_bcond (CORE_ADDR addr, uint32_t insn, unsigned *cond, int32_t *offset)
-{
- /* b.cond 0101 0100 iiii iiii iiii iiii iii0 cccc */
- if (decode_masked_match (insn, 0xff000010, 0x54000000))
- {
- *cond = (insn >> 0) & 0xf;
- *offset = extract_signed_bitfield (insn, 19, 5) << 2;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x b<%u> 0x%s\n",
- core_addr_to_string_nz (addr), insn, *cond,
- core_addr_to_string_nz (addr + *offset));
- }
- return 1;
- }
- return 0;
-}
-
/* Decode an opcode if it represents a branch via register instruction.
ADDR specifies the address of the opcode.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_br (CORE_ADDR addr, uint32_t insn, int *is_blr, unsigned *rn)
+aarch64_decode_br (CORE_ADDR addr, uint32_t insn, int *is_blr,
+ unsigned *rn)
{
/* 8 4 0 6 2 8 4 0 */
/* blr 110101100011111100000000000rrrrr */
return 0;
}
-/* Decode an opcode if it represents a CBZ or CBNZ instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- IS64 receives the 'sf' field from the decoded instruction.
- IS_CBNZ receives the 'op' field from the decoded instruction.
- RN receives the 'rn' field from the decoded instruction.
- OFFSET receives the 'imm19' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_cb (CORE_ADDR addr, uint32_t insn, int *is64, int *is_cbnz,
- unsigned *rn, int32_t *offset)
-{
- /* cbz T011 010o iiii iiii iiii iiii iiir rrrr */
- /* cbnz T011 010o iiii iiii iiii iiii iiir rrrr */
- if (decode_masked_match (insn, 0x7e000000, 0x34000000))
- {
- *rn = (insn >> 0) & 0x1f;
- *is64 = (insn >> 31) & 0x1;
- *is_cbnz = (insn >> 24) & 0x1;
- *offset = extract_signed_bitfield (insn, 19, 5) << 2;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x %s 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_cbnz ? "cbnz" : "cbz",
- core_addr_to_string_nz (addr + *offset));
- }
- return 1;
- }
- return 0;
-}
-
/* Decode an opcode if it represents a ERET instruction.
ADDR specifies the address of the opcode.
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_eret (CORE_ADDR addr, uint32_t insn)
+aarch64_decode_eret (CORE_ADDR addr, uint32_t insn)
{
/* eret 1101 0110 1001 1111 0000 0011 1110 0000 */
if (insn == 0xd69f03e0)
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
+aarch64_decode_movz (CORE_ADDR addr, uint32_t insn, unsigned *rd)
{
if (decode_masked_match (insn, 0xff800000, 0x52800000))
{
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_orr_shifted_register_x (CORE_ADDR addr,
- uint32_t insn, unsigned *rd, unsigned *rn,
- unsigned *rm, int32_t *imm)
+aarch64_decode_orr_shifted_register_x (CORE_ADDR addr, uint32_t insn,
+ unsigned *rd, unsigned *rn,
+ unsigned *rm, int32_t *imm)
{
if (decode_masked_match (insn, 0xff200000, 0xaa000000))
{
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
+aarch64_decode_ret (CORE_ADDR addr, uint32_t insn, unsigned *rn)
{
if (decode_masked_match (insn, 0xfffffc1f, 0xd65f0000))
{
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_stp_offset (CORE_ADDR addr,
- uint32_t insn,
- unsigned *rt1, unsigned *rt2, unsigned *rn, int32_t *imm)
+aarch64_decode_stp_offset (CORE_ADDR addr, uint32_t insn, unsigned *rt1,
+ unsigned *rt2, unsigned *rn, int32_t *imm)
{
if (decode_masked_match (insn, 0xffc00000, 0xa9000000))
{
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_stp_offset_wb (CORE_ADDR addr,
- uint32_t insn,
- unsigned *rt1, unsigned *rt2, unsigned *rn,
- int32_t *imm)
+aarch64_decode_stp_offset_wb (CORE_ADDR addr, uint32_t insn, unsigned *rt1,
+ unsigned *rt2, unsigned *rn, int32_t *imm)
{
if (decode_masked_match (insn, 0xffc00000, 0xa9800000))
{
Return 1 if the opcodes matches and is decoded, otherwise 0. */
static int
-decode_stur (CORE_ADDR addr, uint32_t insn, int *is64, unsigned *rt,
- unsigned *rn, int32_t *imm)
+aarch64_decode_stur (CORE_ADDR addr, uint32_t insn, int *is64,
+ unsigned *rt, unsigned *rn, int32_t *imm)
{
if (decode_masked_match (insn, 0xbfe00c00, 0xb8000000))
{
return 0;
}
-/* Decode an opcode if it represents a TBZ or TBNZ instruction.
-
- ADDR specifies the address of the opcode.
- INSN specifies the opcode to test.
- IS_TBNZ receives the 'op' field from the decoded instruction.
- BIT receives the bit position field from the decoded instruction.
- RT receives 'rt' field from the decoded instruction.
- IMM receives 'imm' field from the decoded instruction.
-
- Return 1 if the opcodes matches and is decoded, otherwise 0. */
-
-static int
-decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz, unsigned *bit,
- unsigned *rt, int32_t *imm)
-{
- /* tbz b011 0110 bbbb biii iiii iiii iiir rrrr */
- /* tbnz B011 0111 bbbb biii iiii iiii iiir rrrr */
- if (decode_masked_match (insn, 0x7e000000, 0x36000000))
- {
- *rt = (insn >> 0) & 0x1f;
- *is_tbnz = (insn >> 24) & 0x1;
- *bit = ((insn >> (31 - 4)) & 0x20) | ((insn >> 19) & 0x1f);
- *imm = extract_signed_bitfield (insn, 14, 5) << 2;
-
- if (aarch64_debug)
- {
- debug_printf ("decode: 0x%s 0x%x %s x%u, #%u, 0x%s\n",
- core_addr_to_string_nz (addr), insn,
- *is_tbnz ? "tbnz" : "tbz", *rt, *bit,
- core_addr_to_string_nz (addr + *imm));
- }
- return 1;
- }
- return 0;
-}
-
/* Analyze a prologue, looking for a recognizable stack frame
and frame pointer. Scan until we encounter a store that could
clobber the stack frame unexpectedly, or an unknown instruction. */
int is_cbnz;
int is_tbnz;
unsigned bit;
+ int is_adrp;
int32_t offset;
insn = read_memory_unsigned_integer (start, 4, byte_order_for_code);
- if (decode_add_sub_imm (start, insn, &rd, &rn, &imm))
+ if (aarch64_decode_add_sub_imm (start, insn, &rd, &rn, &imm))
regs[rd] = pv_add_constant (regs[rn], imm);
- else if (decode_adrp (start, insn, &rd))
+ else if (aarch64_decode_adr (start, insn, &is_adrp, &rd, &offset)
+ && is_adrp)
regs[rd] = pv_unknown ();
- else if (decode_b (start, insn, &is_link, &offset))
+ else if (aarch64_decode_b (start, insn, &is_link, &offset))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_bcond (start, insn, &cond, &offset))
+ else if (aarch64_decode_bcond (start, insn, &cond, &offset))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_br (start, insn, &is_link, &rn))
+ else if (aarch64_decode_br (start, insn, &is_link, &rn))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_cb (start, insn, &is64, &is_cbnz, &rn, &offset))
+ else if (aarch64_decode_cb (start, insn, &is64, &is_cbnz, &rn,
+ &offset))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_eret (start, insn))
+ else if (aarch64_decode_eret (start, insn))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_movz (start, insn, &rd))
+ else if (aarch64_decode_movz (start, insn, &rd))
regs[rd] = pv_unknown ();
- else
- if (decode_orr_shifted_register_x (start, insn, &rd, &rn, &rm, &imm))
+ else if (aarch64_decode_orr_shifted_register_x (start, insn, &rd,
+ &rn, &rm, &imm))
{
if (imm == 0 && rn == 31)
regs[rd] = regs[rm];
break;
}
}
- else if (decode_ret (start, insn, &rn))
+ else if (aarch64_decode_ret (start, insn, &rn))
{
/* Stop analysis on branch. */
break;
}
- else if (decode_stur (start, insn, &is64, &rt, &rn, &offset))
+ else if (aarch64_decode_stur (start, insn, &is64, &rt, &rn, &offset))
{
pv_area_store (stack, pv_add_constant (regs[rn], offset),
is64 ? 8 : 4, regs[rt]);
}
- else if (decode_stp_offset (start, insn, &rt1, &rt2, &rn, &imm))
+ else if (aarch64_decode_stp_offset (start, insn, &rt1, &rt2, &rn,
+ &imm))
{
/* If recording this store would invalidate the store area
(perhaps because rn is not known) then we should abandon
pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
regs[rt2]);
}
- else if (decode_stp_offset_wb (start, insn, &rt1, &rt2, &rn, &imm))
+ else if (aarch64_decode_stp_offset_wb (start, insn, &rt1, &rt2, &rn,
+ &imm))
{
/* If recording this store would invalidate the store area
(perhaps because rn is not known) then we should abandon
regs[rt2]);
regs[rn] = pv_add_constant (regs[rn], imm);
}
- else if (decode_tb (start, insn, &is_tbnz, &bit, &rn, &offset))
+ else if (aarch64_decode_tb (start, insn, &is_tbnz, &bit, &rn,
+ &offset))
{
/* Stop analysis on branch. */
break;
struct aarch64_prologue_cache *cache;
if (*this_cache != NULL)
- return *this_cache;
+ return (struct aarch64_prologue_cache *) *this_cache;
cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
struct aarch64_prologue_cache *cache;
if (*this_cache != NULL)
- return *this_cache;
+ return (struct aarch64_prologue_cache *) *this_cache;
cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache);
cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
typedef struct
{
/* Value to pass on stack. */
- const void *data;
+ const gdb_byte *data;
/* Size in bytes of value to pass on stack. */
int len;
static struct value *
value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
{
- const int *reg_p = baton;
+ const int *reg_p = (const int *) baton;
return value_of_register (*reg_p, frame);
}
int insn_count;
int bc_insn_count = 0; /* Conditional branch instruction count. */
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
+ aarch64_inst inst;
+
+ if (aarch64_decode_insn (insn, &inst) != 0)
+ return 0;
/* Look for a Load Exclusive instruction which begins the sequence. */
- if (!decode_masked_match (insn, 0x3fc00000, 0x08400000))
+ if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
return 0;
for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
{
- int32_t offset;
- unsigned cond;
-
loc += insn_size;
insn = read_memory_unsigned_integer (loc, insn_size,
byte_order_for_code);
+ if (aarch64_decode_insn (insn, &inst) != 0)
+ return 0;
/* Check if the instruction is a conditional branch. */
- if (decode_bcond (loc, insn, &cond, &offset))
+ if (inst.opcode->iclass == condbranch)
{
+ gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
+
if (bc_insn_count >= 1)
return 0;
/* It is, so we'll try to set a breakpoint at the destination. */
- breaks[1] = loc + offset;
+ breaks[1] = loc + inst.operands[0].imm.value;
bc_insn_count++;
last_breakpoint++;
}
/* Look for the Store Exclusive which closes the atomic sequence. */
- if (decode_masked_match (insn, 0x3fc00000, 0x08000000))
+ if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0)
{
closing_insn = loc;
break;
return 1;
}
+struct displaced_step_closure
+{
+ /* It is true when condition instruction, such as B.CON, TBZ, etc,
+ is being displaced stepping. */
+ int cond;
+
+ /* PC adjustment offset after displaced stepping. */
+ int32_t pc_adjust;
+};
+
+/* Data when visiting instructions for displaced stepping. */
+
+struct aarch64_displaced_step_data
+{
+ struct aarch64_insn_data base;
+
+ /* The address where the instruction will be executed at. */
+ CORE_ADDR new_addr;
+ /* Buffer of instructions to be copied to NEW_ADDR to execute. */
+ uint32_t insn_buf[DISPLACED_MODIFIED_INSNS];
+ /* Number of instructions in INSN_BUF. */
+ unsigned insn_count;
+ /* Registers when doing displaced stepping. */
+ struct regcache *regs;
+
+ struct displaced_step_closure *dsc;
+};
+
+/* Implementation of aarch64_insn_visitor method "b". */
+
+static void
+aarch64_displaced_step_b (const int is_bl, const int32_t offset,
+ struct aarch64_insn_data *data)
+{
+ struct aarch64_displaced_step_data *dsd
+ = (struct aarch64_displaced_step_data *) data;
+ int32_t new_offset = data->insn_addr - dsd->new_addr + offset;
+
+ if (can_encode_int32 (new_offset, 28))
+ {
+ /* Emit B rather than BL, because executing BL on a new address
+ will get the wrong address into LR. In order to avoid this,
+ we emit B, and update LR if the instruction is BL. */
+ emit_b (dsd->insn_buf, 0, new_offset);
+ dsd->insn_count++;
+ }
+ else
+ {
+ /* Write NOP. */
+ emit_nop (dsd->insn_buf);
+ dsd->insn_count++;
+ dsd->dsc->pc_adjust = offset;
+ }
+
+ if (is_bl)
+ {
+ /* Update LR. */
+ regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM,
+ data->insn_addr + 4);
+ }
+}
+
+/* Implementation of aarch64_insn_visitor method "b_cond". */
+
+static void
+aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset,
+ struct aarch64_insn_data *data)
+{
+ struct aarch64_displaced_step_data *dsd
+ = (struct aarch64_displaced_step_data *) data;
+ int32_t new_offset = data->insn_addr - dsd->new_addr + offset;
+
+ /* GDB has to fix up PC after displaced step this instruction
+ differently according to the condition is true or false. Instead
+ of checking COND against conditional flags, we can use
+ the following instructions, and GDB can tell how to fix up PC
+ according to the PC value.
+
+ B.COND TAKEN ; If cond is true, then jump to TAKEN.
+ INSN1 ;
+ TAKEN:
+ INSN2
+ */
+
+ emit_bcond (dsd->insn_buf, cond, 8);
+ dsd->dsc->cond = 1;
+ dsd->dsc->pc_adjust = offset;
+ dsd->insn_count = 1;
+}
+
+/* Dynamically allocate a new register. If we know the register
+ statically, we should make it a global as above instead of using this
+ helper function. */
+
+static struct aarch64_register
+aarch64_register (unsigned num, int is64)
+{
+ return (struct aarch64_register) { num, is64 };
+}
+
+/* Implementation of aarch64_insn_visitor method "cb". */
+
+static void
+aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz,
+ const unsigned rn, int is64,
+ struct aarch64_insn_data *data)
+{
+ struct aarch64_displaced_step_data *dsd
+ = (struct aarch64_displaced_step_data *) data;
+ int32_t new_offset = data->insn_addr - dsd->new_addr + offset;
+
+ /* The offset is out of range for a compare and branch
+ instruction. We can use the following instructions instead:
+
+ CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
+ INSN1 ;
+ TAKEN:
+ INSN2
+ */
+ emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8);
+ dsd->insn_count = 1;
+ dsd->dsc->cond = 1;
+ dsd->dsc->pc_adjust = offset;
+}
+
+/* Implementation of aarch64_insn_visitor method "tb". */
+
+static void
+aarch64_displaced_step_tb (const int32_t offset, int is_tbnz,
+ const unsigned rt, unsigned bit,
+ struct aarch64_insn_data *data)
+{
+ struct aarch64_displaced_step_data *dsd
+ = (struct aarch64_displaced_step_data *) data;
+ int32_t new_offset = data->insn_addr - dsd->new_addr + offset;
+
+ /* The offset is out of range for a test bit and branch
+ instruction We can use the following instructions instead:
+
+ TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
+ INSN1 ;
+ TAKEN:
+ INSN2
+
+ */
+ emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8);
+ dsd->insn_count = 1;
+ dsd->dsc->cond = 1;
+ dsd->dsc->pc_adjust = offset;
+}
+
+/* Implementation of aarch64_insn_visitor method "adr". */
+
+static void
+aarch64_displaced_step_adr (const int32_t offset, const unsigned rd,
+ const int is_adrp, struct aarch64_insn_data *data)
+{
+ struct aarch64_displaced_step_data *dsd
+ = (struct aarch64_displaced_step_data *) data;
+ /* We know exactly the address the ADR{P,} instruction will compute.
+ We can just write it to the destination register. */
+ CORE_ADDR address = data->insn_addr + offset;
+
+ if (is_adrp)
+ {
+ /* Clear the lower 12 bits of the offset to get the 4K page. */
+ regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
+ address & ~0xfff);
+ }
+ else
+ regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd,
+ address);
+
+ dsd->dsc->pc_adjust = 4;
+ emit_nop (dsd->insn_buf);
+ dsd->insn_count = 1;
+}
+
+/* Implementation of aarch64_insn_visitor method "ldr_literal". */
+
+static void
+aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw,
+ const unsigned rt, const int is64,
+ struct aarch64_insn_data *data)
+{
+ struct aarch64_displaced_step_data *dsd
+ = (struct aarch64_displaced_step_data *) data;
+ CORE_ADDR address = data->insn_addr + offset;
+ struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 };
+
+ regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt,
+ address);
+
+ if (is_sw)
+ dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1),
+ aarch64_register (rt, 1), zero);
+ else
+ dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64),
+ aarch64_register (rt, 1), zero);
+
+ dsd->dsc->pc_adjust = 4;
+}
+
+/* Implementation of aarch64_insn_visitor method "others". */
+
+static void
+aarch64_displaced_step_others (const uint32_t insn,
+ struct aarch64_insn_data *data)
+{
+ struct aarch64_displaced_step_data *dsd
+ = (struct aarch64_displaced_step_data *) data;
+
+ aarch64_emit_insn (dsd->insn_buf, insn);
+ dsd->insn_count = 1;
+
+ if ((insn & 0xfffffc1f) == 0xd65f0000)
+ {
+ /* RET */
+ dsd->dsc->pc_adjust = 0;
+ }
+ else
+ dsd->dsc->pc_adjust = 4;
+}
+
+static const struct aarch64_insn_visitor visitor =
+{
+ aarch64_displaced_step_b,
+ aarch64_displaced_step_b_cond,
+ aarch64_displaced_step_cb,
+ aarch64_displaced_step_tb,
+ aarch64_displaced_step_adr,
+ aarch64_displaced_step_ldr_literal,
+ aarch64_displaced_step_others,
+};
+
+/* Implement the "displaced_step_copy_insn" gdbarch method. */
+
+struct displaced_step_closure *
+aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
+ CORE_ADDR from, CORE_ADDR to,
+ struct regcache *regs)
+{
+ struct displaced_step_closure *dsc = NULL;
+ enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
+ uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code);
+ struct aarch64_displaced_step_data dsd;
+
+ /* Look for a Load Exclusive instruction which begins the sequence. */
+ if (decode_masked_match (insn, 0x3fc00000, 0x08400000))
+ {
+ /* We can't displaced step atomic sequences. */
+ return NULL;
+ }
+
+ dsc = XCNEW (struct displaced_step_closure);
+ dsd.base.insn_addr = from;
+ dsd.new_addr = to;
+ dsd.regs = regs;
+ dsd.dsc = dsc;
+ aarch64_relocate_instruction (insn, &visitor,
+ (struct aarch64_insn_data *) &dsd);
+ gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS);
+
+ if (dsd.insn_count != 0)
+ {
+ int i;
+
+ /* Instruction can be relocated to scratch pad. Copy
+ relocated instruction(s) there. */
+ for (i = 0; i < dsd.insn_count; i++)
+ {
+ if (debug_displaced)
+ {
+ debug_printf ("displaced: writing insn ");
+ debug_printf ("%.8x", dsd.insn_buf[i]);
+ debug_printf (" at %s\n", paddress (gdbarch, to + i * 4));
+ }
+ write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code,
+ (ULONGEST) dsd.insn_buf[i]);
+ }
+ }
+ else
+ {
+ xfree (dsc);
+ dsc = NULL;
+ }
+
+ return dsc;
+}
+
+/* Implement the "displaced_step_fixup" gdbarch method. */
+
+void
+aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
+ struct displaced_step_closure *dsc,
+ CORE_ADDR from, CORE_ADDR to,
+ struct regcache *regs)
+{
+ if (dsc->cond)
+ {
+ ULONGEST pc;
+
+ regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc);
+ if (pc - to == 8)
+ {
+ /* Condition is true. */
+ }
+ else if (pc - to == 4)
+ {
+ /* Condition is false. */
+ dsc->pc_adjust = 4;
+ }
+ else
+ gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
+ }
+
+ if (dsc->pc_adjust != 0)
+ {
+ if (debug_displaced)
+ {
+ debug_printf ("displaced: fixup: set PC to %s:%d\n",
+ paddress (gdbarch, from), dsc->pc_adjust);
+ }
+ regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM,
+ from + dsc->pc_adjust);
+ }
+}
+
+/* Implement the "displaced_step_hw_singlestep" gdbarch method. */
+
+int
+aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
+ struct displaced_step_closure *closure)
+{
+ return 1;
+}
+
/* Initialize the current architecture based on INFO. If possible,
re-use an architecture from ARCHES, which is a list of
architectures already created during this debugging session.
/* AArch64 process record-replay related structures, defines etc. */
-#define submask(x) ((1L << ((x) + 1)) - 1)
-#define bit(obj,st) (((obj) >> (st)) & 1)
-#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
-
#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
do \
{ \
projects / deliverable / binutils-gdb.git / blobdiff