Change return type of gdbarch_software_single_step to vector<CORE_ADDR>

[deliverable/binutils-gdb.git] / gdb / alpha-tdep.c

diff --git a/gdb/alpha-tdep.c b/gdb/alpha-tdep.c
index a0485efd8baf7504fecddbb20a4b14950a7d5291..d62566c4b0a333d6afe8e1f9693e26ac183aa468 100644 (file)
--- a/gdb/alpha-tdep.c
+++ b/gdb/alpha-tdep.c
@@ -1,6 +1,6 @@
 /* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger.
 
-   Copyright (C) 1993-2016 Free Software Foundation, Inc.
+   Copyright (C) 1993-2017 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -765,11 +765,11 @@ static const int stq_c_opcode = 0x2f;
    is found, attempt to step through it.  A breakpoint is placed at the end of 
    the sequence.  */
 
-static VEC (CORE_ADDR) *
-alpha_deal_with_atomic_sequence (struct frame_info *frame)
+static std::vector<CORE_ADDR>
+alpha_deal_with_atomic_sequence (struct regcache *regcache)
 {
-  struct gdbarch *gdbarch = get_frame_arch (frame);
-  CORE_ADDR pc = get_frame_pc (frame);
+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+  CORE_ADDR pc = regcache_read_pc (regcache);
   CORE_ADDR breaks[2] = {-1, -1};
   CORE_ADDR loc = pc;
   CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence.  */
@@ -779,12 +779,11 @@ alpha_deal_with_atomic_sequence (struct frame_info *frame)
   int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed).  */  
   const int atomic_sequence_length = 16; /* Instruction sequence length.  */
   int bc_insn_count = 0; /* Conditional branch instruction count.  */
-  VEC (CORE_ADDR) *next_pcs = NULL;
 
   /* Assume all atomic sequences start with a LDL_L/LDQ_L instruction.  */
   if (INSN_OPCODE (insn) != ldl_l_opcode
       && INSN_OPCODE (insn) != ldq_l_opcode)
-    return NULL;
+    return {};
 
   /* Assume that no atomic sequence is longer than "atomic_sequence_length" 
      instructions.  */
@@ -803,8 +802,8 @@ alpha_deal_with_atomic_sequence (struct frame_info *frame)
          immediate = (immediate ^ 0x400000) - 0x400000;
 
          if (bc_insn_count >= 1)
-           return NULL; /* More than one branch found, fallback 
-                           to the standard single-step code.  */
+           return {}; /* More than one branch found, fallback
+                         to the standard single-step code.  */
 
          breaks[1] = loc + ALPHA_INSN_SIZE + immediate;
 
@@ -820,7 +819,7 @@ alpha_deal_with_atomic_sequence (struct frame_info *frame)
   /* Assume that the atomic sequence ends with a STL_C/STQ_C instruction.  */
   if (INSN_OPCODE (insn) != stl_c_opcode
       && INSN_OPCODE (insn) != stq_c_opcode)
-    return NULL;
+    return {};
 
   closing_insn = loc;
   loc += ALPHA_INSN_SIZE;
@@ -835,8 +834,10 @@ alpha_deal_with_atomic_sequence (struct frame_info *frame)
          || (breaks[1] >= pc && breaks[1] <= closing_insn)))
     last_breakpoint = 0;
 
+  std::vector<CORE_ADDR> next_pcs;
+
   for (index = 0; index <= last_breakpoint; index++)
-    VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
+    next_pcs.push_back (breaks[index]);
 
   return next_pcs;
 }
@@ -1597,9 +1598,9 @@ fp_register_sign_bit (LONGEST reg)
    the target of the coming instruction and breakpoint it.  */
 
 static CORE_ADDR
-alpha_next_pc (struct frame_info *frame, CORE_ADDR pc)
+alpha_next_pc (struct regcache *regcache, CORE_ADDR pc)
 {
-  struct gdbarch *gdbarch = get_frame_arch (frame);
+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
   unsigned int insn;
   unsigned int op;
   int regno;
@@ -1615,7 +1616,7 @@ alpha_next_pc (struct frame_info *frame, CORE_ADDR pc)
     {
       /* Jump format: target PC is:
         RB & ~3  */
-      return (get_frame_register_unsigned (frame, (insn >> 16) & 0x1f) & ~3);
+      return (regcache_raw_get_unsigned (regcache, (insn >> 16) & 0x1f) & ~3);
     }
 
   if ((op & 0x30) == 0x30)
@@ -1646,7 +1647,7 @@ alpha_next_pc (struct frame_info *frame, CORE_ADDR pc)
             regno += gdbarch_fp0_regnum (gdbarch);
        }
       
-      rav = get_frame_register_signed (frame, regno);
+      rav = regcache_raw_get_signed (regcache, regno);
 
       switch (op)
        {
@@ -1717,17 +1718,15 @@ alpha_next_pc (struct frame_info *frame, CORE_ADDR pc)
   return (pc + ALPHA_INSN_SIZE);
 }
 
-VEC (CORE_ADDR) *
-alpha_software_single_step (struct frame_info *frame)
+std::vector<CORE_ADDR>
+alpha_software_single_step (struct regcache *regcache)
 {
-  struct gdbarch *gdbarch = get_frame_arch (frame);
+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
   CORE_ADDR pc;
-  VEC (CORE_ADDR) *next_pcs = NULL;
 
-  pc = get_frame_pc (frame);
+  pc = alpha_next_pc (regcache, regcache_read_pc (regcache));
 
-  VEC_safe_push (CORE_ADDR, next_pcs, alpha_next_pc (frame, pc));
-  return next_pcs;
+  return {pc};
 }
 
 \f
@@ -1771,6 +1770,8 @@ alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
   set_gdbarch_int_bit (gdbarch, 32);
   set_gdbarch_long_bit (gdbarch, 64);
   set_gdbarch_long_long_bit (gdbarch, 64);
+  set_gdbarch_wchar_bit (gdbarch, 64);
+  set_gdbarch_wchar_signed (gdbarch, 0);
   set_gdbarch_float_bit (gdbarch, 32);
   set_gdbarch_double_bit (gdbarch, 64);
   set_gdbarch_long_double_bit (gdbarch, 64);