/* Target-dependent code for AMD64.
- Copyright 2001, 2002, 2003, 2004, 2005 Free Software Foundation,
- Inc. Contributed by Jiri Smid, SuSE Labs.
+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006
+ Free Software Foundation, Inc.
+
+ Contributed by Jiri Smid, SuSE Labs.
This file is part of GDB.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
+ Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
#include "defs.h"
#include "arch-utils.h"
struct type **type;
};
-static struct amd64_register_info amd64_register_info[] =
+static struct amd64_register_info const amd64_register_info[] =
{
{ "rax", &builtin_type_int64 },
{ "rbx", &builtin_type_int64 },
{ "r14", &builtin_type_int64 },
{ "r15", &builtin_type_int64 },
{ "rip", &builtin_type_void_func_ptr },
- { "eflags", &builtin_type_int32 },
+ { "eflags", &i386_eflags_type },
{ "cs", &builtin_type_int32 },
{ "ss", &builtin_type_int32 },
{ "ds", &builtin_type_int32 },
{ "fop", &builtin_type_int32 },
/* %xmm0 is register number 40. */
- { "xmm0", &builtin_type_v4sf },
- { "xmm1", &builtin_type_v4sf },
- { "xmm2", &builtin_type_v4sf },
- { "xmm3", &builtin_type_v4sf },
- { "xmm4", &builtin_type_v4sf },
- { "xmm5", &builtin_type_v4sf },
- { "xmm6", &builtin_type_v4sf },
- { "xmm7", &builtin_type_v4sf },
- { "xmm8", &builtin_type_v4sf },
- { "xmm9", &builtin_type_v4sf },
- { "xmm10", &builtin_type_v4sf },
- { "xmm11", &builtin_type_v4sf },
- { "xmm12", &builtin_type_v4sf },
- { "xmm13", &builtin_type_v4sf },
- { "xmm14", &builtin_type_v4sf },
- { "xmm15", &builtin_type_v4sf },
- { "mxcsr", &builtin_type_int32 }
+ { "xmm0", &i386_sse_type },
+ { "xmm1", &i386_sse_type },
+ { "xmm2", &i386_sse_type },
+ { "xmm3", &i386_sse_type },
+ { "xmm4", &i386_sse_type },
+ { "xmm5", &i386_sse_type },
+ { "xmm6", &i386_sse_type },
+ { "xmm7", &i386_sse_type },
+ { "xmm8", &i386_sse_type },
+ { "xmm9", &i386_sse_type },
+ { "xmm10", &i386_sse_type },
+ { "xmm11", &i386_sse_type },
+ { "xmm12", &i386_sse_type },
+ { "xmm13", &i386_sse_type },
+ { "xmm14", &i386_sse_type },
+ { "xmm15", &i386_sse_type },
+ { "mxcsr", &i386_mxcsr_type }
};
/* Total number of registers. */
-#define AMD64_NUM_REGS \
- (sizeof (amd64_register_info) / sizeof (amd64_register_info[0]))
+#define AMD64_NUM_REGS ARRAY_SIZE (amd64_register_info)
/* Return the name of register REGNUM. */
AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
- AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7
+ AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
+
+ /* Control and Status Flags Register. */
+ AMD64_EFLAGS_REGNUM,
+
+ /* Selector Registers. */
+ AMD64_ES_REGNUM,
+ AMD64_CS_REGNUM,
+ AMD64_SS_REGNUM,
+ AMD64_DS_REGNUM,
+ AMD64_FS_REGNUM,
+ AMD64_GS_REGNUM,
+ -1,
+ -1,
+
+ /* Segment Base Address Registers. */
+ -1,
+ -1,
+ -1,
+ -1,
+
+ /* Special Selector Registers. */
+ -1,
+ -1,
+
+ /* Floating Point Control Registers. */
+ AMD64_MXCSR_REGNUM,
+ AMD64_FCTRL_REGNUM,
+ AMD64_FSTAT_REGNUM
};
static const int amd64_dwarf_regmap_len =
static enum return_value_convention
amd64_return_value (struct gdbarch *gdbarch, struct type *type,
struct regcache *regcache,
- void *readbuf, const void *writebuf)
+ gdb_byte *readbuf, const gdb_byte *writebuf)
{
enum amd64_reg_class class[2];
int len = TYPE_LENGTH (type);
if (readbuf)
regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
- ((gdb_byte *)readbuf) + i * 8);
+ readbuf + i * 8);
if (writebuf)
regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
- ((const gdb_byte *)writebuf) + i * 8);
+ writebuf + i * 8);
}
return RETURN_VALUE_REGISTER_CONVENTION;
amd64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
int regnum, int *optimizedp,
enum lval_type *lvalp, CORE_ADDR *addrp,
- int *realnump, void *valuep)
+ int *realnump, gdb_byte *valuep)
{
struct amd64_frame_cache *cache =
amd64_frame_cache (next_frame, this_cache);
void **this_cache,
int regnum, int *optimizedp,
enum lval_type *lvalp, CORE_ADDR *addrp,
- int *realnump, void *valuep)
+ int *realnump, gdb_byte *valuep)
{
/* Make sure we've initialized the cache. */
amd64_sigtramp_frame_cache (next_frame, this_cache);