/* Target-dependent code for AMD64.
- Copyright (C) 2001-2016 Free Software Foundation, Inc.
+ Copyright (C) 2001-2017 Free Software Foundation, Inc.
Contributed by Jiri Smid, SuSE Labs.
#include "amd64-tdep.h"
#include "i387-tdep.h"
#include "x86-xstate.h"
+#include <algorithm>
#include "features/i386/amd64.c"
#include "features/i386/amd64-avx.c"
#include "features/i386/amd64-mpx.c"
#include "features/i386/amd64-avx-mpx.c"
-#include "features/i386/amd64-avx512.c"
+#include "features/i386/amd64-avx-avx512.c"
+#include "features/i386/amd64-avx-mpx-avx512-pku.c"
#include "features/i386/x32.c"
#include "features/i386/x32-avx.c"
-#include "features/i386/x32-avx512.c"
+#include "features/i386/x32-avx-avx512.c"
#include "ax.h"
#include "ax-gdb.h"
"xmm28", "xmm29", "xmm30", "xmm31"
};
+static const char *amd64_pkeys_names[] = {
+ "pkru"
+};
+
/* DWARF Register Number Mapping as defined in the System V psABI,
section 3.6. */
struct regcache *regcache,
int regnum)
{
- gdb_byte raw_buf[MAX_REGISTER_SIZE];
+ gdb_byte *raw_buf = (gdb_byte *) alloca (register_size (gdbarch, regnum));
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum register_status status;
struct value *result_value;
struct regcache *regcache,
int regnum, const gdb_byte *buf)
{
- gdb_byte raw_buf[MAX_REGISTER_SIZE];
+ gdb_byte *raw_buf = (gdb_byte *) alloca (register_size (gdbarch, regnum));
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (i386_byte_regnum_p (gdbarch, regnum))
if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
|| code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
|| code == TYPE_CODE_CHAR
- || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
+ || code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type))
&& (len == 1 || len == 2 || len == 4 || len == 8))
theclass[0] = AMD64_INTEGER;
gdb_assert (regnum != -1);
if (readbuf)
- regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
+ regcache_raw_read_part (regcache, regnum, offset, std::min (len, 8),
readbuf + i * 8);
if (writebuf)
- regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
+ regcache_raw_write_part (regcache, regnum, offset, std::min (len, 8),
writebuf + i * 8);
}
gdb_assert (regnum != -1);
memset (buf, 0, sizeof buf);
- memcpy (buf, valbuf + j * 8, min (len, 8));
+ memcpy (buf, valbuf + j * 8, std::min (len, 8));
regcache_raw_write_part (regcache, regnum, offset, 8, buf);
}
}
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte buf[8];
+ /* BND registers can be in arbitrary values at the moment of the
+ inferior call. This can cause boundary violations that are not
+ due to a real bug or even desired by the user. The best to be done
+ is set the BND registers to allow access to the whole memory, INIT
+ state, before pushing the inferior call. */
+ i387_reset_bnd_regs (gdbarch, regcache);
+
/* Pass arguments. */
sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
the user program would return to. */
if (insn[0] == 0xe8)
{
- gdb_byte push_buf[16];
- unsigned int ret_addr;
+ gdb_byte push_buf[32];
+ CORE_ADDR ret_addr;
+ int i = 0;
/* Where "ret" in the original code will return to. */
ret_addr = oldloc + insn_length;
- push_buf[0] = 0x68; /* pushq $... */
- store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
+
+ /* If pushing an address higher than or equal to 0x80000000,
+ avoid 'pushq', as that sign extends its 32-bit operand, which
+ would be incorrect. */
+ if (ret_addr <= 0x7fffffff)
+ {
+ push_buf[0] = 0x68; /* pushq $... */
+ store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
+ i = 5;
+ }
+ else
+ {
+ push_buf[i++] = 0x48; /* sub $0x8,%rsp */
+ push_buf[i++] = 0x83;
+ push_buf[i++] = 0xec;
+ push_buf[i++] = 0x08;
+
+ push_buf[i++] = 0xc7; /* movl $imm,(%rsp) */
+ push_buf[i++] = 0x04;
+ push_buf[i++] = 0x24;
+ store_unsigned_integer (&push_buf[i], 4, byte_order,
+ ret_addr & 0xffffffff);
+ i += 4;
+
+ push_buf[i++] = 0xc7; /* movl $imm,4(%rsp) */
+ push_buf[i++] = 0x44;
+ push_buf[i++] = 0x24;
+ push_buf[i++] = 0x04;
+ store_unsigned_integer (&push_buf[i], 4, byte_order,
+ ret_addr >> 32);
+ i += 4;
+ }
+ gdb_assert (i <= sizeof (push_buf));
/* Push the push. */
- append_insns (to, 5, push_buf);
+ append_insns (to, i, push_buf);
/* Convert the relative call to a relative jump. */
insn[0] = 0xe9;
if (current_pc > pc + offset_and)
cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
- return min (pc + offset + 2, current_pc);
+ return std::min (pc + offset + 2, current_pc);
}
/* Similar to amd64_analyze_stack_align for x32. */
if (current_pc > pc + offset_and)
cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg);
- return min (pc + offset + 2, current_pc);
+ return std::min (pc + offset + 2, current_pc);
}
/* Do a limited analysis of the prologue at PC and update CACHE
&& (cust != NULL
&& COMPUNIT_PRODUCER (cust) != NULL
&& startswith (COMPUNIT_PRODUCER (cust), "clang ")))
- return max (start_pc, post_prologue_pc);
+ return std::max (start_pc, post_prologue_pc);
}
amd64_init_frame_cache (&cache);
tdep->bnd0r_regnum = AMD64_BND0R_REGNUM;
}
+ if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments") != NULL)
+ {
+ const struct tdesc_feature *feature =
+ tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments");
+ struct tdesc_arch_data *tdesc_data_segments =
+ (struct tdesc_arch_data *) info.tdep_info;
+
+ tdesc_numbered_register (feature, tdesc_data_segments,
+ AMD64_FSBASE_REGNUM, "fs_base");
+ tdesc_numbered_register (feature, tdesc_data_segments,
+ AMD64_GSBASE_REGNUM, "gs_base");
+ }
+
+ if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys") != NULL)
+ {
+ tdep->pkeys_register_names = amd64_pkeys_names;
+ tdep->pkru_regnum = AMD64_PKRU_REGNUM;
+ tdep->num_pkeys_regs = 1;
+ }
+
tdep->num_byte_regs = 20;
tdep->num_word_regs = 16;
tdep->num_dword_regs = 16;
{
switch (xcr0 & X86_XSTATE_ALL_MASK)
{
- case X86_XSTATE_MPX_AVX512_MASK:
- case X86_XSTATE_AVX512_MASK:
- return tdesc_amd64_avx512;
+ case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK:
+ return tdesc_amd64_avx_mpx_avx512_pku;
+ case X86_XSTATE_AVX_AVX512_MASK:
+ return tdesc_amd64_avx_avx512;
case X86_XSTATE_MPX_MASK:
return tdesc_amd64_mpx;
case X86_XSTATE_AVX_MPX_MASK:
initialize_tdesc_amd64_avx ();
initialize_tdesc_amd64_mpx ();
initialize_tdesc_amd64_avx_mpx ();
- initialize_tdesc_amd64_avx512 ();
+ initialize_tdesc_amd64_avx_avx512 ();
+ initialize_tdesc_amd64_avx_mpx_avx512_pku ();
initialize_tdesc_x32 ();
initialize_tdesc_x32_avx ();
- initialize_tdesc_x32_avx512 ();
+ initialize_tdesc_x32_avx_avx512 ();
}
\f