Add IA64_MAX_FP_REGISTER_SIZE

[deliverable/binutils-gdb.git] / gdb / amd64-tdep.c

diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c
index fc1f134a18098862fab92ad45e55b05372027beb..9ff7dfc5134f123b1924623356b40e3bb3e57905 100644 (file)
--- a/gdb/amd64-tdep.c
+++ b/gdb/amd64-tdep.c
@@ -46,11 +46,12 @@
 #include "features/i386/amd64-avx.c"
 #include "features/i386/amd64-mpx.c"
 #include "features/i386/amd64-avx-mpx.c"
-#include "features/i386/amd64-avx512.c"
+#include "features/i386/amd64-avx-avx512.c"
+#include "features/i386/amd64-avx-mpx-avx512-pku.c"
 
 #include "features/i386/x32.c"
 #include "features/i386/x32-avx.c"
-#include "features/i386/x32-avx512.c"
+#include "features/i386/x32-avx-avx512.c"
 
 #include "ax.h"
 #include "ax-gdb.h"
@@ -156,6 +157,10 @@ static const char *amd64_xmm_avx512_names[] = {
     "xmm28",  "xmm29",  "xmm30",  "xmm31"
 };
 
+static const char *amd64_pkeys_names[] = {
+    "pkru"
+};
+
 /* DWARF Register Number Mapping as defined in the System V psABI,
    section 3.6.  */
 
@@ -674,7 +679,7 @@ amd64_classify (struct type *type, enum amd64_reg_class theclass[2])
   if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
        || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE
        || code == TYPE_CODE_CHAR
-       || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
+       || code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type))
       && (len == 1 || len == 2 || len == 4 || len == 8))
     theclass[0] = AMD64_INTEGER;
 
@@ -999,6 +1004,13 @@ amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
   gdb_byte buf[8];
 
+  /* BND registers can be in arbitrary values at the moment of the
+     inferior call.  This can cause boundary violations that are not
+     due to a real bug or even desired by the user.  The best to be done
+     is set the BND registers to allow access to the whole memory, INIT
+     state, before pushing the inferior call.   */
+  i387_reset_bnd_regs (gdbarch, regcache);
+
   /* Pass arguments.  */
   sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
 
@@ -3047,6 +3059,26 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
       tdep->bnd0r_regnum = AMD64_BND0R_REGNUM;
     }
 
+  if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments") != NULL)
+    {
+      const struct tdesc_feature *feature =
+         tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments");
+      struct tdesc_arch_data *tdesc_data_segments =
+         (struct tdesc_arch_data *) info.tdep_info;
+
+      tdesc_numbered_register (feature, tdesc_data_segments,
+                      AMD64_FSBASE_REGNUM, "fs_base");
+      tdesc_numbered_register (feature, tdesc_data_segments,
+                      AMD64_GSBASE_REGNUM, "gs_base");
+    }
+
+  if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys") != NULL)
+    {
+      tdep->pkeys_register_names = amd64_pkeys_names;
+      tdep->pkru_regnum = AMD64_PKRU_REGNUM;
+      tdep->num_pkeys_regs = 1;
+    }
+
   tdep->num_byte_regs = 20;
   tdep->num_word_regs = 16;
   tdep->num_dword_regs = 16;
@@ -3189,9 +3221,10 @@ amd64_target_description (uint64_t xcr0)
 {
   switch (xcr0 & X86_XSTATE_ALL_MASK)
     {
-    case X86_XSTATE_MPX_AVX512_MASK:
-    case X86_XSTATE_AVX512_MASK:
-      return tdesc_amd64_avx512;
+    case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK:
+      return tdesc_amd64_avx_mpx_avx512_pku;
+    case X86_XSTATE_AVX_AVX512_MASK:
+      return tdesc_amd64_avx_avx512;
     case X86_XSTATE_MPX_MASK:
       return tdesc_amd64_mpx;
     case X86_XSTATE_AVX_MPX_MASK:
@@ -3213,11 +3246,12 @@ _initialize_amd64_tdep (void)
   initialize_tdesc_amd64_avx ();
   initialize_tdesc_amd64_mpx ();
   initialize_tdesc_amd64_avx_mpx ();
-  initialize_tdesc_amd64_avx512 ();
+  initialize_tdesc_amd64_avx_avx512 ();
+  initialize_tdesc_amd64_avx_mpx_avx512_pku ();
 
   initialize_tdesc_x32 ();
   initialize_tdesc_x32_avx ();
-  initialize_tdesc_x32_avx512 ();
+  initialize_tdesc_x32_avx_avx512 ();
 }
 \f