/* Common target dependent code for GDB on ARM systems.
- Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
- 2001, 2002, 2003 Free Software Foundation, Inc.
+
+ Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999, 2000,
+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
+ Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330,
- Boston, MA 02111-1307, USA. */
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include <ctype.h> /* XXX for isupper () */
#include "inferior.h"
#include "gdbcmd.h"
#include "gdbcore.h"
-#include "symfile.h"
#include "gdb_string.h"
#include "dis-asm.h" /* For register styles. */
#include "regcache.h"
#include "doublest.h"
#include "value.h"
#include "arch-utils.h"
-#include "solib-svr4.h"
#include "osabi.h"
+#include "frame-unwind.h"
+#include "frame-base.h"
+#include "trad-frame.h"
+#include "objfiles.h"
+#include "dwarf2-frame.h"
+#include "gdbtypes.h"
+#include "prologue-value.h"
+#include "target-descriptions.h"
+#include "user-regs.h"
#include "arm-tdep.h"
#include "gdb/sim-arm.h"
#include "elf/arm.h"
#include "gdb_assert.h"
+#include "vec.h"
static int arm_debug;
-/* Each OS has a different mechanism for accessing the various
- registers stored in the sigcontext structure.
-
- SIGCONTEXT_REGISTER_ADDRESS should be defined to the name (or
- function pointer) which may be used to determine the addresses
- of the various saved registers in the sigcontext structure.
-
- For the ARM target, there are three parameters to this function.
- The first is the pc value of the frame under consideration, the
- second the stack pointer of this frame, and the last is the
- register number to fetch.
-
- If the tm.h file does not define this macro, then it's assumed that
- no mechanism is needed and we define SIGCONTEXT_REGISTER_ADDRESS to
- be 0.
-
- When it comes time to multi-arching this code, see the identically
- named machinery in ia64-tdep.c for an example of how it could be
- done. It should not be necessary to modify the code below where
- this macro is used. */
-
-#ifdef SIGCONTEXT_REGISTER_ADDRESS
-#ifndef SIGCONTEXT_REGISTER_ADDRESS_P
-#define SIGCONTEXT_REGISTER_ADDRESS_P() 1
-#endif
-#else
-#define SIGCONTEXT_REGISTER_ADDRESS(SP,PC,REG) 0
-#define SIGCONTEXT_REGISTER_ADDRESS_P() 0
-#endif
-
/* Macros for setting and testing a bit in a minimal symbol that marks
it as Thumb function. The MSB of the minimal symbol's "info" field
- is used for this purpose. This field is already being used to store
- the symbol size, so the assumption is that the symbol size cannot
- exceed 2^31.
+ is used for this purpose.
MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
- MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol.
- MSYMBOL_SIZE Returns the size of the minimal symbol,
- i.e. the "info" field with the "special" bit
- masked out. */
+ MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
#define MSYMBOL_SET_SPECIAL(msym) \
- MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
- | 0x80000000)
+ MSYMBOL_TARGET_FLAG_1 (msym) = 1
#define MSYMBOL_IS_SPECIAL(msym) \
- (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
+ MSYMBOL_TARGET_FLAG_1 (msym)
+
+/* Macros for swapping shorts and ints. In the unlikely case that anybody else needs these,
+ move to a general header. (A better solution might be to define memory read routines that
+ know whether they are reading code or data.) */
-#define MSYMBOL_SIZE(msym) \
- ((long) MSYMBOL_INFO (msym) & 0x7fffffff)
+#define SWAP_SHORT(x) \
+ ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
+
+#define SWAP_INT(x) \
+ ( ((x & 0xff000000) >> 24) \
+ | ((x & 0x00ff0000) >> 8) \
+ | ((x & 0x0000ff00) << 8) \
+ | ((x & 0x000000ff) << 24))
+
+/* Per-objfile data used for mapping symbols. */
+static const struct objfile_data *arm_objfile_data_key;
+
+struct arm_mapping_symbol
+{
+ bfd_vma value;
+ char type;
+};
+typedef struct arm_mapping_symbol arm_mapping_symbol_s;
+DEF_VEC_O(arm_mapping_symbol_s);
+
+struct arm_per_objfile
+{
+ VEC(arm_mapping_symbol_s) **section_maps;
+};
/* The list of available "set arm ..." and "show arm ..." commands. */
static struct cmd_list_element *setarmcmdlist = NULL;
"softfpa",
"fpa",
"softvfp",
- "vfp"
+ "vfp",
+ NULL
};
/* A variable that can be configured by the user. */
static enum arm_float_model arm_fp_model = ARM_FLOAT_AUTO;
static const char *current_fp_model = "auto";
+/* The ABI to use. Keep this in sync with arm_abi_kind. */
+static const char *arm_abi_strings[] =
+{
+ "auto",
+ "APCS",
+ "AAPCS",
+ NULL
+};
+
+/* A variable that can be configured by the user. */
+static enum arm_abi_kind arm_abi_global = ARM_ABI_AUTO;
+static const char *arm_abi_string = "auto";
+
+/* The execution mode to assume. */
+static const char *arm_mode_strings[] =
+ {
+ "auto",
+ "arm",
+ "thumb"
+ };
+
+static const char *arm_fallback_mode_string = "auto";
+static const char *arm_force_mode_string = "auto";
+
/* Number of different reg name sets (options). */
static int num_disassembly_options;
-/* We have more registers than the disassembler as gdb can print the value
- of special registers as well.
- The general register names are overwritten by whatever is being used by
- the disassembler at the moment. We also adjust the case of cpsr and fps. */
+/* The standard register names, and all the valid aliases for them. */
+static const struct
+{
+ const char *name;
+ int regnum;
+} arm_register_aliases[] = {
+ /* Basic register numbers. */
+ { "r0", 0 },
+ { "r1", 1 },
+ { "r2", 2 },
+ { "r3", 3 },
+ { "r4", 4 },
+ { "r5", 5 },
+ { "r6", 6 },
+ { "r7", 7 },
+ { "r8", 8 },
+ { "r9", 9 },
+ { "r10", 10 },
+ { "r11", 11 },
+ { "r12", 12 },
+ { "r13", 13 },
+ { "r14", 14 },
+ { "r15", 15 },
+ /* Synonyms (argument and variable registers). */
+ { "a1", 0 },
+ { "a2", 1 },
+ { "a3", 2 },
+ { "a4", 3 },
+ { "v1", 4 },
+ { "v2", 5 },
+ { "v3", 6 },
+ { "v4", 7 },
+ { "v5", 8 },
+ { "v6", 9 },
+ { "v7", 10 },
+ { "v8", 11 },
+ /* Other platform-specific names for r9. */
+ { "sb", 9 },
+ { "tr", 9 },
+ /* Special names. */
+ { "ip", 12 },
+ { "sp", 13 },
+ { "lr", 14 },
+ { "pc", 15 },
+ /* Names used by GCC (not listed in the ARM EABI). */
+ { "sl", 10 },
+ { "fp", 11 },
+ /* A special name from the older ATPCS. */
+ { "wr", 7 },
+};
-/* Initial value: Register names used in ARM's ISA documentation. */
-static char * arm_register_name_strings[] =
+static const char *const arm_register_names[] =
{"r0", "r1", "r2", "r3", /* 0 1 2 3 */
"r4", "r5", "r6", "r7", /* 4 5 6 7 */
"r8", "r9", "r10", "r11", /* 8 9 10 11 */
"f0", "f1", "f2", "f3", /* 16 17 18 19 */
"f4", "f5", "f6", "f7", /* 20 21 22 23 */
"fps", "cpsr" }; /* 24 25 */
-static char **arm_register_names = arm_register_name_strings;
/* Valid register name styles. */
static const char **valid_disassembly_styles;
/* Disassembly style to use. Default to "std" register names. */
static const char *disassembly_style;
-/* Index to that option in the opcodes table. */
-static int current_option;
/* This is used to keep the bfd arch_info in sync with the disassembly
style. */
static void set_disassembly_style (void);
static void convert_from_extended (const struct floatformat *, const void *,
- void *);
+ void *, int);
static void convert_to_extended (const struct floatformat *, void *,
- const void *);
-
-/* Define other aspects of the stack frame. We keep the offsets of
- all saved registers, 'cause we need 'em a lot! We also keep the
- current size of the stack frame, and the offset of the frame
- pointer from the stack pointer (for frameless functions, and when
- we're still in the prologue of a function with a frame). */
+ const void *, int);
-struct frame_extra_info
+struct arm_prologue_cache
{
+ /* The stack pointer at the time this frame was created; i.e. the
+ caller's stack pointer when this function was called. It is used
+ to identify this frame. */
+ CORE_ADDR prev_sp;
+
+ /* The frame base for this frame is just prev_sp - frame size.
+ FRAMESIZE is the distance from the frame pointer to the
+ initial stack pointer. */
+
int framesize;
- int frameoffset;
+
+ /* The register used to hold the frame pointer for this frame. */
int framereg;
+
+ /* Saved register offsets. */
+ struct trad_frame_saved_reg *saved_regs;
};
/* Addresses for calling Thumb functions have the bit 0 set.
#define MAKE_THUMB_ADDR(addr) ((addr) | 1)
#define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
-static int
-arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe)
-{
- return (DEPRECATED_FRAME_SAVED_PC (thisframe) >= LOWEST_PC);
-}
-
/* Set to true if the 32-bit mode is in use. */
int arm_apcs_32 = 1;
-/* Flag set by arm_fix_call_dummy that tells whether the target
- function is a Thumb function. This flag is checked by
- arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
- its use in valops.c) to pass the function address as an additional
- parameter. */
+/* Determine if FRAME is executing in Thumb mode. */
+
+static int
+arm_frame_is_thumb (struct frame_info *frame)
+{
+ CORE_ADDR cpsr;
+
+ /* Every ARM frame unwinder can unwind the T bit of the CPSR, either
+ directly (from a signal frame or dummy frame) or by interpreting
+ the saved LR (from a prologue or DWARF frame). So consult it and
+ trust the unwinders. */
+ cpsr = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
-static int target_is_thumb;
+ return (cpsr & CPSR_T) != 0;
+}
-/* Flag set by arm_fix_call_dummy that tells whether the calling
- function is a Thumb function. This flag is checked by
- arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
+/* Callback for VEC_lower_bound. */
-static int caller_is_thumb;
+static inline int
+arm_compare_mapping_symbols (const struct arm_mapping_symbol *lhs,
+ const struct arm_mapping_symbol *rhs)
+{
+ return lhs->value < rhs->value;
+}
/* Determine if the program counter specified in MEMADDR is in a Thumb
- function. */
+ function. This function should be called for addresses unrelated to
+ any executing frame; otherwise, prefer arm_frame_is_thumb. */
-int
+static int
arm_pc_is_thumb (CORE_ADDR memaddr)
{
+ struct obj_section *sec;
struct minimal_symbol *sym;
/* If bit 0 of the address is set, assume this is a Thumb address. */
if (IS_THUMB_ADDR (memaddr))
return 1;
- /* Thumb functions have a "special" bit set in minimal symbols. */
- sym = lookup_minimal_symbol_by_pc (memaddr);
- if (sym)
- {
- return (MSYMBOL_IS_SPECIAL (sym));
- }
- else
+ /* If the user wants to override the symbol table, let him. */
+ if (strcmp (arm_force_mode_string, "arm") == 0)
+ return 0;
+ if (strcmp (arm_force_mode_string, "thumb") == 0)
+ return 1;
+
+ /* If there are mapping symbols, consult them. */
+ sec = find_pc_section (memaddr);
+ if (sec != NULL)
{
- return 0;
+ struct arm_per_objfile *data;
+ VEC(arm_mapping_symbol_s) *map;
+ struct arm_mapping_symbol map_key = { memaddr - obj_section_addr (sec),
+ 0 };
+ unsigned int idx;
+
+ data = objfile_data (sec->objfile, arm_objfile_data_key);
+ if (data != NULL)
+ {
+ map = data->section_maps[sec->the_bfd_section->index];
+ if (!VEC_empty (arm_mapping_symbol_s, map))
+ {
+ struct arm_mapping_symbol *map_sym;
+
+ idx = VEC_lower_bound (arm_mapping_symbol_s, map, &map_key,
+ arm_compare_mapping_symbols);
+
+ /* VEC_lower_bound finds the earliest ordered insertion
+ point. If the following symbol starts at this exact
+ address, we use that; otherwise, the preceding
+ mapping symbol covers this address. */
+ if (idx < VEC_length (arm_mapping_symbol_s, map))
+ {
+ map_sym = VEC_index (arm_mapping_symbol_s, map, idx);
+ if (map_sym->value == map_key.value)
+ return map_sym->type == 't';
+ }
+
+ if (idx > 0)
+ {
+ map_sym = VEC_index (arm_mapping_symbol_s, map, idx - 1);
+ return map_sym->type == 't';
+ }
+ }
+ }
}
-}
-/* Determine if the program counter specified in MEMADDR is in a call
- dummy being called from a Thumb function. */
+ /* Thumb functions have a "special" bit set in minimal symbols. */
+ sym = lookup_minimal_symbol_by_pc (memaddr);
+ if (sym)
+ return (MSYMBOL_IS_SPECIAL (sym));
-int
-arm_pc_is_thumb_dummy (CORE_ADDR memaddr)
-{
- CORE_ADDR sp = read_sp ();
-
- /* FIXME: Until we switch for the new call dummy macros, this heuristic
- is the best we can do. We are trying to determine if the pc is on
- the stack, which (hopefully) will only happen in a call dummy.
- We hope the current stack pointer is not so far alway from the dummy
- frame location (true if we have not pushed large data structures or
- gone too many levels deep) and that our 1024 is not enough to consider
- code regions as part of the stack (true for most practical purposes). */
- if (DEPRECATED_PC_IN_CALL_DUMMY (memaddr, sp, sp + 1024))
- return caller_is_thumb;
- else
+ /* If the user wants to override the fallback mode, let them. */
+ if (strcmp (arm_fallback_mode_string, "arm") == 0)
return 0;
+ if (strcmp (arm_fallback_mode_string, "thumb") == 0)
+ return 1;
+
+ /* If we couldn't find any symbol, but we're talking to a running
+ target, then trust the current value of $cpsr. This lets
+ "display/i $pc" always show the correct mode (though if there is
+ a symbol table we will not reach here, so it still may not be
+ displayed in the mode it will be executed). */
+ if (target_has_registers)
+ return arm_frame_is_thumb (get_current_frame ());
+
+ /* Otherwise we're out of luck; we assume ARM. */
+ return 0;
}
/* Remove useless bits from addresses in a running program. */
static CORE_ADDR
-arm_addr_bits_remove (CORE_ADDR val)
+arm_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR val)
{
if (arm_apcs_32)
- return (val & (arm_pc_is_thumb (val) ? 0xfffffffe : 0xfffffffc));
+ return UNMAKE_THUMB_ADDR (val);
else
return (val & 0x03fffffc);
}
/* When reading symbols, we need to zap the low bit of the address,
which may be set to 1 for Thumb functions. */
static CORE_ADDR
-arm_smash_text_address (CORE_ADDR val)
+arm_smash_text_address (struct gdbarch *gdbarch, CORE_ADDR val)
{
return val & ~1;
}
-/* Immediately after a function call, return the saved pc. Can't
- always go through the frames for this because on some machines the
- new frame is not set up until the new function executes some
- instructions. */
+/* Analyze a Thumb prologue, looking for a recognizable stack frame
+ and frame pointer. Scan until we encounter a store that could
+ clobber the stack frame unexpectedly, or an unknown instruction. */
static CORE_ADDR
-arm_saved_pc_after_call (struct frame_info *frame)
+thumb_analyze_prologue (struct gdbarch *gdbarch,
+ CORE_ADDR start, CORE_ADDR limit,
+ struct arm_prologue_cache *cache)
{
- return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM));
-}
-
-/* Determine whether the function invocation represented by FI has a
- frame on the stack associated with it. If it does return zero,
- otherwise return 1. */
-
-static int
-arm_frameless_function_invocation (struct frame_info *fi)
-{
- CORE_ADDR func_start, after_prologue;
- int frameless;
-
- /* Sometimes we have functions that do a little setup (like saving the
- vN registers with the stmdb instruction, but DO NOT set up a frame.
- The symbol table will report this as a prologue. However, it is
- important not to try to parse these partial frames as frames, or we
- will get really confused.
-
- So I will demand 3 instructions between the start & end of the
- prologue before I call it a real prologue, i.e. at least
- mov ip, sp,
- stmdb sp!, {}
- sub sp, ip, #4. */
-
- func_start = (get_pc_function_start (get_frame_pc (fi)) + FUNCTION_START_OFFSET);
- after_prologue = SKIP_PROLOGUE (func_start);
+ int i;
+ pv_t regs[16];
+ struct pv_area *stack;
+ struct cleanup *back_to;
+ CORE_ADDR offset;
- /* There are some frameless functions whose first two instructions
- follow the standard APCS form, in which case after_prologue will
- be func_start + 8. */
+ for (i = 0; i < 16; i++)
+ regs[i] = pv_register (i, 0);
+ stack = make_pv_area (ARM_SP_REGNUM);
+ back_to = make_cleanup_free_pv_area (stack);
- frameless = (after_prologue < func_start + 12);
- return frameless;
-}
+ while (start < limit)
+ {
+ unsigned short insn;
-/* The address of the arguments in the frame. */
-static CORE_ADDR
-arm_frame_args_address (struct frame_info *fi)
-{
- return get_frame_base (fi);
-}
+ insn = read_memory_unsigned_integer (start, 2);
-/* The address of the local variables in the frame. */
-static CORE_ADDR
-arm_frame_locals_address (struct frame_info *fi)
-{
- return get_frame_base (fi);
-}
+ if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
+ insn = SWAP_SHORT (insn);
-/* The number of arguments being passed in the frame. */
-static int
-arm_frame_num_args (struct frame_info *fi)
-{
- /* We have no way of knowing. */
- return -1;
-}
+ if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
+ {
+ int regno;
+ int mask;
-/* A typical Thumb prologue looks like this:
- push {r7, lr}
- add sp, sp, #-28
- add r7, sp, #12
- Sometimes the latter instruction may be replaced by:
- mov r7, sp
-
- or like this:
- push {r7, lr}
- mov r7, sp
- sub sp, #12
-
- or, on tpcs, like this:
- sub sp,#16
- push {r7, lr}
- (many instructions)
- mov r7, sp
- sub sp, #12
-
- There is always one instruction of three classes:
- 1 - push
- 2 - setting of r7
- 3 - adjusting of sp
-
- When we have found at least one of each class we are done with the prolog.
- Note that the "sub sp, #NN" before the push does not count.
- */
+ if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
+ break;
-static CORE_ADDR
-thumb_skip_prologue (CORE_ADDR pc, CORE_ADDR func_end)
-{
- CORE_ADDR current_pc;
- /* findmask:
- bit 0 - push { rlist }
- bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
- bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
- */
- int findmask = 0;
-
- for (current_pc = pc;
- current_pc + 2 < func_end && current_pc < pc + 40;
- current_pc += 2)
- {
- unsigned short insn = read_memory_unsigned_integer (current_pc, 2);
+ /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
+ whether to save LR (R14). */
+ mask = (insn & 0xff) | ((insn & 0x100) << 6);
- if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
- {
- findmask |= 1; /* push found */
+ /* Calculate offsets of saved R0-R7 and LR. */
+ for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
+ if (mask & (1 << regno))
+ {
+ regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
+ -4);
+ pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
+ }
}
else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
sub sp, #simm */
{
- if ((findmask & 1) == 0) /* before push ? */
- continue;
+ offset = (insn & 0x7f) << 2; /* get scaled offset */
+ if (insn & 0x80) /* Check for SUB. */
+ regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
+ -offset);
else
- findmask |= 4; /* add/sub sp found */
+ regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
+ offset);
}
else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
+ regs[THUMB_FP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
+ (insn & 0xff) << 2);
+ else if ((insn & 0xff00) == 0x4600) /* mov hi, lo or mov lo, hi */
{
- findmask |= 2; /* setting of r7 found */
+ int dst_reg = (insn & 0x7) + ((insn & 0x80) >> 4);
+ int src_reg = (insn & 0x78) >> 3;
+ regs[dst_reg] = regs[src_reg];
}
- else if (insn == 0x466f) /* mov r7, sp */
+ else if ((insn & 0xf800) == 0x9000) /* str rd, [sp, #off] */
{
- findmask |= 2; /* setting of r7 found */
+ /* Handle stores to the stack. Normally pushes are used,
+ but with GCC -mtpcs-frame, there may be other stores
+ in the prologue to create the frame. */
+ int regno = (insn >> 8) & 0x7;
+ pv_t addr;
+
+ offset = (insn & 0xff) << 2;
+ addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
+
+ if (pv_area_store_would_trash (stack, addr))
+ break;
+
+ pv_area_store (stack, addr, 4, regs[regno]);
}
- else if (findmask == (4+2+1))
+ else
{
- /* We have found one of each type of prologue instruction */
+ /* We don't know what this instruction is. We're finished
+ scanning. NOTE: Recognizing more safe-to-ignore
+ instructions here will improve support for optimized
+ code. */
break;
}
- else
- /* Something in the prolog that we don't care about or some
- instruction from outside the prolog scheduled here for
- optimization. */
- continue;
+
+ start += 2;
+ }
+
+ if (cache == NULL)
+ {
+ do_cleanups (back_to);
+ return start;
}
- return current_pc;
+ if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
+ {
+ /* Frame pointer is fp. Frame size is constant. */
+ cache->framereg = ARM_FP_REGNUM;
+ cache->framesize = -regs[ARM_FP_REGNUM].k;
+ }
+ else if (pv_is_register (regs[THUMB_FP_REGNUM], ARM_SP_REGNUM))
+ {
+ /* Frame pointer is r7. Frame size is constant. */
+ cache->framereg = THUMB_FP_REGNUM;
+ cache->framesize = -regs[THUMB_FP_REGNUM].k;
+ }
+ else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
+ {
+ /* Try the stack pointer... this is a bit desperate. */
+ cache->framereg = ARM_SP_REGNUM;
+ cache->framesize = -regs[ARM_SP_REGNUM].k;
+ }
+ else
+ {
+ /* We're just out of luck. We don't know where the frame is. */
+ cache->framereg = -1;
+ cache->framesize = 0;
+ }
+
+ for (i = 0; i < 16; i++)
+ if (pv_area_find_reg (stack, gdbarch, i, &offset))
+ cache->saved_regs[i].addr = offset;
+
+ do_cleanups (back_to);
+ return start;
}
/* Advance the PC across any function entry prologue instructions to
sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
static CORE_ADDR
-arm_skip_prologue (CORE_ADDR pc)
+arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
{
unsigned long inst;
CORE_ADDR skip_pc;
- CORE_ADDR func_addr, func_end = 0;
- char *func_name;
+ CORE_ADDR func_addr, limit_pc;
struct symtab_and_line sal;
/* If we're in a dummy frame, don't even try to skip the prologue. */
- if (DEPRECATED_PC_IN_CALL_DUMMY (pc, 0, 0))
+ if (deprecated_pc_in_call_dummy (pc))
return pc;
- /* See what the symbol table says. */
-
- if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
+ /* See if we can determine the end of the prologue via the symbol table.
+ If so, then return either PC, or the PC after the prologue, whichever
+ is greater. */
+ if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
{
- struct symbol *sym;
-
- /* Found a function. */
- sym = lookup_symbol (func_name, NULL, VAR_NAMESPACE, NULL, NULL);
- if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
- {
- /* Don't use this trick for assembly source files. */
- sal = find_pc_line (func_addr, 0);
- if ((sal.line != 0) && (sal.end < func_end))
- return sal.end;
- }
+ CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
+ if (post_prologue_pc != 0)
+ return max (pc, post_prologue_pc);
}
- /* Check if this is Thumb code. */
- if (arm_pc_is_thumb (pc))
- return thumb_skip_prologue (pc, func_end);
-
- /* Can't find the prologue end in the symbol table, try it the hard way
- by disassembling the instructions. */
+ /* Can't determine prologue from the symbol table, need to examine
+ instructions. */
+ /* Find an upper limit on the function prologue using the debug
+ information. If the debug information could not be used to provide
+ that bound, then use an arbitrary large number as the upper bound. */
/* Like arm_scan_prologue, stop no later than pc + 64. */
- if (func_end == 0 || func_end > pc + 64)
- func_end = pc + 64;
+ limit_pc = skip_prologue_using_sal (pc);
+ if (limit_pc == 0)
+ limit_pc = pc + 64; /* Magic. */
+
- for (skip_pc = pc; skip_pc < func_end; skip_pc += 4)
+ /* Check if this is Thumb code. */
+ if (arm_pc_is_thumb (pc))
+ return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL);
+
+ for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4)
{
- inst = read_memory_integer (skip_pc, 4);
+ inst = read_memory_unsigned_integer (skip_pc, 4);
+
+ if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
+ inst = SWAP_INT (inst);
/* "mov ip, sp" is no longer a required part of the prologue. */
if (inst == 0xe1a0c00d) /* mov ip, sp */
continue;
+ if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
+ continue;
+
+ if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
+ continue;
+
/* Some prologues begin with "str lr, [sp, #-4]!". */
if (inst == 0xe52de004) /* str lr, [sp, #-4]! */
continue;
2) which registers are saved on it
3) the offsets of saved regs
4) the offset from the stack pointer to the frame pointer
- This information is stored in the "extra" fields of the frame_info.
A typical Thumb function prologue would create this stack frame
(offsets relative to FP)
/* *INDENT-ON* */
static void
-thumb_scan_prologue (struct frame_info *fi)
+thumb_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR prev_pc,
+ CORE_ADDR block_addr, struct arm_prologue_cache *cache)
{
CORE_ADDR prologue_start;
CORE_ADDR prologue_end;
CORE_ADDR current_pc;
- /* Which register has been copied to register n? */
- int saved_reg[16];
- /* findmask:
- bit 0 - push { rlist }
- bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
- bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
- */
- int findmask = 0;
- int i;
- /* Don't try to scan dummy frames. */
- if (fi != NULL
- && DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0))
- return;
-
- if (find_pc_partial_function (get_frame_pc (fi), NULL, &prologue_start, &prologue_end))
+ if (find_pc_partial_function (block_addr, NULL, &prologue_start,
+ &prologue_end))
{
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
if (sal.line == 0) /* no line info, use current PC */
- prologue_end = get_frame_pc (fi);
+ prologue_end = prev_pc;
else if (sal.end < prologue_end) /* next line begins after fn end */
prologue_end = sal.end; /* (probably means no prologue) */
}
else
- /* We're in the boondocks: allow for
- 16 pushes, an add, and "mv fp,sp". */
- prologue_end = prologue_start + 40;
-
- prologue_end = min (prologue_end, get_frame_pc (fi));
-
- /* Initialize the saved register map. When register H is copied to
- register L, we will put H in saved_reg[L]. */
- for (i = 0; i < 16; i++)
- saved_reg[i] = i;
-
- /* Search the prologue looking for instructions that set up the
- frame pointer, adjust the stack pointer, and save registers.
- Do this until all basic prolog instructions are found. */
-
- get_frame_extra_info (fi)->framesize = 0;
- for (current_pc = prologue_start;
- (current_pc < prologue_end) && ((findmask & 7) != 7);
- current_pc += 2)
- {
- unsigned short insn;
- int regno;
- int offset;
+ /* We're in the boondocks: we have no idea where the start of the
+ function is. */
+ return;
- insn = read_memory_unsigned_integer (current_pc, 2);
+ prologue_end = min (prologue_end, prev_pc);
- if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
- {
- int mask;
- findmask |= 1; /* push found */
- /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
- whether to save LR (R14). */
- mask = (insn & 0xff) | ((insn & 0x100) << 6);
-
- /* Calculate offsets of saved R0-R7 and LR. */
- for (regno = ARM_LR_REGNUM; regno >= 0; regno--)
- if (mask & (1 << regno))
- {
- get_frame_extra_info (fi)->framesize += 4;
- get_frame_saved_regs (fi)[saved_reg[regno]] =
- -(get_frame_extra_info (fi)->framesize);
- /* Reset saved register map. */
- saved_reg[regno] = regno;
- }
- }
- else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
- sub sp, #simm */
- {
- if ((findmask & 1) == 0) /* before push? */
- continue;
- else
- findmask |= 4; /* add/sub sp found */
-
- offset = (insn & 0x7f) << 2; /* get scaled offset */
- if (insn & 0x80) /* is it signed? (==subtracting) */
- {
- get_frame_extra_info (fi)->frameoffset += offset;
- offset = -offset;
- }
- get_frame_extra_info (fi)->framesize -= offset;
- }
- else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */
- {
- findmask |= 2; /* setting of r7 found */
- get_frame_extra_info (fi)->framereg = THUMB_FP_REGNUM;
- /* get scaled offset */
- get_frame_extra_info (fi)->frameoffset = (insn & 0xff) << 2;
- }
- else if (insn == 0x466f) /* mov r7, sp */
- {
- findmask |= 2; /* setting of r7 found */
- get_frame_extra_info (fi)->framereg = THUMB_FP_REGNUM;
- get_frame_extra_info (fi)->frameoffset = 0;
- saved_reg[THUMB_FP_REGNUM] = ARM_SP_REGNUM;
- }
- else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
- {
- int lo_reg = insn & 7; /* dest. register (r0-r7) */
- int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */
- saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */
- }
- else
- /* Something in the prolog that we don't care about or some
- instruction from outside the prolog scheduled here for
- optimization. */
- continue;
- }
+ thumb_analyze_prologue (gdbarch, prologue_start, prologue_end, cache);
}
/* This function decodes an ARM function prologue to determine:
*/
static void
-arm_scan_prologue (struct frame_info *fi)
+arm_scan_prologue (struct frame_info *this_frame,
+ struct arm_prologue_cache *cache)
{
- int regno, sp_offset, fp_offset;
- LONGEST return_value;
+ struct gdbarch *gdbarch = get_frame_arch (this_frame);
+ int regno;
CORE_ADDR prologue_start, prologue_end, current_pc;
+ CORE_ADDR prev_pc = get_frame_pc (this_frame);
+ CORE_ADDR block_addr = get_frame_address_in_block (this_frame);
+ pv_t regs[ARM_FPS_REGNUM];
+ struct pv_area *stack;
+ struct cleanup *back_to;
+ CORE_ADDR offset;
/* Assume there is no frame until proven otherwise. */
- get_frame_extra_info (fi)->framereg = ARM_SP_REGNUM;
- get_frame_extra_info (fi)->framesize = 0;
- get_frame_extra_info (fi)->frameoffset = 0;
+ cache->framereg = ARM_SP_REGNUM;
+ cache->framesize = 0;
/* Check for Thumb prologue. */
- if (arm_pc_is_thumb (get_frame_pc (fi)))
+ if (arm_frame_is_thumb (this_frame))
{
- thumb_scan_prologue (fi);
+ thumb_scan_prologue (gdbarch, prev_pc, block_addr, cache);
return;
}
/* Find the function prologue. If we can't find the function in
the symbol table, peek in the stack frame to find the PC. */
- if (find_pc_partial_function (get_frame_pc (fi), NULL, &prologue_start, &prologue_end))
+ if (find_pc_partial_function (block_addr, NULL, &prologue_start,
+ &prologue_end))
{
/* One way to find the end of the prologue (which works well
for unoptimized code) is to do the following:
struct symtab_and_line sal = find_pc_line (prologue_start, 0);
if (sal.line == 0)
- prologue_end = get_frame_pc (fi);
+ prologue_end = prev_pc;
else if (sal.end < prologue_end)
prologue_end = sal.end;
}
else
{
- /* Get address of the stmfd in the prologue of the callee;
- the saved PC is the address of the stmfd + 8. */
- if (!safe_read_memory_integer (get_frame_base (fi), 4, &return_value))
+ /* We have no symbol information. Our only option is to assume this
+ function has a standard stack frame and the normal frame register.
+ Then, we can find the value of our frame pointer on entrance to
+ the callee (or at the present moment if this is the innermost frame).
+ The value stored there should be the address of the stmfd + 8. */
+ CORE_ADDR frame_loc;
+ LONGEST return_value;
+
+ frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
+ if (!safe_read_memory_integer (frame_loc, 4, &return_value))
return;
else
{
- prologue_start = ADDR_BITS_REMOVE (return_value) - 8;
+ prologue_start = gdbarch_addr_bits_remove
+ (gdbarch, return_value) - 8;
prologue_end = prologue_start + 64; /* See above. */
}
}
+ if (prev_pc < prologue_end)
+ prologue_end = prev_pc;
+
/* Now search the prologue looking for instructions that set up the
frame pointer, adjust the stack pointer, and save registers.
in which case it is often (but not always) replaced by
"str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
- sp_offset = fp_offset = 0;
+ for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
+ regs[regno] = pv_register (regno, 0);
+ stack = make_pv_area (ARM_SP_REGNUM);
+ back_to = make_cleanup_free_pv_area (stack);
for (current_pc = prologue_start;
current_pc < prologue_end;
{
unsigned int insn = read_memory_unsigned_integer (current_pc, 4);
+ if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
+ insn = SWAP_INT (insn);
+
if (insn == 0xe1a0c00d) /* mov ip, sp */
{
+ regs[ARM_IP_REGNUM] = regs[ARM_SP_REGNUM];
+ continue;
+ }
+ else if ((insn & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
+ {
+ unsigned imm = insn & 0xff; /* immediate value */
+ unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
+ imm = (imm >> rot) | (imm << (32 - rot));
+ regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], imm);
+ continue;
+ }
+ else if ((insn & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
+ {
+ unsigned imm = insn & 0xff; /* immediate value */
+ unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
+ imm = (imm >> rot) | (imm << (32 - rot));
+ regs[ARM_IP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
continue;
}
else if (insn == 0xe52de004) /* str lr, [sp, #-4]! */
{
- /* Function is frameless: extra_info defaults OK? */
+ if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
+ break;
+ regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
+ pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[ARM_LR_REGNUM]);
continue;
}
else if ((insn & 0xffff0000) == 0xe92d0000)
{
int mask = insn & 0xffff;
+ if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
+ break;
+
/* Calculate offsets of saved registers. */
for (regno = ARM_PC_REGNUM; regno >= 0; regno--)
if (mask & (1 << regno))
{
- sp_offset -= 4;
- get_frame_saved_regs (fi)[regno] = sp_offset;
+ regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
+ pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
}
}
else if ((insn & 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
unsigned imm = insn & 0xff; /* immediate value */
unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
imm = (imm >> rot) | (imm << (32 - rot));
- fp_offset = -imm;
- get_frame_extra_info (fi)->framereg = ARM_FP_REGNUM;
+ regs[ARM_FP_REGNUM] = pv_add_constant (regs[ARM_IP_REGNUM], -imm);
}
else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
{
unsigned imm = insn & 0xff; /* immediate value */
unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */
imm = (imm >> rot) | (imm << (32 - rot));
- sp_offset -= imm;
+ regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -imm);
}
- else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
+ else if ((insn & 0xffff7fff) == 0xed6d0103 /* stfe f?, [sp, -#c]! */
+ && gdbarch_tdep (gdbarch)->have_fpa_registers)
{
- sp_offset -= 12;
+ if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
+ break;
+
+ regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
- get_frame_saved_regs (fi)[regno] = sp_offset;
+ pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
}
- else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
+ else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4, [sp!] */
+ && gdbarch_tdep (gdbarch)->have_fpa_registers)
{
int n_saved_fp_regs;
unsigned int fp_start_reg, fp_bound_reg;
+ if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
+ break;
+
if ((insn & 0x800) == 0x800) /* N0 is set */
{
if ((insn & 0x40000) == 0x40000) /* N1 is set */
fp_bound_reg = fp_start_reg + n_saved_fp_regs;
for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
{
- sp_offset -= 12;
- get_frame_saved_regs (fi)[fp_start_reg++] = sp_offset;
+ regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
+ pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
+ regs[fp_start_reg++]);
}
}
else if ((insn & 0xf0000000) != 0xe0000000)
continue;
}
- /* The frame size is just the negative of the offset (from the
- original SP) of the last thing thing we pushed on the stack.
- The frame offset is [new FP] - [new SP]. */
- get_frame_extra_info (fi)->framesize = -sp_offset;
- if (get_frame_extra_info (fi)->framereg == ARM_FP_REGNUM)
- get_frame_extra_info (fi)->frameoffset = fp_offset - sp_offset;
+ /* The frame size is just the distance from the frame register
+ to the original stack pointer. */
+ if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
+ {
+ /* Frame pointer is fp. */
+ cache->framereg = ARM_FP_REGNUM;
+ cache->framesize = -regs[ARM_FP_REGNUM].k;
+ }
+ else if (pv_is_register (regs[ARM_SP_REGNUM], ARM_SP_REGNUM))
+ {
+ /* Try the stack pointer... this is a bit desperate. */
+ cache->framereg = ARM_SP_REGNUM;
+ cache->framesize = -regs[ARM_SP_REGNUM].k;
+ }
else
- get_frame_extra_info (fi)->frameoffset = 0;
-}
-
-/* Find REGNUM on the stack. Otherwise, it's in an active register.
- One thing we might want to do here is to check REGNUM against the
- clobber mask, and somehow flag it as invalid if it isn't saved on
- the stack somewhere. This would provide a graceful failure mode
- when trying to get the value of caller-saves registers for an inner
- frame. */
-
-static CORE_ADDR
-arm_find_callers_reg (struct frame_info *fi, int regnum)
-{
- /* NOTE: cagney/2002-05-03: This function really shouldn't be
- needed. Instead the (still being written) register unwind
- function could be called directly. */
- for (; fi; fi = get_next_frame (fi))
{
- if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0))
- {
- return deprecated_read_register_dummy (get_frame_pc (fi),
- get_frame_base (fi), regnum);
- }
- else if (get_frame_saved_regs (fi)[regnum] != 0)
- {
- /* NOTE: cagney/2002-05-03: This would normally need to
- handle ARM_SP_REGNUM as a special case as, according to
- the frame.h comments, saved_regs[SP_REGNUM] contains the
- SP value not its address. It appears that the ARM isn't
- doing this though. */
- return read_memory_integer (get_frame_saved_regs (fi)[regnum],
- REGISTER_RAW_SIZE (regnum));
- }
+ /* We're just out of luck. We don't know where the frame is. */
+ cache->framereg = -1;
+ cache->framesize = 0;
}
- return read_register (regnum);
+
+ for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
+ if (pv_area_find_reg (stack, gdbarch, regno, &offset))
+ cache->saved_regs[regno].addr = offset;
+
+ do_cleanups (back_to);
}
-/* Function: frame_chain Given a GDB frame, determine the address of
- the calling function's frame. This will be used to create a new
- GDB frame struct, and then DEPRECATED_INIT_EXTRA_FRAME_INFO and
- DEPRECATED_INIT_FRAME_PC will be called for the new frame. For
- ARM, we save the frame size when we initialize the frame_info. */
-static CORE_ADDR
-arm_frame_chain (struct frame_info *fi)
+static struct arm_prologue_cache *
+arm_make_prologue_cache (struct frame_info *this_frame)
{
- CORE_ADDR caller_pc;
- int framereg = get_frame_extra_info (fi)->framereg;
+ int reg;
+ struct arm_prologue_cache *cache;
+ CORE_ADDR unwound_fp;
- if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0))
- /* A generic call dummy's frame is the same as caller's. */
- return get_frame_base (fi);
+ cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
+ cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
- if (get_frame_pc (fi) < LOWEST_PC)
- return 0;
+ arm_scan_prologue (this_frame, cache);
- /* If the caller is the startup code, we're at the end of the chain. */
- caller_pc = DEPRECATED_FRAME_SAVED_PC (fi);
+ unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg);
+ if (unwound_fp == 0)
+ return cache;
- /* If the caller is Thumb and the caller is ARM, or vice versa,
- the frame register of the caller is different from ours.
- So we must scan the prologue of the caller to determine its
- frame register number. */
- /* XXX Fixme, we should try to do this without creating a temporary
- caller_fi. */
- if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (get_frame_pc (fi)))
- {
- struct cleanup *old_chain = make_cleanup (null_cleanup, NULL);
- struct frame_info *caller_fi =
- deprecated_frame_xmalloc_with_cleanup (SIZEOF_FRAME_SAVED_REGS,
- sizeof (struct frame_extra_info));
-
- /* Now, scan the prologue and obtain the frame register. */
- deprecated_update_frame_pc_hack (caller_fi, caller_pc);
- arm_scan_prologue (caller_fi);
- framereg = get_frame_extra_info (caller_fi)->framereg;
-
- /* Deallocate the storage associated with the temporary frame
- created above. */
- do_cleanups (old_chain);
- }
+ cache->prev_sp = unwound_fp + cache->framesize;
- /* If the caller used a frame register, return its value.
- Otherwise, return the caller's stack pointer. */
- if (framereg == ARM_FP_REGNUM || framereg == THUMB_FP_REGNUM)
- return arm_find_callers_reg (fi, framereg);
- else
- return get_frame_base (fi) + get_frame_extra_info (fi)->framesize;
+ /* Calculate actual addresses of saved registers using offsets
+ determined by arm_scan_prologue. */
+ for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++)
+ if (trad_frame_addr_p (cache->saved_regs, reg))
+ cache->saved_regs[reg].addr += cache->prev_sp;
+
+ return cache;
}
-/* This function actually figures out the frame address for a given pc
- and sp. This is tricky because we sometimes don't use an explicit
- frame pointer, and the previous stack pointer isn't necessarily
- recorded on the stack. The only reliable way to get this info is
- to examine the prologue. FROMLEAF is a little confusing, it means
- this is the next frame up the chain AFTER a frameless function. If
- this is true, then the frame value for this frame is still in the
- fp register. */
+/* Our frame ID for a normal frame is the current function's starting PC
+ and the caller's SP when we were called. */
static void
-arm_init_extra_frame_info (int fromleaf, struct frame_info *fi)
+arm_prologue_this_id (struct frame_info *this_frame,
+ void **this_cache,
+ struct frame_id *this_id)
{
- int reg;
- CORE_ADDR sp;
+ struct arm_prologue_cache *cache;
+ struct frame_id id;
+ CORE_ADDR pc, func;
- if (get_frame_saved_regs (fi) == NULL)
- frame_saved_regs_zalloc (fi);
+ if (*this_cache == NULL)
+ *this_cache = arm_make_prologue_cache (this_frame);
+ cache = *this_cache;
- frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
+ /* This is meant to halt the backtrace at "_start". */
+ pc = get_frame_pc (this_frame);
+ if (pc <= gdbarch_tdep (get_frame_arch (this_frame))->lowest_pc)
+ return;
- get_frame_extra_info (fi)->framesize = 0;
- get_frame_extra_info (fi)->frameoffset = 0;
- get_frame_extra_info (fi)->framereg = 0;
+ /* If we've hit a wall, stop. */
+ if (cache->prev_sp == 0)
+ return;
- if (get_next_frame (fi))
- deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
+ func = get_frame_func (this_frame);
+ id = frame_id_build (cache->prev_sp, func);
+ *this_id = id;
+}
- memset (get_frame_saved_regs (fi), '\000', sizeof get_frame_saved_regs (fi));
+static struct value *
+arm_prologue_prev_register (struct frame_info *this_frame,
+ void **this_cache,
+ int prev_regnum)
+{
+ struct gdbarch *gdbarch = get_frame_arch (this_frame);
+ struct arm_prologue_cache *cache;
- /* Compute stack pointer for this frame. We use this value for both
- the sigtramp and call dummy cases. */
- if (!get_next_frame (fi))
- sp = read_sp();
- else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0))
- /* For generic dummy frames, pull the value direct from the frame.
- Having an unwind function to do this would be nice. */
- sp = deprecated_read_register_dummy (get_frame_pc (get_next_frame (fi)),
- get_frame_base (get_next_frame (fi)),
- ARM_SP_REGNUM);
- else
- sp = (get_frame_base (get_next_frame (fi))
- - get_frame_extra_info (get_next_frame (fi))->frameoffset
- + get_frame_extra_info (get_next_frame (fi))->framesize);
-
- /* Determine whether or not we're in a sigtramp frame.
- Unfortunately, it isn't sufficient to test (get_frame_type (fi)
- == SIGTRAMP_FRAME) because this value is sometimes set after
- invoking DEPRECATED_INIT_EXTRA_FRAME_INFO. So we test *both*
- (get_frame_type (fi) == SIGTRAMP_FRAME) and PC_IN_SIGTRAMP to
- determine if we need to use the sigcontext addresses for the
- saved registers.
-
- Note: If an ARM PC_IN_SIGTRAMP method ever needs to compare
- against the name of the function, the code below will have to be
- changed to first fetch the name of the function and then pass
- this name to PC_IN_SIGTRAMP. */
-
- /* FIXME: cagney/2002-11-18: This problem will go away once
- frame.c:get_prev_frame() is modified to set the frame's type
- before calling functions like this. */
-
- if (SIGCONTEXT_REGISTER_ADDRESS_P ()
- && ((get_frame_type (fi) == SIGTRAMP_FRAME) || PC_IN_SIGTRAMP (get_frame_pc (fi), (char *)0)))
- {
- for (reg = 0; reg < NUM_REGS; reg++)
- get_frame_saved_regs (fi)[reg] = SIGCONTEXT_REGISTER_ADDRESS (sp, get_frame_pc (fi), reg);
+ if (*this_cache == NULL)
+ *this_cache = arm_make_prologue_cache (this_frame);
+ cache = *this_cache;
- /* FIXME: What about thumb mode? */
- get_frame_extra_info (fi)->framereg = ARM_SP_REGNUM;
- deprecated_update_frame_base_hack (fi, read_memory_integer (get_frame_saved_regs (fi)[get_frame_extra_info (fi)->framereg], REGISTER_RAW_SIZE (get_frame_extra_info (fi)->framereg)));
- get_frame_extra_info (fi)->framesize = 0;
- get_frame_extra_info (fi)->frameoffset = 0;
+ /* If we are asked to unwind the PC, then we need to return the LR
+ instead. The prologue may save PC, but it will point into this
+ frame's prologue, not the next frame's resume location. Also
+ strip the saved T bit. A valid LR may have the low bit set, but
+ a valid PC never does. */
+ if (prev_regnum == ARM_PC_REGNUM)
+ {
+ CORE_ADDR lr;
+ lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
+ return frame_unwind_got_constant (this_frame, prev_regnum,
+ arm_addr_bits_remove (gdbarch, lr));
}
- else
+
+ /* SP is generally not saved to the stack, but this frame is
+ identified by the next frame's stack pointer at the time of the call.
+ The value was already reconstructed into PREV_SP. */
+ if (prev_regnum == ARM_SP_REGNUM)
+ return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
+
+ /* The CPSR may have been changed by the call instruction and by the
+ called function. The only bit we can reconstruct is the T bit,
+ by checking the low bit of LR as of the call. This is a reliable
+ indicator of Thumb-ness except for some ARM v4T pre-interworking
+ Thumb code, which could get away with a clear low bit as long as
+ the called function did not use bx. Guess that all other
+ bits are unchanged; the condition flags are presumably lost,
+ but the processor status is likely valid. */
+ if (prev_regnum == ARM_PS_REGNUM)
{
- arm_scan_prologue (fi);
-
- if (!get_next_frame (fi))
- /* This is the innermost frame? */
- deprecated_update_frame_base_hack (fi, read_register (get_frame_extra_info (fi)->framereg));
- else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0))
- /* Next inner most frame is a dummy, just grab its frame.
- Dummy frames always have the same FP as their caller. */
- deprecated_update_frame_base_hack (fi, get_frame_base (get_next_frame (fi)));
- else if (get_frame_extra_info (fi)->framereg == ARM_FP_REGNUM
- || get_frame_extra_info (fi)->framereg == THUMB_FP_REGNUM)
- {
- /* not the innermost frame */
- /* If we have an FP, the callee saved it. */
- if (get_frame_saved_regs (get_next_frame (fi))[get_frame_extra_info (fi)->framereg] != 0)
- deprecated_update_frame_base_hack (fi, read_memory_integer (get_frame_saved_regs (get_next_frame (fi))[get_frame_extra_info (fi)->framereg], 4));
- else if (fromleaf)
- /* If we were called by a frameless fn. then our frame is
- still in the frame pointer register on the board... */
- deprecated_update_frame_base_hack (fi, read_fp ());
- }
+ CORE_ADDR lr, cpsr;
- /* Calculate actual addresses of saved registers using offsets
- determined by arm_scan_prologue. */
- for (reg = 0; reg < NUM_REGS; reg++)
- if (get_frame_saved_regs (fi)[reg] != 0)
- get_frame_saved_regs (fi)[reg]
- += (get_frame_base (fi)
- + get_frame_extra_info (fi)->framesize
- - get_frame_extra_info (fi)->frameoffset);
+ cpsr = get_frame_register_unsigned (this_frame, prev_regnum);
+ lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
+ if (IS_THUMB_ADDR (lr))
+ cpsr |= CPSR_T;
+ else
+ cpsr &= ~CPSR_T;
+ return frame_unwind_got_constant (this_frame, prev_regnum, cpsr);
}
-}
+ return trad_frame_get_prev_register (this_frame, cache->saved_regs,
+ prev_regnum);
+}
-/* Find the caller of this frame. We do this by seeing if ARM_LR_REGNUM
- is saved in the stack anywhere, otherwise we get it from the
- registers.
-
- The old definition of this function was a macro:
- #define FRAME_SAVED_PC(FRAME) \
- ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
+struct frame_unwind arm_prologue_unwind = {
+ NORMAL_FRAME,
+ arm_prologue_this_id,
+ arm_prologue_prev_register,
+ NULL,
+ default_frame_sniffer
+};
-static CORE_ADDR
-arm_frame_saved_pc (struct frame_info *fi)
+static struct arm_prologue_cache *
+arm_make_stub_cache (struct frame_info *this_frame)
{
- /* If a dummy frame, pull the PC out of the frame's register buffer. */
- if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), 0, 0))
- return deprecated_read_register_dummy (get_frame_pc (fi),
- get_frame_base (fi), ARM_PC_REGNUM);
+ int reg;
+ struct arm_prologue_cache *cache;
+ CORE_ADDR unwound_fp;
- if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi),
- (get_frame_base (fi)
- - get_frame_extra_info (fi)->frameoffset),
- get_frame_base (fi)))
- {
- return read_memory_integer (get_frame_saved_regs (fi)[ARM_PC_REGNUM],
- REGISTER_RAW_SIZE (ARM_PC_REGNUM));
- }
- else
- {
- CORE_ADDR pc = arm_find_callers_reg (fi, ARM_LR_REGNUM);
- return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc;
- }
-}
+ cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
+ cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
-/* Return the frame address. On ARM, it is R11; on Thumb it is R7.
- Examine the Program Status Register to decide which state we're in. */
+ cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
-static CORE_ADDR
-arm_read_fp (void)
-{
- if (read_register (ARM_PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */
- return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */
- else
- return read_register (ARM_FP_REGNUM); /* R11 if ARM */
+ return cache;
}
-/* Store into a struct frame_saved_regs the addresses of the saved
- registers of frame described by FRAME_INFO. This includes special
- registers such as PC and FP saved in special ways in the stack
- frame. SP is even more special: the address we return for it IS
- the sp for the next frame. */
+/* Our frame ID for a stub frame is the current SP and LR. */
static void
-arm_frame_init_saved_regs (struct frame_info *fip)
+arm_stub_this_id (struct frame_info *this_frame,
+ void **this_cache,
+ struct frame_id *this_id)
{
+ struct arm_prologue_cache *cache;
- if (get_frame_saved_regs (fip))
- return;
+ if (*this_cache == NULL)
+ *this_cache = arm_make_stub_cache (this_frame);
+ cache = *this_cache;
- arm_init_extra_frame_info (0, fip);
+ *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
}
-/* Set the return address for a generic dummy frame. ARM uses the
- entry point. */
-
-static CORE_ADDR
-arm_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
+static int
+arm_stub_unwind_sniffer (const struct frame_unwind *self,
+ struct frame_info *this_frame,
+ void **this_prologue_cache)
{
- write_register (ARM_LR_REGNUM, CALL_DUMMY_ADDRESS ());
- return sp;
+ CORE_ADDR addr_in_block;
+ char dummy[4];
+
+ addr_in_block = get_frame_address_in_block (this_frame);
+ if (in_plt_section (addr_in_block, NULL)
+ || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0)
+ return 1;
+
+ return 0;
}
-/* Push an empty stack frame, to record the current PC, etc. */
+struct frame_unwind arm_stub_unwind = {
+ NORMAL_FRAME,
+ arm_stub_this_id,
+ arm_prologue_prev_register,
+ NULL,
+ arm_stub_unwind_sniffer
+};
-static void
-arm_push_dummy_frame (void)
+static CORE_ADDR
+arm_normal_frame_base (struct frame_info *this_frame, void **this_cache)
{
- CORE_ADDR old_sp = read_register (ARM_SP_REGNUM);
- CORE_ADDR sp = old_sp;
- CORE_ADDR fp, prologue_start;
- int regnum;
+ struct arm_prologue_cache *cache;
- /* Push the two dummy prologue instructions in reverse order,
- so that they'll be in the correct low-to-high order in memory. */
- /* sub fp, ip, #4 */
- sp = push_word (sp, 0xe24cb004);
- /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
- prologue_start = sp = push_word (sp, 0xe92ddfff);
+ if (*this_cache == NULL)
+ *this_cache = arm_make_prologue_cache (this_frame);
+ cache = *this_cache;
- /* Push a pointer to the dummy prologue + 12, because when stm
- instruction stores the PC, it stores the address of the stm
- instruction itself plus 12. */
- fp = sp = push_word (sp, prologue_start + 12);
+ return cache->prev_sp - cache->framesize;
+}
- /* Push the processor status. */
- sp = push_word (sp, read_register (ARM_PS_REGNUM));
+struct frame_base arm_normal_base = {
+ &arm_prologue_unwind,
+ arm_normal_frame_base,
+ arm_normal_frame_base,
+ arm_normal_frame_base
+};
- /* Push all 16 registers starting with r15. */
- for (regnum = ARM_PC_REGNUM; regnum >= 0; regnum--)
- sp = push_word (sp, read_register (regnum));
+/* Assuming THIS_FRAME is a dummy, return the frame ID of that
+ dummy frame. The frame ID's base needs to match the TOS value
+ saved by save_dummy_frame_tos() and returned from
+ arm_push_dummy_call, and the PC needs to match the dummy frame's
+ breakpoint. */
- /* Update fp (for both Thumb and ARM) and sp. */
- write_register (ARM_FP_REGNUM, fp);
- write_register (THUMB_FP_REGNUM, fp);
- write_register (ARM_SP_REGNUM, sp);
+static struct frame_id
+arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
+{
+ return frame_id_build (get_frame_register_unsigned (this_frame, ARM_SP_REGNUM),
+ get_frame_pc (this_frame));
}
-/* CALL_DUMMY_WORDS:
- This sequence of words is the instructions
-
- mov lr,pc
- mov pc,r4
- illegal
+/* Given THIS_FRAME, find the previous frame's resume PC (which will
+ be used to construct the previous frame's ID, after looking up the
+ containing function). */
- Note this is 12 bytes. */
+static CORE_ADDR
+arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
+{
+ CORE_ADDR pc;
+ pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
+ return arm_addr_bits_remove (gdbarch, pc);
+}
-static LONGEST arm_call_dummy_words[] =
+static CORE_ADDR
+arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
{
- 0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe
-};
+ return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
+}
-/* Adjust the call_dummy_breakpoint_offset for the bp_call_dummy
- breakpoint to the proper address in the call dummy, so that
- `finish' after a stop in a call dummy works.
+static struct value *
+arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
+ int regnum)
+{
+ struct gdbarch * gdbarch = get_frame_arch (this_frame);
+ CORE_ADDR lr, cpsr;
- FIXME rearnsha 2002-02018: Tweeking current_gdbarch is not an
- optimal solution, but the call to arm_fix_call_dummy is immediately
- followed by a call to run_stack_dummy, which is the only function
- where call_dummy_breakpoint_offset is actually used. */
+ switch (regnum)
+ {
+ case ARM_PC_REGNUM:
+ /* The PC is normally copied from the return column, which
+ describes saves of LR. However, that version may have an
+ extra bit set to indicate Thumb state. The bit is not
+ part of the PC. */
+ lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
+ return frame_unwind_got_constant (this_frame, regnum,
+ arm_addr_bits_remove (gdbarch, lr));
+
+ case ARM_PS_REGNUM:
+ /* Reconstruct the T bit; see arm_prologue_prev_register for details. */
+ cpsr = get_frame_register_unsigned (this_frame, regnum);
+ lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM);
+ if (IS_THUMB_ADDR (lr))
+ cpsr |= CPSR_T;
+ else
+ cpsr &= ~CPSR_T;
+ return frame_unwind_got_constant (this_frame, regnum, cpsr);
+ default:
+ internal_error (__FILE__, __LINE__,
+ _("Unexpected register %d"), regnum);
+ }
+}
static void
-arm_set_call_dummy_breakpoint_offset (void)
+arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
+ struct dwarf2_frame_state_reg *reg,
+ struct frame_info *this_frame)
{
- if (caller_is_thumb)
- set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 4);
- else
- set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch, 8);
+ switch (regnum)
+ {
+ case ARM_PC_REGNUM:
+ case ARM_PS_REGNUM:
+ reg->how = DWARF2_FRAME_REG_FN;
+ reg->loc.fn = arm_dwarf2_prev_register;
+ break;
+ case ARM_SP_REGNUM:
+ reg->how = DWARF2_FRAME_REG_CFA;
+ break;
+ }
}
-/* Fix up the call dummy, based on whether the processor is currently
- in Thumb or ARM mode, and whether the target function is Thumb or
- ARM. There are three different situations requiring three
- different dummies:
+/* When arguments must be pushed onto the stack, they go on in reverse
+ order. The code below implements a FILO (stack) to do this. */
- * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
- been copied into the dummy parameter to this function.
- * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
- "mov pc,r4" instruction patched to be a "bx r4" instead.
- * Thumb calling anything: uses the Thumb dummy defined below, which
- works for calling both ARM and Thumb functions.
+struct stack_item
+{
+ int len;
+ struct stack_item *prev;
+ void *data;
+};
- All three call dummies expect to receive the target function
- address in R4, with the low bit set if it's a Thumb function. */
+static struct stack_item *
+push_stack_item (struct stack_item *prev, void *contents, int len)
+{
+ struct stack_item *si;
+ si = xmalloc (sizeof (struct stack_item));
+ si->data = xmalloc (len);
+ si->len = len;
+ si->prev = prev;
+ memcpy (si->data, contents, len);
+ return si;
+}
-static void
-arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
- struct value **args, struct type *type, int gcc_p)
+static struct stack_item *
+pop_stack_item (struct stack_item *si)
{
- static short thumb_dummy[4] =
- {
- 0xf000, 0xf801, /* bl label */
- 0xdf18, /* swi 24 */
- 0x4720, /* label: bx r4 */
- };
- static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */
-
- /* Set flag indicating whether the current PC is in a Thumb function. */
- caller_is_thumb = arm_pc_is_thumb (read_pc ());
- arm_set_call_dummy_breakpoint_offset ();
-
- /* If the target function is Thumb, set the low bit of the function
- address. And if the CPU is currently in ARM mode, patch the
- second instruction of call dummy to use a BX instruction to
- switch to Thumb mode. */
- target_is_thumb = arm_pc_is_thumb (fun);
- if (target_is_thumb)
- {
- fun |= 1;
- if (!caller_is_thumb)
- store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4);
- }
+ struct stack_item *dead = si;
+ si = si->prev;
+ xfree (dead->data);
+ xfree (dead);
+ return si;
+}
- /* If the CPU is currently in Thumb mode, use the Thumb call dummy
- instead of the ARM one that's already been copied. This will
- work for both Thumb and ARM target functions. */
- if (caller_is_thumb)
- {
- int i;
- char *p = dummy;
- int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]);
- for (i = 0; i < len; i++)
+/* Return the alignment (in bytes) of the given type. */
+
+static int
+arm_type_align (struct type *t)
+{
+ int n;
+ int align;
+ int falign;
+
+ t = check_typedef (t);
+ switch (TYPE_CODE (t))
+ {
+ default:
+ /* Should never happen. */
+ internal_error (__FILE__, __LINE__, _("unknown type alignment"));
+ return 4;
+
+ case TYPE_CODE_PTR:
+ case TYPE_CODE_ENUM:
+ case TYPE_CODE_INT:
+ case TYPE_CODE_FLT:
+ case TYPE_CODE_SET:
+ case TYPE_CODE_RANGE:
+ case TYPE_CODE_BITSTRING:
+ case TYPE_CODE_REF:
+ case TYPE_CODE_CHAR:
+ case TYPE_CODE_BOOL:
+ return TYPE_LENGTH (t);
+
+ case TYPE_CODE_ARRAY:
+ case TYPE_CODE_COMPLEX:
+ /* TODO: What about vector types? */
+ return arm_type_align (TYPE_TARGET_TYPE (t));
+
+ case TYPE_CODE_STRUCT:
+ case TYPE_CODE_UNION:
+ align = 1;
+ for (n = 0; n < TYPE_NFIELDS (t); n++)
{
- store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]);
- p += sizeof (thumb_dummy[0]);
+ falign = arm_type_align (TYPE_FIELD_TYPE (t, n));
+ if (falign > align)
+ align = falign;
}
+ return align;
}
-
- /* Put the target address in r4; the call dummy will copy this to
- the PC. */
- write_register (4, fun);
}
-/* Note: ScottB
-
- This function does not support passing parameters using the FPA
- variant of the APCS. It passes any floating point arguments in the
- general registers and/or on the stack. */
+/* We currently only support passing parameters in integer registers. This
+ conforms with GCC's default model. Several other variants exist and
+ we should probably support some of them based on the selected ABI. */
static CORE_ADDR
-arm_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
- int struct_return, CORE_ADDR struct_addr)
+arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
+ struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
+ struct value **args, CORE_ADDR sp, int struct_return,
+ CORE_ADDR struct_addr)
{
- CORE_ADDR fp;
int argnum;
int argreg;
int nstack;
- int simd_argreg;
- int second_pass;
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ struct stack_item *si = NULL;
+
+ /* Set the return address. For the ARM, the return breakpoint is
+ always at BP_ADDR. */
+ /* XXX Fix for Thumb. */
+ regcache_cooked_write_unsigned (regcache, ARM_LR_REGNUM, bp_addr);
/* Walk through the list of args and determine how large a temporary
stack is required. Need to take care here as structs may be
- passed on the stack, and we have to to push them. On the second
- pass, do the store. */
+ passed on the stack, and we have to to push them. */
nstack = 0;
- fp = sp;
- for (second_pass = 0; second_pass < 2; second_pass++)
+
+ argreg = ARM_A1_REGNUM;
+ nstack = 0;
+
+ /* The struct_return pointer occupies the first parameter
+ passing register. */
+ if (struct_return)
{
- /* Compute the FP using the information computed during the
- first pass. */
- if (second_pass)
- fp = sp - nstack;
-
- simd_argreg = 0;
- argreg = ARM_A1_REGNUM;
- nstack = 0;
-
- /* The struct_return pointer occupies the first parameter
- passing register. */
- if (struct_return)
+ if (arm_debug)
+ fprintf_unfiltered (gdb_stdlog, "struct return in %s = 0x%s\n",
+ gdbarch_register_name (gdbarch, argreg),
+ paddr (struct_addr));
+ regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
+ argreg++;
+ }
+
+ for (argnum = 0; argnum < nargs; argnum++)
+ {
+ int len;
+ struct type *arg_type;
+ struct type *target_type;
+ enum type_code typecode;
+ bfd_byte *val;
+ int align;
+
+ arg_type = check_typedef (value_type (args[argnum]));
+ len = TYPE_LENGTH (arg_type);
+ target_type = TYPE_TARGET_TYPE (arg_type);
+ typecode = TYPE_CODE (arg_type);
+ val = value_contents_writeable (args[argnum]);
+
+ align = arm_type_align (arg_type);
+ /* Round alignment up to a whole number of words. */
+ align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
+ /* Different ABIs have different maximum alignments. */
+ if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
{
- if (second_pass)
+ /* The APCS ABI only requires word alignment. */
+ align = INT_REGISTER_SIZE;
+ }
+ else
+ {
+ /* The AAPCS requires at most doubleword alignment. */
+ if (align > INT_REGISTER_SIZE * 2)
+ align = INT_REGISTER_SIZE * 2;
+ }
+
+ /* Push stack padding for dowubleword alignment. */
+ if (nstack & (align - 1))
+ {
+ si = push_stack_item (si, val, INT_REGISTER_SIZE);
+ nstack += INT_REGISTER_SIZE;
+ }
+
+ /* Doubleword aligned quantities must go in even register pairs. */
+ if (argreg <= ARM_LAST_ARG_REGNUM
+ && align > INT_REGISTER_SIZE
+ && argreg & 1)
+ argreg++;
+
+ /* If the argument is a pointer to a function, and it is a
+ Thumb function, create a LOCAL copy of the value and set
+ the THUMB bit in it. */
+ if (TYPE_CODE_PTR == typecode
+ && target_type != NULL
+ && TYPE_CODE_FUNC == TYPE_CODE (target_type))
+ {
+ CORE_ADDR regval = extract_unsigned_integer (val, len);
+ if (arm_pc_is_thumb (regval))
{
- if (arm_debug)
- fprintf_unfiltered (gdb_stdlog,
- "struct return in %s = 0x%s\n",
- REGISTER_NAME (argreg),
- paddr (struct_addr));
- write_register (argreg, struct_addr);
+ val = alloca (len);
+ store_unsigned_integer (val, len, MAKE_THUMB_ADDR (regval));
}
- argreg++;
}
- for (argnum = 0; argnum < nargs; argnum++)
+ /* Copy the argument to general registers or the stack in
+ register-sized pieces. Large arguments are split between
+ registers and stack. */
+ while (len > 0)
{
- int len;
- struct type *arg_type;
- struct type *target_type;
- enum type_code typecode;
- char *val;
-
- arg_type = check_typedef (VALUE_TYPE (args[argnum]));
- len = TYPE_LENGTH (arg_type);
- target_type = TYPE_TARGET_TYPE (arg_type);
- typecode = TYPE_CODE (arg_type);
- val = VALUE_CONTENTS (args[argnum]);
-
- /* If the argument is a pointer to a function, and it is a
- Thumb function, create a LOCAL copy of the value and set
- the THUMB bit in it. */
- if (second_pass
- && TYPE_CODE_PTR == typecode
- && target_type != NULL
- && TYPE_CODE_FUNC == TYPE_CODE (target_type))
+ int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
+
+ if (argreg <= ARM_LAST_ARG_REGNUM)
{
- CORE_ADDR regval = extract_address (val, len);
- if (arm_pc_is_thumb (regval))
- {
- val = alloca (len);
- store_address (val, len, MAKE_THUMB_ADDR (regval));
- }
+ /* The argument is being passed in a general purpose
+ register. */
+ CORE_ADDR regval = extract_unsigned_integer (val, partial_len);
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+ regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
+ if (arm_debug)
+ fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
+ argnum,
+ gdbarch_register_name
+ (gdbarch, argreg),
+ phex (regval, INT_REGISTER_SIZE));
+ regcache_cooked_write_unsigned (regcache, argreg, regval);
+ argreg++;
}
-
- /* Copy the argument to general registers or the stack in
- register-sized pieces. Large arguments are split between
- registers and stack. */
- while (len > 0)
+ else
{
- int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE;
-
- if (argreg <= ARM_LAST_ARG_REGNUM)
- {
- /* The argument is being passed in a general purpose
- register. */
- if (second_pass)
- {
- CORE_ADDR regval = extract_address (val,
- partial_len);
- if (arm_debug)
- fprintf_unfiltered (gdb_stdlog,
- "arg %d in %s = 0x%s\n",
- argnum,
- REGISTER_NAME (argreg),
- phex (regval, REGISTER_SIZE));
- write_register (argreg, regval);
- }
- argreg++;
- }
- else
- {
- if (second_pass)
- {
- /* Push the arguments onto the stack. */
- if (arm_debug)
- fprintf_unfiltered (gdb_stdlog,
- "arg %d @ 0x%s + %d\n",
- argnum, paddr (fp), nstack);
- write_memory (fp + nstack, val, REGISTER_SIZE);
- }
- nstack += REGISTER_SIZE;
- }
-
- len -= partial_len;
- val += partial_len;
+ /* Push the arguments onto the stack. */
+ if (arm_debug)
+ fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
+ argnum, nstack);
+ si = push_stack_item (si, val, INT_REGISTER_SIZE);
+ nstack += INT_REGISTER_SIZE;
}
-
+
+ len -= partial_len;
+ val += partial_len;
}
}
+ /* If we have an odd number of words to push, then decrement the stack
+ by one word now, so first stack argument will be dword aligned. */
+ if (nstack & 4)
+ sp -= 4;
- /* Return the bottom of the argument list (pointed to by fp). */
- return fp;
-}
-
-/* Pop the current frame. So long as the frame info has been
- initialized properly (see arm_init_extra_frame_info), this code
- works for dummy frames as well as regular frames. I.e, there's no
- need to have a special case for dummy frames. */
-static void
-arm_pop_frame (void)
-{
- int regnum;
- struct frame_info *frame = get_current_frame ();
- CORE_ADDR old_SP = (get_frame_base (frame)
- - get_frame_extra_info (frame)->frameoffset
- + get_frame_extra_info (frame)->framesize);
-
- if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
- get_frame_base (frame),
- get_frame_base (frame)))
+ while (si)
{
- generic_pop_dummy_frame ();
- flush_cached_frames ();
- return;
+ sp -= si->len;
+ write_memory (sp, si->data, si->len);
+ si = pop_stack_item (si);
}
- for (regnum = 0; regnum < NUM_REGS; regnum++)
- if (get_frame_saved_regs (frame)[regnum] != 0)
- write_register (regnum,
- read_memory_integer (get_frame_saved_regs (frame)[regnum],
- REGISTER_RAW_SIZE (regnum)));
+ /* Finally, update teh SP register. */
+ regcache_cooked_write_unsigned (regcache, ARM_SP_REGNUM, sp);
+
+ return sp;
+}
- write_register (ARM_PC_REGNUM, DEPRECATED_FRAME_SAVED_PC (frame));
- write_register (ARM_SP_REGNUM, old_SP);
- flush_cached_frames ();
+/* Always align the frame to an 8-byte boundary. This is required on
+ some platforms and harmless on the rest. */
+
+static CORE_ADDR
+arm_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
+{
+ /* Align the stack to eight bytes. */
+ return sp & ~ (CORE_ADDR) 7;
}
static void
arm_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
struct frame_info *frame, const char *args)
{
- register unsigned long status = read_register (ARM_FPS_REGNUM);
+ unsigned long status = get_frame_register_unsigned (frame, ARM_FPS_REGNUM);
int type;
type = (status >> 24) & 127;
- printf ("%s FPU type %d\n",
- (status & (1 << 31)) ? "Hardware" : "Software",
- type);
- fputs ("mask: ", stdout);
+ if (status & (1 << 31))
+ printf (_("Hardware FPU type %d\n"), type);
+ else
+ printf (_("Software FPU type %d\n"), type);
+ /* i18n: [floating point unit] mask */
+ fputs (_("mask: "), stdout);
print_fpu_flags (status >> 16);
- fputs ("flags: ", stdout);
+ /* i18n: [floating point unit] flags */
+ fputs (_("flags: "), stdout);
print_fpu_flags (status);
}
register N. */
static struct type *
-arm_register_type (int regnum)
+arm_register_type (struct gdbarch *gdbarch, int regnum)
{
if (regnum >= ARM_F0_REGNUM && regnum < ARM_F0_REGNUM + NUM_FREGS)
- {
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
- return builtin_type_arm_ext_big;
- else
- return builtin_type_arm_ext_littlebyte_bigword;
- }
+ return builtin_type_arm_ext;
+ else if (regnum == ARM_SP_REGNUM)
+ return builtin_type (gdbarch)->builtin_data_ptr;
+ else if (regnum == ARM_PC_REGNUM)
+ return builtin_type (gdbarch)->builtin_func_ptr;
+ else if (regnum >= ARRAY_SIZE (arm_register_names))
+ /* These registers are only supported on targets which supply
+ an XML description. */
+ return builtin_type_int0;
else
- return builtin_type_int32;
+ return builtin_type_uint32;
}
-/* Index within `registers' of the first byte of the space for
- register N. */
+/* Map a DWARF register REGNUM onto the appropriate GDB register
+ number. */
static int
-arm_register_byte (int regnum)
+arm_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
{
- if (regnum < ARM_F0_REGNUM)
- return regnum * INT_REGISTER_RAW_SIZE;
- else if (regnum < ARM_PS_REGNUM)
- return (NUM_GREGS * INT_REGISTER_RAW_SIZE
- + (regnum - ARM_F0_REGNUM) * FP_REGISTER_RAW_SIZE);
- else
- return (NUM_GREGS * INT_REGISTER_RAW_SIZE
- + NUM_FREGS * FP_REGISTER_RAW_SIZE
- + (regnum - ARM_FPS_REGNUM) * STATUS_REGISTER_SIZE);
-}
+ /* Core integer regs. */
+ if (reg >= 0 && reg <= 15)
+ return reg;
-/* Number of bytes of storage in the actual machine representation for
- register N. All registers are 4 bytes, except fp0 - fp7, which are
- 12 bytes in length. */
+ /* Legacy FPA encoding. These were once used in a way which
+ overlapped with VFP register numbering, so their use is
+ discouraged, but GDB doesn't support the ARM toolchain
+ which used them for VFP. */
+ if (reg >= 16 && reg <= 23)
+ return ARM_F0_REGNUM + reg - 16;
-static int
-arm_register_raw_size (int regnum)
-{
- if (regnum < ARM_F0_REGNUM)
- return INT_REGISTER_RAW_SIZE;
- else if (regnum < ARM_FPS_REGNUM)
- return FP_REGISTER_RAW_SIZE;
- else
- return STATUS_REGISTER_SIZE;
-}
+ /* New assignments for the FPA registers. */
+ if (reg >= 96 && reg <= 103)
+ return ARM_F0_REGNUM + reg - 96;
-/* Number of bytes of storage in a program's representation
- for register N. */
-static int
-arm_register_virtual_size (int regnum)
-{
- if (regnum < ARM_F0_REGNUM)
- return INT_REGISTER_VIRTUAL_SIZE;
- else if (regnum < ARM_FPS_REGNUM)
- return FP_REGISTER_VIRTUAL_SIZE;
- else
- return STATUS_REGISTER_SIZE;
+ /* WMMX register assignments. */
+ if (reg >= 104 && reg <= 111)
+ return ARM_WCGR0_REGNUM + reg - 104;
+
+ if (reg >= 112 && reg <= 127)
+ return ARM_WR0_REGNUM + reg - 112;
+
+ if (reg >= 192 && reg <= 199)
+ return ARM_WC0_REGNUM + reg - 192;
+
+ return -1;
}
/* Map GDB internal REGNUM onto the Arm simulator register numbers. */
static int
-arm_register_sim_regno (int regnum)
+arm_register_sim_regno (struct gdbarch *gdbarch, int regnum)
{
int reg = regnum;
- gdb_assert (reg >= 0 && reg < NUM_REGS);
+ gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch));
+
+ if (regnum >= ARM_WR0_REGNUM && regnum <= ARM_WR15_REGNUM)
+ return regnum - ARM_WR0_REGNUM + SIM_ARM_IWMMXT_COP0R0_REGNUM;
+
+ if (regnum >= ARM_WC0_REGNUM && regnum <= ARM_WC7_REGNUM)
+ return regnum - ARM_WC0_REGNUM + SIM_ARM_IWMMXT_COP1R0_REGNUM;
+
+ if (regnum >= ARM_WCGR0_REGNUM && regnum <= ARM_WCGR7_REGNUM)
+ return regnum - ARM_WCGR0_REGNUM + SIM_ARM_IWMMXT_COP1R8_REGNUM;
if (reg < NUM_GREGS)
return SIM_ARM_R0_REGNUM + reg;
return SIM_ARM_FPS_REGNUM + reg;
reg -= NUM_SREGS;
- internal_error (__FILE__, __LINE__, "Bad REGNUM %d", regnum);
+ internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
}
/* NOTE: cagney/2001-08-20: Both convert_from_extended() and
static void
convert_from_extended (const struct floatformat *fmt, const void *ptr,
- void *dbl)
+ void *dbl, int endianess)
{
DOUBLEST d;
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+
+ if (endianess == BFD_ENDIAN_BIG)
floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
else
floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
}
static void
-convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr)
+convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
+ int endianess)
{
DOUBLEST d;
+
floatformat_to_doublest (fmt, ptr, &d);
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (endianess == BFD_ENDIAN_BIG)
floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
else
floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
#define ARM_PC_32 1
static unsigned long
-shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val,
- unsigned long status_reg)
+shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry,
+ unsigned long pc_val, unsigned long status_reg)
{
unsigned long res, shift;
int rm = bits (inst, 0, 3);
if (bit (inst, 4))
{
int rs = bits (inst, 8, 11);
- shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
+ shift = (rs == 15 ? pc_val + 8
+ : get_frame_register_unsigned (frame, rs)) & 0xFF;
}
else
shift = bits (inst, 7, 11);
res = (rm == 15
? ((pc_val | (ARM_PC_32 ? 0 : status_reg))
+ (bit (inst, 4) ? 12 : 8))
- : read_register (rm));
+ : get_frame_register_unsigned (frame, rm));
switch (shifttype)
{
return nbits;
}
-CORE_ADDR
-thumb_get_next_pc (CORE_ADDR pc)
+static CORE_ADDR
+thumb_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
{
+ struct gdbarch *gdbarch = get_frame_arch (frame);
unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */
- unsigned short inst1 = read_memory_integer (pc, 2);
+ unsigned short inst1 = read_memory_unsigned_integer (pc, 2);
CORE_ADDR nextpc = pc + 2; /* default is next instruction */
unsigned long offset;
+ if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
+ inst1 = SWAP_SHORT (inst1);
+
if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */
{
CORE_ADDR sp;
/* Fetch the saved PC from the stack. It's stored above
all of the other registers. */
- offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE;
- sp = read_register (ARM_SP_REGNUM);
- nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4);
- nextpc = ADDR_BITS_REMOVE (nextpc);
+ offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
+ sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM);
+ nextpc = (CORE_ADDR) read_memory_unsigned_integer (sp + offset, 4);
+ nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
if (nextpc == pc)
- error ("Infinite loop detected");
+ error (_("Infinite loop detected"));
}
else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */
{
- unsigned long status = read_register (ARM_PS_REGNUM);
+ unsigned long status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
unsigned long cond = bits (inst1, 8, 11);
if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */
nextpc = pc_val + (sbits (inst1, 0, 7) << 1);
{
nextpc = pc_val + (sbits (inst1, 0, 10) << 1);
}
- else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */
+ else if ((inst1 & 0xf800) == 0xf000) /* long branch with link, and blx */
{
- unsigned short inst2 = read_memory_integer (pc + 2, 2);
+ unsigned short inst2 = read_memory_unsigned_integer (pc + 2, 2);
+ if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
+ inst2 = SWAP_SHORT (inst2);
offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1);
nextpc = pc_val + offset;
+ /* For BLX make sure to clear the low bits. */
+ if (bits (inst2, 11, 12) == 1)
+ nextpc = nextpc & 0xfffffffc;
+ }
+ else if ((inst1 & 0xff00) == 0x4700) /* bx REG, blx REG */
+ {
+ if (bits (inst1, 3, 6) == 0x0f)
+ nextpc = pc_val;
+ else
+ nextpc = get_frame_register_unsigned (frame, bits (inst1, 3, 6));
+
+ nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
+ if (nextpc == pc)
+ error (_("Infinite loop detected"));
}
return nextpc;
}
CORE_ADDR
-arm_get_next_pc (CORE_ADDR pc)
+arm_get_next_pc (struct frame_info *frame, CORE_ADDR pc)
{
+ struct gdbarch *gdbarch = get_frame_arch (frame);
unsigned long pc_val;
unsigned long this_instr;
unsigned long status;
CORE_ADDR nextpc;
- if (arm_pc_is_thumb (pc))
- return thumb_get_next_pc (pc);
+ if (arm_frame_is_thumb (frame))
+ return thumb_get_next_pc (frame, pc);
pc_val = (unsigned long) pc;
- this_instr = read_memory_integer (pc, 4);
- status = read_register (ARM_PS_REGNUM);
+ this_instr = read_memory_unsigned_integer (pc, 4);
+
+ if (gdbarch_byte_order_for_code (gdbarch) != gdbarch_byte_order (gdbarch))
+ this_instr = SWAP_INT (this_instr);
+
+ status = get_frame_register_unsigned (frame, ARM_PS_REGNUM);
nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
- if (condition_true (bits (this_instr, 28, 31), status))
+ if (bits (this_instr, 28, 31) == INST_NV)
+ switch (bits (this_instr, 24, 27))
+ {
+ case 0xa:
+ case 0xb:
+ {
+ /* Branch with Link and change to Thumb. */
+ nextpc = BranchDest (pc, this_instr);
+ nextpc |= bit (this_instr, 24) << 1;
+
+ nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
+ if (nextpc == pc)
+ error (_("Infinite loop detected"));
+ break;
+ }
+ case 0xc:
+ case 0xd:
+ case 0xe:
+ /* Coprocessor register transfer. */
+ if (bits (this_instr, 12, 15) == 15)
+ error (_("Invalid update to pc in instruction"));
+ break;
+ }
+ else if (condition_true (bits (this_instr, 28, 31), status))
{
switch (bits (this_instr, 24, 27))
{
if (bits (this_instr, 22, 25) == 0
&& bits (this_instr, 4, 7) == 9) /* multiply */
- error ("Illegal update to pc in instruction");
+ error (_("Invalid update to pc in instruction"));
+
+ /* BX <reg>, BLX <reg> */
+ if (bits (this_instr, 4, 27) == 0x12fff1
+ || bits (this_instr, 4, 27) == 0x12fff3)
+ {
+ rn = bits (this_instr, 0, 3);
+ result = (rn == 15) ? pc_val + 8
+ : get_frame_register_unsigned (frame, rn);
+ nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
+ (gdbarch, result);
+
+ if (nextpc == pc)
+ error (_("Infinite loop detected"));
+
+ return nextpc;
+ }
/* Multiply into PC */
c = (status & FLAG_C) ? 1 : 0;
rn = bits (this_instr, 16, 19);
- operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
+ operand1 = (rn == 15) ? pc_val + 8
+ : get_frame_register_unsigned (frame, rn);
if (bit (this_instr, 25))
{
& 0xffffffff;
}
else /* operand 2 is a shifted register */
- operand2 = shifted_reg_val (this_instr, c, pc_val, status);
+ operand2 = shifted_reg_val (frame, this_instr, c, pc_val, status);
switch (bits (this_instr, 21, 24))
{
result = ~operand2;
break;
}
- nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
+ nextpc = (CORE_ADDR) gdbarch_addr_bits_remove
+ (gdbarch, result);
if (nextpc == pc)
- error ("Infinite loop detected");
+ error (_("Infinite loop detected"));
break;
}
unsigned long base;
if (bit (this_instr, 22))
- error ("Illegal update to pc in instruction");
+ error (_("Invalid update to pc in instruction"));
/* byte write to PC */
rn = bits (this_instr, 16, 19);
- base = (rn == 15) ? pc_val + 8 : read_register (rn);
+ base = (rn == 15) ? pc_val + 8
+ : get_frame_register_unsigned (frame, rn);
if (bit (this_instr, 24))
{
/* pre-indexed */
int c = (status & FLAG_C) ? 1 : 0;
unsigned long offset =
(bit (this_instr, 25)
- ? shifted_reg_val (this_instr, c, pc_val, status)
+ ? shifted_reg_val (frame, this_instr, c, pc_val, status)
: bits (this_instr, 0, 11));
if (bit (this_instr, 23))
nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
4);
- nextpc = ADDR_BITS_REMOVE (nextpc);
+ nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
if (nextpc == pc)
- error ("Infinite loop detected");
+ error (_("Infinite loop detected"));
}
}
break;
{
unsigned long rn_val =
- read_register (bits (this_instr, 16, 19));
+ get_frame_register_unsigned (frame,
+ bits (this_instr, 16, 19));
nextpc =
(CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
+ offset),
4);
}
- nextpc = ADDR_BITS_REMOVE (nextpc);
+ nextpc = gdbarch_addr_bits_remove
+ (gdbarch, nextpc);
if (nextpc == pc)
- error ("Infinite loop detected");
+ error (_("Infinite loop detected"));
}
}
break;
{
nextpc = BranchDest (pc, this_instr);
- nextpc = ADDR_BITS_REMOVE (nextpc);
+ nextpc = gdbarch_addr_bits_remove (gdbarch, nextpc);
if (nextpc == pc)
- error ("Infinite loop detected");
+ error (_("Infinite loop detected"));
break;
}
break;
default:
- fprintf_filtered (gdb_stderr, "Bad bit-field extraction\n");
+ fprintf_filtered (gdb_stderr, _("Bad bit-field extraction\n"));
return (pc);
}
}
/* single_step() is called just before we want to resume the inferior,
if we want to single-step it but there is no hardware or kernel
single-step support. We find the target of the coming instruction
- and breakpoint it.
-
- single_step() is also called just after the inferior stops. If we
- had set up a simulated single-step, we undo our damage. */
+ and breakpoint it. */
-static void
-arm_software_single_step (enum target_signal sig, int insert_bpt)
+int
+arm_software_single_step (struct frame_info *frame)
{
- static int next_pc; /* State between setting and unsetting. */
- static char break_mem[BREAKPOINT_MAX]; /* Temporary storage for mem@bpt */
+ /* NOTE: This may insert the wrong breakpoint instruction when
+ single-stepping over a mode-changing instruction, if the
+ CPSR heuristics are used. */
- if (insert_bpt)
- {
- next_pc = arm_get_next_pc (read_register (ARM_PC_REGNUM));
- target_insert_breakpoint (next_pc, break_mem);
- }
- else
- target_remove_breakpoint (next_pc, break_mem);
+ CORE_ADDR next_pc = arm_get_next_pc (frame, get_frame_pc (frame));
+ insert_single_step_breakpoint (next_pc);
+
+ return 1;
}
#include "bfd-in2.h"
else
info->symbols = NULL;
- if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
+ if (info->endian == BFD_ENDIAN_BIG)
return print_insn_big_arm (memaddr, info);
else
return print_insn_little_arm (memaddr, info);
instruction to force a trap. This can be handled by by the
abi-specific code during establishment of the gdbarch vector. */
-
-/* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
- override these definitions. */
-#ifndef ARM_LE_BREAKPOINT
#define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
-#endif
-#ifndef ARM_BE_BREAKPOINT
#define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
-#endif
-#ifndef THUMB_LE_BREAKPOINT
-#define THUMB_LE_BREAKPOINT {0xfe,0xdf}
-#endif
-#ifndef THUMB_BE_BREAKPOINT
-#define THUMB_BE_BREAKPOINT {0xdf,0xfe}
-#endif
+#define THUMB_LE_BREAKPOINT {0xbe,0xbe}
+#define THUMB_BE_BREAKPOINT {0xbe,0xbe}
static const char arm_default_arm_le_breakpoint[] = ARM_LE_BREAKPOINT;
static const char arm_default_arm_be_breakpoint[] = ARM_BE_BREAKPOINT;
necessary) to point to the actual memory location where the
breakpoint should be inserted. */
-/* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
- breakpoints and storing their handles instread of what was in
- memory. It is nice that this is the same size as a handle -
- otherwise remote-rdp will have to change. */
-
static const unsigned char *
-arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
+arm_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr))
+ if (arm_pc_is_thumb (*pcptr))
{
*pcptr = UNMAKE_THUMB_ADDR (*pcptr);
*lenptr = tdep->thumb_breakpoint_size;
format, into VALBUF. */
static void
-arm_extract_return_value (struct type *type,
- struct regcache *regs,
- void *dst)
+arm_extract_return_value (struct type *type, struct regcache *regs,
+ gdb_byte *valbuf)
{
- bfd_byte *valbuf = dst;
+ struct gdbarch *gdbarch = get_regcache_arch (regs);
if (TYPE_CODE_FLT == TYPE_CODE (type))
{
- switch (arm_get_fp_model (current_gdbarch))
+ switch (gdbarch_tdep (gdbarch)->fp_model)
{
case ARM_FLOAT_FPA:
{
/* The value is in register F0 in internal format. We need to
extract the raw value and then convert it to the desired
internal type. */
- bfd_byte tmpbuf[FP_REGISTER_RAW_SIZE];
+ bfd_byte tmpbuf[FP_REGISTER_SIZE];
regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
convert_from_extended (floatformat_from_type (type), tmpbuf,
- valbuf);
+ valbuf, gdbarch_byte_order (gdbarch));
}
break;
regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
if (TYPE_LENGTH (type) > 4)
regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
- valbuf + INT_REGISTER_RAW_SIZE);
+ valbuf + INT_REGISTER_SIZE);
break;
default:
internal_error
(__FILE__, __LINE__,
- "arm_extract_return_value: Floating point model not supported");
+ _("arm_extract_return_value: Floating point model not supported"));
break;
}
}
anything special for small big-endian values. */
regcache_cooked_read_unsigned (regs, regno++, &tmp);
store_unsigned_integer (valbuf,
- (len > INT_REGISTER_RAW_SIZE
- ? INT_REGISTER_RAW_SIZE : len),
+ (len > INT_REGISTER_SIZE
+ ? INT_REGISTER_SIZE : len),
tmp);
- len -= INT_REGISTER_RAW_SIZE;
- valbuf += INT_REGISTER_RAW_SIZE;
+ len -= INT_REGISTER_SIZE;
+ valbuf += INT_REGISTER_SIZE;
}
}
else
registers with 32-bit load instruction(s). */
int len = TYPE_LENGTH (type);
int regno = ARM_A1_REGNUM;
- bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE];
+ bfd_byte tmpbuf[INT_REGISTER_SIZE];
while (len > 0)
{
regcache_cooked_read (regs, regno++, tmpbuf);
memcpy (valbuf, tmpbuf,
- len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len);
- len -= INT_REGISTER_RAW_SIZE;
- valbuf += INT_REGISTER_RAW_SIZE;
+ len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
+ len -= INT_REGISTER_SIZE;
+ valbuf += INT_REGISTER_SIZE;
}
}
}
-/* Extract from an array REGBUF containing the (raw) register state
- the address in which a function should return its structure value. */
-
-static CORE_ADDR
-arm_extract_struct_value_address (struct regcache *regcache)
-{
- ULONGEST ret;
-
- regcache_cooked_read_unsigned (regcache, ARM_A1_REGNUM, &ret);
- return ret;
-}
/* Will a function return an aggregate type in memory or in a
register? Return 0 if an aggregate type can be returned in a
register, 1 if it must be returned in memory. */
static int
-arm_use_struct_convention (int gcc_p, struct type *type)
+arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
{
int nRc;
- register enum type_code code;
+ enum type_code code;
+
+ CHECK_TYPEDEF (type);
/* In the ARM ABI, "integer" like aggregate types are returned in
registers. For an aggregate type to be integer like, its size
- must be less than or equal to REGISTER_SIZE and the offset of
- each addressable subfield must be zero. Note that bit fields are
- not addressable, and all addressable subfields of unions always
- start at offset zero.
+ must be less than or equal to INT_REGISTER_SIZE and the
+ offset of each addressable subfield must be zero. Note that bit
+ fields are not addressable, and all addressable subfields of
+ unions always start at offset zero.
This function is based on the behaviour of GCC 2.95.1.
See: gcc/arm.c: arm_return_in_memory() for details.
/* All aggregate types that won't fit in a register must be returned
in memory. */
- if (TYPE_LENGTH (type) > REGISTER_SIZE)
+ if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
{
return 1;
}
+ /* The AAPCS says all aggregates not larger than a word are returned
+ in a register. */
+ if (gdbarch_tdep (gdbarch)->arm_abi != ARM_ABI_APCS)
+ return 0;
+
/* The only aggregate types that can be returned in a register are
structs and unions. Arrays must be returned in memory. */
code = TYPE_CODE (type);
int i;
/* Need to check if this struct/union is "integer" like. For
this to be true, its size must be less than or equal to
- REGISTER_SIZE and the offset of each addressable subfield
- must be zero. Note that bit fields are not addressable, and
- unions always start at offset zero. If any of the subfields
- is a floating point type, the struct/union cannot be an
- integer type. */
+ INT_REGISTER_SIZE and the offset of each addressable
+ subfield must be zero. Note that bit fields are not
+ addressable, and unions always start at offset zero. If any
+ of the subfields is a floating point type, the struct/union
+ cannot be an integer type. */
/* For each field in the object, check:
1) Is it FP? --> yes, nRc = 1;
for (i = 0; i < TYPE_NFIELDS (type); i++)
{
enum type_code field_type_code;
- field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i));
+ field_type_code = TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, i)));
/* Is it a floating point type field? */
if (field_type_code == TYPE_CODE_FLT)
static void
arm_store_return_value (struct type *type, struct regcache *regs,
- const void *src)
+ const gdb_byte *valbuf)
{
- const bfd_byte *valbuf = src;
+ struct gdbarch *gdbarch = get_regcache_arch (regs);
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
- char buf[ARM_MAX_REGISTER_RAW_SIZE];
+ char buf[MAX_REGISTER_SIZE];
- switch (arm_get_fp_model (current_gdbarch))
+ switch (gdbarch_tdep (gdbarch)->fp_model)
{
case ARM_FLOAT_FPA:
- convert_to_extended (floatformat_from_type (type), buf, valbuf);
+ convert_to_extended (floatformat_from_type (type), buf, valbuf,
+ gdbarch_byte_order (gdbarch));
regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
break;
regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
if (TYPE_LENGTH (type) > 4)
regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
- valbuf + INT_REGISTER_RAW_SIZE);
+ valbuf + INT_REGISTER_SIZE);
break;
default:
internal_error
(__FILE__, __LINE__,
- "arm_store_return_value: Floating point model not supported");
+ _("arm_store_return_value: Floating point model not supported"));
break;
}
}
{
/* Values of one word or less are zero/sign-extended and
returned in r0. */
- bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE];
+ bfd_byte tmpbuf[INT_REGISTER_SIZE];
LONGEST val = unpack_long (type, valbuf);
- store_signed_integer (tmpbuf, INT_REGISTER_RAW_SIZE, val);
+ store_signed_integer (tmpbuf, INT_REGISTER_SIZE, val);
regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
}
else
while (len > 0)
{
regcache_cooked_write (regs, regno++, valbuf);
- len -= INT_REGISTER_RAW_SIZE;
- valbuf += INT_REGISTER_RAW_SIZE;
+ len -= INT_REGISTER_SIZE;
+ valbuf += INT_REGISTER_SIZE;
}
}
}
registers with 32-bit load instruction(s). */
int len = TYPE_LENGTH (type);
int regno = ARM_A1_REGNUM;
- bfd_byte tmpbuf[INT_REGISTER_RAW_SIZE];
+ bfd_byte tmpbuf[INT_REGISTER_SIZE];
while (len > 0)
{
memcpy (tmpbuf, valbuf,
- len > INT_REGISTER_RAW_SIZE ? INT_REGISTER_RAW_SIZE : len);
+ len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
regcache_cooked_write (regs, regno++, tmpbuf);
- len -= INT_REGISTER_RAW_SIZE;
- valbuf += INT_REGISTER_RAW_SIZE;
+ len -= INT_REGISTER_SIZE;
+ valbuf += INT_REGISTER_SIZE;
}
}
}
-/* Store the address of the place in which to copy the structure the
- subroutine will return. This is called from call_function. */
-static void
-arm_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
+/* Handle function return values. */
+
+static enum return_value_convention
+arm_return_value (struct gdbarch *gdbarch, struct type *func_type,
+ struct type *valtype, struct regcache *regcache,
+ gdb_byte *readbuf, const gdb_byte *writebuf)
{
- write_register (ARM_A1_REGNUM, addr);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
+ || TYPE_CODE (valtype) == TYPE_CODE_UNION
+ || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
+ {
+ if (tdep->struct_return == pcc_struct_return
+ || arm_return_in_memory (gdbarch, valtype))
+ return RETURN_VALUE_STRUCT_CONVENTION;
+ }
+
+ if (writebuf)
+ arm_store_return_value (valtype, regcache, writebuf);
+
+ if (readbuf)
+ arm_extract_return_value (valtype, regcache, readbuf);
+
+ return RETURN_VALUE_REGISTER_CONVENTION;
}
+
static int
-arm_get_longjmp_target (CORE_ADDR *pc)
+arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
{
CORE_ADDR jb_addr;
- char buf[INT_REGISTER_RAW_SIZE];
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ char buf[INT_REGISTER_SIZE];
+ struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
- jb_addr = read_register (ARM_A1_REGNUM);
+ jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
- INT_REGISTER_RAW_SIZE))
+ INT_REGISTER_SIZE))
return 0;
- *pc = extract_address (buf, INT_REGISTER_RAW_SIZE);
+ *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE);
return 1;
}
-/* Return non-zero if the PC is inside a thumb call thunk. */
-
-int
-arm_in_call_stub (CORE_ADDR pc, char *name)
-{
- CORE_ADDR start_addr;
-
- /* Find the starting address of the function containing the PC. If
- the caller didn't give us a name, look it up at the same time. */
- if (0 == find_pc_partial_function (pc, name ? NULL : &name,
- &start_addr, NULL))
- return 0;
-
- return strncmp (name, "_call_via_r", 11) == 0;
-}
-
-/* If PC is in a Thumb call or return stub, return the address of the
- target PC, which is in a register. The thunk functions are called
- _called_via_xx, where x is the register name. The possible names
- are r0-r9, sl, fp, ip, sp, and lr. */
+/* Recognize GCC and GNU ld's trampolines. If we are in a trampoline,
+ return the target PC. Otherwise return 0. */
CORE_ADDR
-arm_skip_stub (CORE_ADDR pc)
+arm_skip_stub (struct frame_info *frame, CORE_ADDR pc)
{
char *name;
+ int namelen;
CORE_ADDR start_addr;
/* Find the starting address and name of the function containing the PC. */
if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
return 0;
- /* Call thunks always start with "_call_via_". */
+ /* If PC is in a Thumb call or return stub, return the address of the
+ target PC, which is in a register. The thunk functions are called
+ _call_via_xx, where x is the register name. The possible names
+ are r0-r9, sl, fp, ip, sp, and lr. */
if (strncmp (name, "_call_via_", 10) == 0)
{
/* Use the name suffix to determine which register contains the
"r8", "r9", "sl", "fp", "ip", "sp", "lr"
};
int regno;
+ int offset = strlen (name) - 2;
for (regno = 0; regno <= 14; regno++)
- if (strcmp (&name[10], table[regno]) == 0)
- return read_register (regno);
+ if (strcmp (&name[offset], table[regno]) == 0)
+ return get_frame_register_unsigned (frame, regno);
+ }
+
+ /* GNU ld generates __foo_from_arm or __foo_from_thumb for
+ non-interworking calls to foo. We could decode the stubs
+ to find the target but it's easier to use the symbol table. */
+ namelen = strlen (name);
+ if (name[0] == '_' && name[1] == '_'
+ && ((namelen > 2 + strlen ("_from_thumb")
+ && strncmp (name + namelen - strlen ("_from_thumb"), "_from_thumb",
+ strlen ("_from_thumb")) == 0)
+ || (namelen > 2 + strlen ("_from_arm")
+ && strncmp (name + namelen - strlen ("_from_arm"), "_from_arm",
+ strlen ("_from_arm")) == 0)))
+ {
+ char *target_name;
+ int target_len = namelen - 2;
+ struct minimal_symbol *minsym;
+ struct objfile *objfile;
+ struct obj_section *sec;
+
+ if (name[namelen - 1] == 'b')
+ target_len -= strlen ("_from_thumb");
+ else
+ target_len -= strlen ("_from_arm");
+
+ target_name = alloca (target_len + 1);
+ memcpy (target_name, name + 2, target_len);
+ target_name[target_len] = '\0';
+
+ sec = find_pc_section (pc);
+ objfile = (sec == NULL) ? NULL : sec->objfile;
+ minsym = lookup_minimal_symbol (target_name, NULL, objfile);
+ if (minsym != NULL)
+ return SYMBOL_VALUE_ADDRESS (minsym);
+ else
+ return 0;
}
return 0; /* not a stub */
static void
set_arm_command (char *args, int from_tty)
{
- printf_unfiltered ("\"set arm\" must be followed by an apporpriate subcommand.\n");
+ printf_unfiltered (_("\
+\"set arm\" must be followed by an apporpriate subcommand.\n"));
help_list (setarmcmdlist, "set arm ", all_commands, gdb_stdout);
}
cmd_show_list (showarmcmdlist, from_tty, "");
}
-enum arm_float_model
-arm_get_fp_model (struct gdbarch *gdbarch)
+static void
+arm_update_current_architecture (void)
{
- if (arm_fp_model == ARM_FLOAT_AUTO)
- return gdbarch_tdep (gdbarch)->fp_model;
+ struct gdbarch_info info;
- return arm_fp_model;
-}
+ /* If the current architecture is not ARM, we have nothing to do. */
+ if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_arm)
+ return;
-static void
-arm_set_fp (struct gdbarch *gdbarch)
-{
- enum arm_float_model fp_model = arm_get_fp_model (gdbarch);
+ /* Update the architecture. */
+ gdbarch_info_init (&info);
- if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
- && (fp_model == ARM_FLOAT_SOFT_FPA || fp_model == ARM_FLOAT_FPA))
- {
- set_gdbarch_double_format (gdbarch,
- &floatformat_ieee_double_littlebyte_bigword);
- set_gdbarch_long_double_format
- (gdbarch, &floatformat_ieee_double_littlebyte_bigword);
- }
- else
- {
- set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_little);
- set_gdbarch_long_double_format (gdbarch,
- &floatformat_ieee_double_little);
- }
+ if (!gdbarch_update_p (info))
+ internal_error (__FILE__, __LINE__, "could not update architecture");
}
static void
}
if (fp_model == ARM_FLOAT_LAST)
- internal_error (__FILE__, __LINE__, "Invalid fp model accepted: %s.",
+ internal_error (__FILE__, __LINE__, _("Invalid fp model accepted: %s."),
current_fp_model);
- if (gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
- arm_set_fp (current_gdbarch);
+ arm_update_current_architecture ();
+}
+
+static void
+show_fp_model (struct ui_file *file, int from_tty,
+ struct cmd_list_element *c, const char *value)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
+
+ if (arm_fp_model == ARM_FLOAT_AUTO
+ && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
+ fprintf_filtered (file, _("\
+The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
+ fp_model_strings[tdep->fp_model]);
+ else
+ fprintf_filtered (file, _("\
+The current ARM floating point model is \"%s\".\n"),
+ fp_model_strings[arm_fp_model]);
+}
+
+static void
+arm_set_abi (char *args, int from_tty,
+ struct cmd_list_element *c)
+{
+ enum arm_abi_kind arm_abi;
+
+ for (arm_abi = ARM_ABI_AUTO; arm_abi != ARM_ABI_LAST; arm_abi++)
+ if (strcmp (arm_abi_string, arm_abi_strings[arm_abi]) == 0)
+ {
+ arm_abi_global = arm_abi;
+ break;
+ }
+
+ if (arm_abi == ARM_ABI_LAST)
+ internal_error (__FILE__, __LINE__, _("Invalid ABI accepted: %s."),
+ arm_abi_string);
+
+ arm_update_current_architecture ();
+}
+
+static void
+arm_show_abi (struct ui_file *file, int from_tty,
+ struct cmd_list_element *c, const char *value)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
+
+ if (arm_abi_global == ARM_ABI_AUTO
+ && gdbarch_bfd_arch_info (target_gdbarch)->arch == bfd_arch_arm)
+ fprintf_filtered (file, _("\
+The current ARM ABI is \"auto\" (currently \"%s\").\n"),
+ arm_abi_strings[tdep->arm_abi]);
+ else
+ fprintf_filtered (file, _("The current ARM ABI is \"%s\".\n"),
+ arm_abi_string);
+}
+
+static void
+arm_show_fallback_mode (struct ui_file *file, int from_tty,
+ struct cmd_list_element *c, const char *value)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
+
+ fprintf_filtered (file, _("\
+The current execution mode assumed (when symbols are unavailable) is \"%s\".\n"),
+ arm_fallback_mode_string);
}
static void
-show_fp_model (char *args, int from_tty,
- struct cmd_list_element *c)
+arm_show_force_mode (struct ui_file *file, int from_tty,
+ struct cmd_list_element *c, const char *value)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch);
- if (arm_fp_model == ARM_FLOAT_AUTO
- && gdbarch_bfd_arch_info (current_gdbarch)->arch == bfd_arch_arm)
- printf_filtered (" - the default for the current ABI is \"%s\".\n",
- fp_model_strings[tdep->fp_model]);
+ fprintf_filtered (file, _("\
+The current execution mode assumed (even when symbols are available) is \"%s\".\n"),
+ arm_force_mode_string);
}
/* If the user changes the register disassembly style used for info
\f
/* Return the ARM register name corresponding to register I. */
static const char *
-arm_register_name (int i)
+arm_register_name (struct gdbarch *gdbarch, int i)
{
+ if (i >= ARRAY_SIZE (arm_register_names))
+ /* These registers are only supported on targets which supply
+ an XML description. */
+ return "";
+
return arm_register_names[i];
}
static void
set_disassembly_style (void)
{
- const char *setname, *setdesc, **regnames;
- int numregs, j;
-
- /* Find the style that the user wants in the opcodes table. */
- int current = 0;
- numregs = get_arm_regnames (current, &setname, &setdesc, ®names);
- while ((disassembly_style != setname)
- && (current < num_disassembly_options))
- get_arm_regnames (++current, &setname, &setdesc, ®names);
- current_option = current;
+ int current;
- /* Fill our copy. */
- for (j = 0; j < numregs; j++)
- arm_register_names[j] = (char *) regnames[j];
-
- /* Adjust case. */
- if (isupper (*regnames[ARM_PC_REGNUM]))
- {
- arm_register_names[ARM_FPS_REGNUM] = "FPS";
- arm_register_names[ARM_PS_REGNUM] = "CPSR";
- }
- else
- {
- arm_register_names[ARM_FPS_REGNUM] = "fps";
- arm_register_names[ARM_PS_REGNUM] = "cpsr";
- }
+ /* Find the style that the user wants. */
+ for (current = 0; current < num_disassembly_options; current++)
+ if (disassembly_style == valid_disassembly_styles[current])
+ break;
+ gdb_assert (current < num_disassembly_options);
/* Synchronize the disassembler. */
set_arm_regname_option (current);
}
-/* arm_othernames implements the "othernames" command. This is deprecated
- by the "set arm disassembly" command. */
-
-static void
-arm_othernames (char *names, int n)
-{
- /* Circle through the various flavors. */
- current_option = (current_option + 1) % num_disassembly_options;
-
- disassembly_style = valid_disassembly_styles[current_option];
- set_disassembly_style ();
-}
-
-/* Fetch, and possibly build, an appropriate link_map_offsets structure
- for ARM linux targets using the struct offsets defined in <link.h>.
- Note, however, that link.h is not actually referred to in this file.
- Instead, the relevant structs offsets were obtained from examining
- link.h. (We can't refer to link.h from this file because the host
- system won't necessarily have it, or if it does, the structs which
- it defines will refer to the host system, not the target). */
-
-struct link_map_offsets *
-arm_linux_svr4_fetch_link_map_offsets (void)
-{
- static struct link_map_offsets lmo;
- static struct link_map_offsets *lmp = 0;
-
- if (lmp == 0)
- {
- lmp = &lmo;
-
- lmo.r_debug_size = 8; /* Actual size is 20, but this is all we
- need. */
-
- lmo.r_map_offset = 4;
- lmo.r_map_size = 4;
-
- lmo.link_map_size = 20; /* Actual size is 552, but this is all we
- need. */
-
- lmo.l_addr_offset = 0;
- lmo.l_addr_size = 4;
-
- lmo.l_name_offset = 4;
- lmo.l_name_size = 4;
-
- lmo.l_next_offset = 12;
- lmo.l_next_size = 4;
-
- lmo.l_prev_offset = 16;
- lmo.l_prev_size = 4;
- }
-
- return lmp;
-}
-
/* Test whether the coff symbol specific value corresponds to a Thumb
function. */
MSYMBOL_SET_SPECIAL (msym);
}
-\f
-static enum gdb_osabi
-arm_elf_osabi_sniffer (bfd *abfd)
+static void
+arm_objfile_data_cleanup (struct objfile *objfile, void *arg)
{
- unsigned int elfosabi, eflags;
- enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
+ struct arm_per_objfile *data = arg;
+ unsigned int i;
- elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
+ for (i = 0; i < objfile->obfd->section_count; i++)
+ VEC_free (arm_mapping_symbol_s, data->section_maps[i]);
+}
- switch (elfosabi)
- {
- case ELFOSABI_NONE:
- /* When elfosabi is ELFOSABI_NONE (0), then the ELF structures in the
- file are conforming to the base specification for that machine
- (there are no OS-specific extensions). In order to determine the
- real OS in use we must look for OS notes that have been added. */
- bfd_map_over_sections (abfd,
- generic_elf_osabi_sniff_abi_tag_sections,
- &osabi);
- if (osabi == GDB_OSABI_UNKNOWN)
- {
- /* Existing ARM tools don't set this field, so look at the EI_FLAGS
- field for more information. */
- eflags = EF_ARM_EABI_VERSION(elf_elfheader(abfd)->e_flags);
- switch (eflags)
- {
- case EF_ARM_EABI_VER1:
- osabi = GDB_OSABI_ARM_EABI_V1;
- break;
+static void
+arm_record_special_symbol (struct gdbarch *gdbarch, struct objfile *objfile,
+ asymbol *sym)
+{
+ const char *name = bfd_asymbol_name (sym);
+ struct arm_per_objfile *data;
+ VEC(arm_mapping_symbol_s) **map_p;
+ struct arm_mapping_symbol new_map_sym;
- case EF_ARM_EABI_VER2:
- osabi = GDB_OSABI_ARM_EABI_V2;
- break;
+ gdb_assert (name[0] == '$');
+ if (name[1] != 'a' && name[1] != 't' && name[1] != 'd')
+ return;
- case EF_ARM_EABI_UNKNOWN:
- /* Assume GNU tools. */
- osabi = GDB_OSABI_ARM_APCS;
- break;
+ data = objfile_data (objfile, arm_objfile_data_key);
+ if (data == NULL)
+ {
+ data = OBSTACK_ZALLOC (&objfile->objfile_obstack,
+ struct arm_per_objfile);
+ set_objfile_data (objfile, arm_objfile_data_key, data);
+ data->section_maps = OBSTACK_CALLOC (&objfile->objfile_obstack,
+ objfile->obfd->section_count,
+ VEC(arm_mapping_symbol_s) *);
+ }
+ map_p = &data->section_maps[bfd_get_section (sym)->index];
- default:
- internal_error (__FILE__, __LINE__,
- "arm_elf_osabi_sniffer: Unknown ARM EABI "
- "version 0x%x", eflags);
- }
- }
- break;
+ new_map_sym.value = sym->value;
+ new_map_sym.type = name[1];
+
+ /* Assume that most mapping symbols appear in order of increasing
+ value. If they were randomly distributed, it would be faster to
+ always push here and then sort at first use. */
+ if (!VEC_empty (arm_mapping_symbol_s, *map_p))
+ {
+ struct arm_mapping_symbol *prev_map_sym;
- case ELFOSABI_ARM:
- /* GNU tools use this value. Check note sections in this case,
- as well. */
- bfd_map_over_sections (abfd,
- generic_elf_osabi_sniff_abi_tag_sections,
- &osabi);
- if (osabi == GDB_OSABI_UNKNOWN)
+ prev_map_sym = VEC_last (arm_mapping_symbol_s, *map_p);
+ if (prev_map_sym->value >= sym->value)
{
- /* Assume APCS ABI. */
- osabi = GDB_OSABI_ARM_APCS;
+ unsigned int idx;
+ idx = VEC_lower_bound (arm_mapping_symbol_s, *map_p, &new_map_sym,
+ arm_compare_mapping_symbols);
+ VEC_safe_insert (arm_mapping_symbol_s, *map_p, idx, &new_map_sym);
+ return;
}
- break;
+ }
- case ELFOSABI_FREEBSD:
- osabi = GDB_OSABI_FREEBSD_ELF;
- break;
+ VEC_safe_push (arm_mapping_symbol_s, *map_p, &new_map_sym);
+}
- case ELFOSABI_NETBSD:
- osabi = GDB_OSABI_NETBSD_ELF;
- break;
+static void
+arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
+{
+ regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
- case ELFOSABI_LINUX:
- osabi = GDB_OSABI_LINUX;
- break;
+ /* If necessary, set the T bit. */
+ if (arm_apcs_32)
+ {
+ ULONGEST val;
+ regcache_cooked_read_unsigned (regcache, ARM_PS_REGNUM, &val);
+ if (arm_pc_is_thumb (pc))
+ regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM, val | CPSR_T);
+ else
+ regcache_cooked_write_unsigned (regcache, ARM_PS_REGNUM,
+ val & ~(ULONGEST) CPSR_T);
}
+}
+
+static struct value *
+value_of_arm_user_reg (struct frame_info *frame, const void *baton)
+{
+ const int *reg_p = baton;
+ return value_of_register (*reg_p, frame);
+}
+\f
+static enum gdb_osabi
+arm_elf_osabi_sniffer (bfd *abfd)
+{
+ unsigned int elfosabi;
+ enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
+ elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
+
+ if (elfosabi == ELFOSABI_ARM)
+ /* GNU tools use this value. Check note sections in this case,
+ as well. */
+ bfd_map_over_sections (abfd,
+ generic_elf_osabi_sniff_abi_tag_sections,
+ &osabi);
+
+ /* Anything else will be handled by the generic ELF sniffer. */
return osabi;
}
{
struct gdbarch_tdep *tdep;
struct gdbarch *gdbarch;
+ struct gdbarch_list *best_arch;
+ enum arm_abi_kind arm_abi = arm_abi_global;
+ enum arm_float_model fp_model = arm_fp_model;
+ struct tdesc_arch_data *tdesc_data = NULL;
+ int i;
+ int have_fpa_registers = 1;
- /* Try to deterimine the ABI of the object we are loading. */
+ /* Check any target description for validity. */
+ if (tdesc_has_registers (info.target_desc))
+ {
+ /* For most registers we require GDB's default names; but also allow
+ the numeric names for sp / lr / pc, as a convenience. */
+ static const char *const arm_sp_names[] = { "r13", "sp", NULL };
+ static const char *const arm_lr_names[] = { "r14", "lr", NULL };
+ static const char *const arm_pc_names[] = { "r15", "pc", NULL };
+
+ const struct tdesc_feature *feature;
+ int i, valid_p;
+
+ feature = tdesc_find_feature (info.target_desc,
+ "org.gnu.gdb.arm.core");
+ if (feature == NULL)
+ return NULL;
+
+ tdesc_data = tdesc_data_alloc ();
+
+ valid_p = 1;
+ for (i = 0; i < ARM_SP_REGNUM; i++)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
+ arm_register_names[i]);
+ valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
+ ARM_SP_REGNUM,
+ arm_sp_names);
+ valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
+ ARM_LR_REGNUM,
+ arm_lr_names);
+ valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
+ ARM_PC_REGNUM,
+ arm_pc_names);
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ ARM_PS_REGNUM, "cpsr");
+
+ if (!valid_p)
+ {
+ tdesc_data_cleanup (tdesc_data);
+ return NULL;
+ }
+
+ feature = tdesc_find_feature (info.target_desc,
+ "org.gnu.gdb.arm.fpa");
+ if (feature != NULL)
+ {
+ valid_p = 1;
+ for (i = ARM_F0_REGNUM; i <= ARM_FPS_REGNUM; i++)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
+ arm_register_names[i]);
+ if (!valid_p)
+ {
+ tdesc_data_cleanup (tdesc_data);
+ return NULL;
+ }
+ }
+ else
+ have_fpa_registers = 0;
+
+ feature = tdesc_find_feature (info.target_desc,
+ "org.gnu.gdb.xscale.iwmmxt");
+ if (feature != NULL)
+ {
+ static const char *const iwmmxt_names[] = {
+ "wR0", "wR1", "wR2", "wR3", "wR4", "wR5", "wR6", "wR7",
+ "wR8", "wR9", "wR10", "wR11", "wR12", "wR13", "wR14", "wR15",
+ "wCID", "wCon", "wCSSF", "wCASF", "", "", "", "",
+ "wCGR0", "wCGR1", "wCGR2", "wCGR3", "", "", "", "",
+ };
+
+ valid_p = 1;
+ for (i = ARM_WR0_REGNUM; i <= ARM_WR15_REGNUM; i++)
+ valid_p
+ &= tdesc_numbered_register (feature, tdesc_data, i,
+ iwmmxt_names[i - ARM_WR0_REGNUM]);
+
+ /* Check for the control registers, but do not fail if they
+ are missing. */
+ for (i = ARM_WC0_REGNUM; i <= ARM_WCASF_REGNUM; i++)
+ tdesc_numbered_register (feature, tdesc_data, i,
+ iwmmxt_names[i - ARM_WR0_REGNUM]);
+
+ for (i = ARM_WCGR0_REGNUM; i <= ARM_WCGR3_REGNUM; i++)
+ valid_p
+ &= tdesc_numbered_register (feature, tdesc_data, i,
+ iwmmxt_names[i - ARM_WR0_REGNUM]);
+
+ if (!valid_p)
+ {
+ tdesc_data_cleanup (tdesc_data);
+ return NULL;
+ }
+ }
+ }
+
+ /* If we have an object to base this architecture on, try to determine
+ its ABI. */
- if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN)
+ if (arm_abi == ARM_ABI_AUTO && info.abfd != NULL)
{
+ int ei_osabi, e_flags;
+
switch (bfd_get_flavour (info.abfd))
{
case bfd_target_aout_flavour:
/* Assume it's an old APCS-style ABI. */
- info.osabi = GDB_OSABI_ARM_APCS;
+ arm_abi = ARM_ABI_APCS;
break;
case bfd_target_coff_flavour:
/* Assume it's an old APCS-style ABI. */
/* XXX WinCE? */
- info.osabi = GDB_OSABI_ARM_APCS;
+ arm_abi = ARM_ABI_APCS;
+ break;
+
+ case bfd_target_elf_flavour:
+ ei_osabi = elf_elfheader (info.abfd)->e_ident[EI_OSABI];
+ e_flags = elf_elfheader (info.abfd)->e_flags;
+
+ if (ei_osabi == ELFOSABI_ARM)
+ {
+ /* GNU tools used to use this value, but do not for EABI
+ objects. There's nowhere to tag an EABI version
+ anyway, so assume APCS. */
+ arm_abi = ARM_ABI_APCS;
+ }
+ else if (ei_osabi == ELFOSABI_NONE)
+ {
+ int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
+
+ switch (eabi_ver)
+ {
+ case EF_ARM_EABI_UNKNOWN:
+ /* Assume GNU tools. */
+ arm_abi = ARM_ABI_APCS;
+ break;
+
+ case EF_ARM_EABI_VER4:
+ case EF_ARM_EABI_VER5:
+ arm_abi = ARM_ABI_AAPCS;
+ /* EABI binaries default to VFP float ordering. */
+ if (fp_model == ARM_FLOAT_AUTO)
+ fp_model = ARM_FLOAT_SOFT_VFP;
+ break;
+
+ default:
+ /* Leave it as "auto". */
+ warning (_("unknown ARM EABI version 0x%x"), eabi_ver);
+ break;
+ }
+ }
+
+ if (fp_model == ARM_FLOAT_AUTO)
+ {
+ int e_flags = elf_elfheader (info.abfd)->e_flags;
+
+ switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
+ {
+ case 0:
+ /* Leave it as "auto". Strictly speaking this case
+ means FPA, but almost nobody uses that now, and
+ many toolchains fail to set the appropriate bits
+ for the floating-point model they use. */
+ break;
+ case EF_ARM_SOFT_FLOAT:
+ fp_model = ARM_FLOAT_SOFT_FPA;
+ break;
+ case EF_ARM_VFP_FLOAT:
+ fp_model = ARM_FLOAT_VFP;
+ break;
+ case EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT:
+ fp_model = ARM_FLOAT_SOFT_VFP;
+ break;
+ }
+ }
+
+ if (e_flags & EF_ARM_BE8)
+ info.byte_order_for_code = BFD_ENDIAN_LITTLE;
+
break;
default:
- /* Leave it as "unknown". */
+ /* Leave it as "auto". */
break;
}
}
/* If there is already a candidate, use it. */
- arches = gdbarch_list_lookup_by_info (arches, &info);
- if (arches != NULL)
- return arches->gdbarch;
+ for (best_arch = gdbarch_list_lookup_by_info (arches, &info);
+ best_arch != NULL;
+ best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
+ {
+ if (arm_abi != ARM_ABI_AUTO
+ && arm_abi != gdbarch_tdep (best_arch->gdbarch)->arm_abi)
+ continue;
- tdep = xmalloc (sizeof (struct gdbarch_tdep));
- gdbarch = gdbarch_alloc (&info, tdep);
+ if (fp_model != ARM_FLOAT_AUTO
+ && fp_model != gdbarch_tdep (best_arch->gdbarch)->fp_model)
+ continue;
- /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
- ready to unwind the PC first (see frame.c:get_prev_frame()). */
- set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default);
+ /* Found a match. */
+ break;
+ }
+
+ if (best_arch != NULL)
+ {
+ if (tdesc_data != NULL)
+ tdesc_data_cleanup (tdesc_data);
+ return best_arch->gdbarch;
+ }
+
+ tdep = xcalloc (1, sizeof (struct gdbarch_tdep));
+ gdbarch = gdbarch_alloc (&info, tdep);
- /* We used to default to FPA for generic ARM, but almost nobody uses that
- now, and we now provide a way for the user to force the model. So
- default to the most useful variant. */
- tdep->fp_model = ARM_FLOAT_SOFT_FPA;
+ /* Record additional information about the architecture we are defining.
+ These are gdbarch discriminators, like the OSABI. */
+ tdep->arm_abi = arm_abi;
+ tdep->fp_model = fp_model;
+ tdep->have_fpa_registers = have_fpa_registers;
/* Breakpoints. */
- switch (info.byte_order)
+ switch (info.byte_order_for_code)
{
case BFD_ENDIAN_BIG:
tdep->arm_breakpoint = arm_default_arm_be_breakpoint;
default:
internal_error (__FILE__, __LINE__,
- "arm_gdbarch_init: bad byte order for float format");
+ _("arm_gdbarch_init: bad byte order for float format"));
}
/* On ARM targets char defaults to unsigned. */
tdep->lowest_pc = 0x20;
tdep->jb_pc = -1; /* Longjump support not enabled by default. */
- set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
- set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
-
- set_gdbarch_call_dummy_p (gdbarch, 1);
+ /* The default, for both APCS and AAPCS, is to return small
+ structures in registers. */
+ tdep->struct_return = reg_struct_return;
- set_gdbarch_call_dummy_words (gdbarch, arm_call_dummy_words);
- set_gdbarch_sizeof_call_dummy_words (gdbarch, 0);
- set_gdbarch_call_dummy_start_offset (gdbarch, 0);
- set_gdbarch_call_dummy_length (gdbarch, 0);
+ set_gdbarch_push_dummy_call (gdbarch, arm_push_dummy_call);
+ set_gdbarch_frame_align (gdbarch, arm_frame_align);
- set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
-
- set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
- set_gdbarch_push_return_address (gdbarch, arm_push_return_address);
-
- set_gdbarch_push_arguments (gdbarch, arm_push_arguments);
+ set_gdbarch_write_pc (gdbarch, arm_write_pc);
/* Frame handling. */
- set_gdbarch_deprecated_frame_chain_valid (gdbarch, arm_frame_chain_valid);
- set_gdbarch_deprecated_init_extra_frame_info (gdbarch, arm_init_extra_frame_info);
- set_gdbarch_read_fp (gdbarch, arm_read_fp);
- set_gdbarch_deprecated_frame_chain (gdbarch, arm_frame_chain);
- set_gdbarch_frameless_function_invocation
- (gdbarch, arm_frameless_function_invocation);
- set_gdbarch_deprecated_frame_saved_pc (gdbarch, arm_frame_saved_pc);
- set_gdbarch_frame_args_address (gdbarch, arm_frame_args_address);
- set_gdbarch_frame_locals_address (gdbarch, arm_frame_locals_address);
- set_gdbarch_frame_num_args (gdbarch, arm_frame_num_args);
- set_gdbarch_frame_args_skip (gdbarch, 0);
- set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, arm_frame_init_saved_regs);
- set_gdbarch_deprecated_pop_frame (gdbarch, arm_pop_frame);
+ set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
+ set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
+ set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
+
+ frame_base_set_default (gdbarch, &arm_normal_base);
/* Address manipulation. */
set_gdbarch_smash_text_address (gdbarch, arm_smash_text_address);
set_gdbarch_addr_bits_remove (gdbarch, arm_addr_bits_remove);
- /* Offset from address of function to start of its code. */
- set_gdbarch_function_start_offset (gdbarch, 0);
-
/* Advance PC across function entry code. */
set_gdbarch_skip_prologue (gdbarch, arm_skip_prologue);
- /* Get the PC when a frame might not be available. */
- set_gdbarch_saved_pc_after_call (gdbarch, arm_saved_pc_after_call);
+ /* Skip trampolines. */
+ set_gdbarch_skip_trampoline_code (gdbarch, arm_skip_stub);
/* The stack grows downward. */
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
/* Breakpoint manipulation. */
set_gdbarch_breakpoint_from_pc (gdbarch, arm_breakpoint_from_pc);
- set_gdbarch_decr_pc_after_break (gdbarch, 0);
/* Information about registers, etc. */
- set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
- set_gdbarch_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
+ set_gdbarch_deprecated_fp_regnum (gdbarch, ARM_FP_REGNUM); /* ??? */
set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
set_gdbarch_pc_regnum (gdbarch, ARM_PC_REGNUM);
- set_gdbarch_register_byte (gdbarch, arm_register_byte);
- set_gdbarch_register_bytes (gdbarch,
- (NUM_GREGS * INT_REGISTER_RAW_SIZE
- + NUM_FREGS * FP_REGISTER_RAW_SIZE
- + NUM_SREGS * STATUS_REGISTER_SIZE));
- set_gdbarch_num_regs (gdbarch, NUM_GREGS + NUM_FREGS + NUM_SREGS);
- set_gdbarch_register_raw_size (gdbarch, arm_register_raw_size);
- set_gdbarch_register_virtual_size (gdbarch, arm_register_virtual_size);
- set_gdbarch_deprecated_max_register_raw_size (gdbarch, FP_REGISTER_RAW_SIZE);
- set_gdbarch_deprecated_max_register_virtual_size (gdbarch, FP_REGISTER_VIRTUAL_SIZE);
- set_gdbarch_register_virtual_type (gdbarch, arm_register_type);
+ set_gdbarch_num_regs (gdbarch, ARM_NUM_REGS);
+ set_gdbarch_register_type (gdbarch, arm_register_type);
+
+ /* This "info float" is FPA-specific. Use the generic version if we
+ do not have FPA. */
+ if (gdbarch_tdep (gdbarch)->have_fpa_registers)
+ set_gdbarch_print_float_info (gdbarch, arm_print_float_info);
/* Internal <-> external register number maps. */
+ set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arm_dwarf_reg_to_regnum);
set_gdbarch_register_sim_regno (gdbarch, arm_register_sim_regno);
- /* Integer registers are 4 bytes. */
- set_gdbarch_register_size (gdbarch, 4);
set_gdbarch_register_name (gdbarch, arm_register_name);
/* Returning results. */
- set_gdbarch_extract_return_value (gdbarch, arm_extract_return_value);
- set_gdbarch_store_return_value (gdbarch, arm_store_return_value);
- set_gdbarch_deprecated_store_struct_return (gdbarch, arm_store_struct_return);
- set_gdbarch_use_struct_convention (gdbarch, arm_use_struct_convention);
- set_gdbarch_extract_struct_value_address (gdbarch,
- arm_extract_struct_value_address);
-
- /* Single stepping. */
- /* XXX For an RDI target we should ask the target if it can single-step. */
- set_gdbarch_software_single_step (gdbarch, arm_software_single_step);
+ set_gdbarch_return_value (gdbarch, arm_return_value);
/* Disassembly. */
set_gdbarch_print_insn (gdbarch, gdb_print_insn_arm);
set_gdbarch_elf_make_msymbol_special (gdbarch, arm_elf_make_msymbol_special);
set_gdbarch_coff_make_msymbol_special (gdbarch,
arm_coff_make_msymbol_special);
+ set_gdbarch_record_special_symbol (gdbarch, arm_record_special_symbol);
+
+ /* Virtual tables. */
+ set_gdbarch_vbit_in_delta (gdbarch, 1);
/* Hook in the ABI-specific overrides, if they have been registered. */
gdbarch_init_osabi (info, gdbarch);
+ dwarf2_frame_set_init_reg (gdbarch, arm_dwarf2_frame_init_reg);
+
+ /* Add some default predicates. */
+ frame_unwind_append_unwinder (gdbarch, &arm_stub_unwind);
+ dwarf2_append_unwinders (gdbarch);
+ frame_unwind_append_unwinder (gdbarch, &arm_prologue_unwind);
+
/* Now we have tuned the configuration, set a few final things,
based on what the OS ABI has told us. */
+ /* If the ABI is not otherwise marked, assume the old GNU APCS. EABI
+ binaries are always marked. */
+ if (tdep->arm_abi == ARM_ABI_AUTO)
+ tdep->arm_abi = ARM_ABI_APCS;
+
+ /* We used to default to FPA for generic ARM, but almost nobody
+ uses that now, and we now provide a way for the user to force
+ the model. So default to the most useful variant. */
+ if (tdep->fp_model == ARM_FLOAT_AUTO)
+ tdep->fp_model = ARM_FLOAT_SOFT_FPA;
+
if (tdep->jb_pc >= 0)
set_gdbarch_get_longjmp_target (gdbarch, arm_get_longjmp_target);
/* Floating point sizes and format. */
- switch (info.byte_order)
+ set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
+ if (tdep->fp_model == ARM_FLOAT_SOFT_FPA || tdep->fp_model == ARM_FLOAT_FPA)
{
- case BFD_ENDIAN_BIG:
- set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big);
- set_gdbarch_double_format (gdbarch, &floatformat_ieee_double_big);
- set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big);
-
- break;
+ set_gdbarch_double_format
+ (gdbarch, floatformats_ieee_double_littlebyte_bigword);
+ set_gdbarch_long_double_format
+ (gdbarch, floatformats_ieee_double_littlebyte_bigword);
+ }
+ else
+ {
+ set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
+ set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
+ }
- case BFD_ENDIAN_LITTLE:
- set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little);
- arm_set_fp (gdbarch);
- break;
+ if (tdesc_data)
+ tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
- default:
- internal_error (__FILE__, __LINE__,
- "arm_gdbarch_init: bad byte order for float format");
- }
+ /* Add standard register aliases. We add aliases even for those
+ nanes which are used by the current architecture - it's simpler,
+ and does no harm, since nothing ever lists user registers. */
+ for (i = 0; i < ARRAY_SIZE (arm_register_aliases); i++)
+ user_reg_add (gdbarch, arm_register_aliases[i].name,
+ value_of_arm_user_reg, &arm_register_aliases[i].regnum);
return gdbarch;
}
static void
-arm_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
+arm_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (tdep == NULL)
return;
- fprintf_unfiltered (file, "arm_dump_tdep: Lowest pc = 0x%lx",
+ fprintf_unfiltered (file, _("arm_dump_tdep: Lowest pc = 0x%lx"),
(unsigned long) tdep->lowest_pc);
}
-static void
-arm_init_abi_eabi_v1 (struct gdbarch_info info,
- struct gdbarch *gdbarch)
-{
- /* Place-holder. */
-}
-
-static void
-arm_init_abi_eabi_v2 (struct gdbarch_info info,
- struct gdbarch *gdbarch)
-{
- /* Place-holder. */
-}
-
-static void
-arm_init_abi_apcs (struct gdbarch_info info,
- struct gdbarch *gdbarch)
-{
- /* Place-holder. */
-}
+extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
void
_initialize_arm_tdep (void)
struct cmd_list_element *new_set, *new_show;
const char *setname;
const char *setdesc;
- const char **regnames;
+ const char *const *regnames;
int numregs, i, j;
static char *helptext;
+ char regdesc[1024], *rdptr = regdesc;
+ size_t rest = sizeof (regdesc);
+
+ gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
- if (GDB_MULTI_ARCH)
- gdbarch_register (bfd_arch_arm, arm_gdbarch_init, arm_dump_tdep);
+ arm_objfile_data_key
+ = register_objfile_data_with_cleanup (arm_objfile_data_cleanup);
/* Register an ELF OS ABI sniffer for ARM binaries. */
gdbarch_register_osabi_sniffer (bfd_arch_arm,
bfd_target_elf_flavour,
arm_elf_osabi_sniffer);
- /* Register some ABI variants for embedded systems. */
- gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V1,
- arm_init_abi_eabi_v1);
- gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_EABI_V2,
- arm_init_abi_eabi_v2);
- gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_ARM_APCS,
- arm_init_abi_apcs);
-
/* Get the number of possible sets of register names defined in opcodes. */
num_disassembly_options = get_arm_regname_num_options ();
/* Add root prefix command for all "set arm"/"show arm" commands. */
add_prefix_cmd ("arm", no_class, set_arm_command,
- "Various ARM-specific commands.",
+ _("Various ARM-specific commands."),
&setarmcmdlist, "set arm ", 0, &setlist);
add_prefix_cmd ("arm", no_class, show_arm_command,
- "Various ARM-specific commands.",
+ _("Various ARM-specific commands."),
&showarmcmdlist, "show arm ", 0, &showlist);
/* Sync the opcode insn printer with our register viewer. */
parse_arm_disassembler_option ("reg-names-std");
- /* Begin creating the help text. */
- stb = mem_fileopen ();
- fprintf_unfiltered (stb, "Set the disassembly style.\n"
- "The valid values are:\n");
-
- /* Initialize the array that will be passed to add_set_enum_cmd(). */
+ /* Initialize the array that will be passed to
+ add_setshow_enum_cmd(). */
valid_disassembly_styles
= xmalloc ((num_disassembly_options + 1) * sizeof (char *));
for (i = 0; i < num_disassembly_options; i++)
{
numregs = get_arm_regnames (i, &setname, &setdesc, ®names);
valid_disassembly_styles[i] = setname;
- fprintf_unfiltered (stb, "%s - %s\n", setname,
- setdesc);
- /* Copy the default names (if found) and synchronize disassembler. */
+ length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
+ rdptr += length;
+ rest -= length;
+ /* When we find the default names, tell the disassembler to use
+ them. */
if (!strcmp (setname, "std"))
{
disassembly_style = setname;
- current_option = i;
- for (j = 0; j < numregs; j++)
- arm_register_names[j] = (char *) regnames[j];
set_arm_regname_option (i);
}
}
/* Mark the end of valid options. */
valid_disassembly_styles[num_disassembly_options] = NULL;
- /* Finish the creation of the help text. */
- fprintf_unfiltered (stb, "The default is \"std\".");
+ /* Create the help text. */
+ stb = mem_fileopen ();
+ fprintf_unfiltered (stb, "%s%s%s",
+ _("The valid values are:\n"),
+ regdesc,
+ _("The default is \"std\"."));
helptext = ui_file_xstrdup (stb, &length);
ui_file_delete (stb);
- /* Add the deprecated disassembly-flavor command. */
- new_set = add_set_enum_cmd ("disassembly-flavor", no_class,
- valid_disassembly_styles,
- &disassembly_style,
- helptext,
- &setlist);
- set_cmd_sfunc (new_set, set_disassembly_style_sfunc);
- deprecate_cmd (new_set, "set arm disassembly");
- deprecate_cmd (add_show_from_set (new_set, &showlist),
- "show arm disassembly");
-
- /* And now add the new interface. */
- new_set = add_set_enum_cmd ("disassembler", no_class,
- valid_disassembly_styles, &disassembly_style,
- helptext, &setarmcmdlist);
-
- set_cmd_sfunc (new_set, set_disassembly_style_sfunc);
- add_show_from_set (new_set, &showarmcmdlist);
-
- add_setshow_cmd_full ("apcs32", no_class,
- var_boolean, (char *) &arm_apcs_32,
- "Set usage of ARM 32-bit mode.",
- "Show usage of ARM 32-bit mode.",
- NULL, NULL,
- &setlist, &showlist, &new_set, &new_show);
- deprecate_cmd (new_set, "set arm apcs32");
- deprecate_cmd (new_show, "show arm apcs32");
+ add_setshow_enum_cmd("disassembler", no_class,
+ valid_disassembly_styles, &disassembly_style,
+ _("Set the disassembly style."),
+ _("Show the disassembly style."),
+ helptext,
+ set_disassembly_style_sfunc,
+ NULL, /* FIXME: i18n: The disassembly style is \"%s\". */
+ &setarmcmdlist, &showarmcmdlist);
add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
- "Set usage of ARM 32-bit mode. "
- "When off, a 26-bit PC will be used.",
- "Show usage of ARM 32-bit mode. "
- "When off, a 26-bit PC will be used.",
- NULL, NULL,
+ _("Set usage of ARM 32-bit mode."),
+ _("Show usage of ARM 32-bit mode."),
+ _("When off, a 26-bit PC will be used."),
+ NULL,
+ NULL, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
&setarmcmdlist, &showarmcmdlist);
/* Add a command to allow the user to force the FPU model. */
- new_set = add_set_enum_cmd
- ("fpu", no_class, fp_model_strings, ¤t_fp_model,
- "Set the floating point type.\n"
- "auto - Determine the FP typefrom the OS-ABI.\n"
- "softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n"
- "fpa - FPA co-processor (GCC compiled).\n"
- "softvfp - Software FP with pure-endian doubles.\n"
- "vfp - VFP co-processor.",
- &setarmcmdlist);
- set_cmd_sfunc (new_set, set_fp_model_sfunc);
- set_cmd_sfunc (add_show_from_set (new_set, &showarmcmdlist), show_fp_model);
-
- /* Add the deprecated "othernames" command. */
- deprecate_cmd (add_com ("othernames", class_obscure, arm_othernames,
- "Switch to the next set of register names."),
- "set arm disassembly");
+ add_setshow_enum_cmd ("fpu", no_class, fp_model_strings, ¤t_fp_model,
+ _("Set the floating point type."),
+ _("Show the floating point type."),
+ _("auto - Determine the FP typefrom the OS-ABI.\n\
+softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
+fpa - FPA co-processor (GCC compiled).\n\
+softvfp - Software FP with pure-endian doubles.\n\
+vfp - VFP co-processor."),
+ set_fp_model_sfunc, show_fp_model,
+ &setarmcmdlist, &showarmcmdlist);
+
+ /* Add a command to allow the user to force the ABI. */
+ add_setshow_enum_cmd ("abi", class_support, arm_abi_strings, &arm_abi_string,
+ _("Set the ABI."),
+ _("Show the ABI."),
+ NULL, arm_set_abi, arm_show_abi,
+ &setarmcmdlist, &showarmcmdlist);
+
+ /* Add two commands to allow the user to force the assumed
+ execution mode. */
+ add_setshow_enum_cmd ("fallback-mode", class_support,
+ arm_mode_strings, &arm_fallback_mode_string,
+ _("Set the mode assumed when symbols are unavailable."),
+ _("Show the mode assumed when symbols are unavailable."),
+ NULL, NULL, arm_show_fallback_mode,
+ &setarmcmdlist, &showarmcmdlist);
+ add_setshow_enum_cmd ("force-mode", class_support,
+ arm_mode_strings, &arm_force_mode_string,
+ _("Set the mode assumed even when symbols are available."),
+ _("Show the mode assumed even when symbols are available."),
+ NULL, NULL, arm_show_force_mode,
+ &setarmcmdlist, &showarmcmdlist);
/* Debugging flag. */
add_setshow_boolean_cmd ("arm", class_maintenance, &arm_debug,
- "Set ARM debugging. "
- "When on, arm-specific debugging is enabled.",
- "Show ARM debugging. "
- "When on, arm-specific debugging is enabled.",
- NULL, NULL,
+ _("Set ARM debugging."),
+ _("Show ARM debugging."),
+ _("When on, arm-specific debugging is enabled."),
+ NULL,
+ NULL, /* FIXME: i18n: "ARM debugging is %s. */
&setdebuglist, &showdebuglist);
}
projects / deliverable / binutils-gdb.git / blobdiff