case 0x5: /* data transfer */
case 0x6:
case 0x7:
+ if (bits (this_instr, 25, 27) == 0x3 && bit (this_instr, 4) == 1)
+ {
+ /* Media instructions and architecturally undefined
+ instructions. */
+ break;
+ }
+
if (bit (this_instr, 20))
{
/* load */
int nRc;
enum type_code code;
- CHECK_TYPEDEF (type);
+ type = check_typedef (type);
/* In the ARM ABI, "integer" like aggregate types are returned in
registers. For an aggregate type to be integer like, its size
struct tdesc_arch_data *tdesc_data = NULL;
int i, is_m = 0;
int vfp_register_count = 0, have_vfp_pseudos = 0, have_neon_pseudos = 0;
+ int have_wmmx_registers = 0;
int have_neon = 0;
int have_fpa_registers = 1;
const struct target_desc *tdesc = info.target_desc;
tdesc_data_cleanup (tdesc_data);
return NULL;
}
+
+ have_wmmx_registers = 1;
}
/* If we have a VFP unit, check whether the single precision registers
tdep->fp_model = fp_model;
tdep->is_m = is_m;
tdep->have_fpa_registers = have_fpa_registers;
+ tdep->have_wmmx_registers = have_wmmx_registers;
gdb_assert (vfp_register_count == 0
|| vfp_register_count == 16
|| vfp_register_count == 32);